CN110889500A - Shared data storage module, neural network processor and electronic device - Google Patents
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Abstract
The embodiment of the application provides a shared data storage module, a neural network processor and an electronic device, wherein the data storage module comprises: at least two data storage units, each for storing data; and each address decoding unit comprises at least two output ports, the number of the output ports of the address decoding unit is equal to that of the data storage units, and data output by one output port is used for being stored in one data storage unit. The embodiment of the application can improve the data processing efficiency of the neural network processor. Therefore, the data output by the address decoding unit can be stored in any data storage unit, and the storage space of the data storage module can be shared.
Description
Technical Field
The present application relates to the field of processor technologies, and in particular, to a shared data storage module, a neural network processor, and an electronic device.
Background
An Artificial Neural Network (ANN) abstracts a neuron network from an information processing perspective, establishes a certain simple model, and forms different networks according to different connection modes. These studies are commonly referred to as deep learning (deep learning), computer learning (computer learning), and the like.
In the related art, since one memory of the neural network processor is used for storing the feature map and the other memory is used for storing the training parameters, the memory storing the feature map cannot be used for storing the training parameters.
Disclosure of Invention
The embodiment of the application provides a shared data storage module, a neural network processor and electronic equipment, and the sharing of the data storage module can be realized.
The embodiment of the application discloses a shared data storage module, which comprises:
at least two data storage units, each for storing data; and
each address decoding unit comprises at least two output ports, the number of the output ports of each address decoding unit is equal to that of the data storage units, and data output by one output port is used for being stored in one data storage unit.
The embodiment of the application discloses a shared data storage module, which comprises:
at least two data storage units, each for storing data; and
each address decoding unit is used for decoding the received data into at least two data and storing all the data corresponding to one data storage unit into the data storage unit;
the number of the at least two data decoded by the address decoding unit is equal to the number of the at least two data storage units.
The embodiment of the application discloses neural network processor includes:
and the data storage module is used for storing data and is the data storage module.
The embodiment of the present application further discloses an electronic device, including:
a neural network processor, the neural network processor being as described above.
In the embodiment of the application, the number of the output ports of each address decoding unit of the shared data storage module is equal to the number of the data storage units, and one output port of each address decoding unit can correspond to one data storage unit, so that the data output by the address decoding unit can be stored in any one data storage unit, and further, the sharing of the storage space in the data storage module can be realized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below.
Fig. 1 is a schematic view of a first structure of a data storage module according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a second structure of a data storage module according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a data storage module according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a fourth structure of a data storage module according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a fifth structure of a data storage module according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of a neural network processor according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a first structural diagram of a data storage module according to an embodiment of the present disclosure, in which a data storage module 240 includes at least two data storage units 241 and at least two address decoding units 242. Because the number of the output ports of each address decoding unit 241 is equal to the number of the data storage units 241, one output port of each address decoding unit 241 can correspond to one data storage unit 241, so that the data output by the address decoding unit 241 can be stored in any data storage unit 241, and further, the storage space in the data storage module 240 can be shared.
Wherein the number of the address decoding units 242 is not greater than the number of the data storage units 241, for example, the number of the data storage units 241 is two, such as a data storage unit a and a data storage unit b, the number of the address decoding units 242 is two, such as an address decoding unit a and an address decoding unit b, and the following description takes two data storage units 241 and two address decoding units 242 as an example.
Among them, the data storage unit (Bank)241 may store data such as image data, weight data, and the like. The data stored in the data storage unit 241 may be data to be processed, or the data stored in the data storage unit 241 may be data that requires a plurality of processing units to perform processing such as arithmetic. The data stored in the data storage unit 241 may also be the processing result, or the data stored in the data storage unit 241 may be the data processed by the plurality of processing units. Note that the data actually stored in the data storage unit 241 is not limited to this, and the data storage unit 241 may store other data.
Each data storage unit 241 may be configured to store image data, weight data, and the like, for example, the data storage unit a may be configured to store image data, and the data storage unit b may be configured to store weight data, or the data storage unit a may be configured to store weight data, and the data storage unit b may be configured to store image data, so that any one data storage unit may store any one data, thereby enabling sharing among the plurality of data storage units 241 in the data storage module 240.
Here, sharing is understood to mean that any type of data can be stored in any one of the data storage units 241.
Each data storage unit 241 includes a write data port and a read data port, and can implement the functions of storing data in the data storage unit 241 through the write data port and reading data in the data storage unit 241 through the read data port. A function of storing data to the data storage unit 241 through the write data port or a function of reading data from the data storage unit 241 through the read data port, or a function of simultaneously storing data to the data storage unit 241 through the write data port and reading data from the data storage unit 241 through the read data port may be implemented.
The memory sizes of all the data storage units 241 in the embodiment of the present application are the same, for example, the memory size may be 512kb, 1024kb, and the like, and as the data storage units 241 in the embodiment of the present application may be shared, when storing large data, the data storage units 241 may be allocated to a plurality of data storage units 241 for storage, so that a phenomenon of memory resource waste caused when the data storage units 241 are set according to the maximum memory may be avoided.
In some embodiments, the memory sizes of all the data storage units 241 may be different, for example, the memory sizes of the data storage modules a, b, c and d are different.
In some embodiments, the memory sizes of all the data storage units 241 may also be partially the same, for example, the memory sizes of the data storage unit a and the data storage unit b are the same, and the memory sizes of the data storage unit c and the data storage unit d are different, or the memory sizes of the data storage unit a, the data storage unit b and the data storage unit c are the same, and the memory sizes of the data storage unit d and other data storage units are different.
Address decoding units (Address decoders) 242, each Address decoding unit 242 being configured to decode data received by it into at least two data, and store all data corresponding to one data storage unit 241 into the data storage unit 241.
Two address decoding units 242 are connected to one data storage unit 241, one address decoding unit 242 includes two output ports, the number of the output ports of one address decoding unit 242 is equal to the number of the data storage units in the data storage module 240, that is, the output port of one address decoding unit 242 corresponds to one data storage unit 241, and data output by one output port can be used for being stored in one data storage unit corresponding to the output port.
One output port of the same address decoding unit 242 corresponds to one data storage unit 241, for example, one output port of the address decoding unit a corresponds to the data storage unit a, the other output port corresponds to the data storage unit b, one output port of the address decoding unit b corresponds to the data storage unit a, and the other output port corresponds to the data storage unit b.
For example, the data output by the output port corresponding to the data storage unit a of the address decoding unit a and the data output by the output port corresponding to the data storage unit a of the address decoding unit b are stored in the data storage unit a; the data output by the output port corresponding to the address decoding unit a and the data storage unit b and the data output by the output port corresponding to the address decoding unit b and the data storage unit b are stored in the data storage unit b, so that the data in one address decoding unit a can be stored in any one data storage unit 241, and the sharing among the data storage units 241 can be realized.
One output port is used to output a type of data, and the two output ports of the same address decoding unit 242 have different data types, for example, one output port of one address decoding unit 242 is used to output a feature map, and the other output port is used to output a feature parameter.
It should be noted that the number of output ports of each address decoding unit 242 is set according to the number of data storage units 241, there are several data storage units 241 in the data storage module 240, and each address decoding unit 242 has the number of output ports corresponding to the number of data storage units 241.
Of course, in some embodiments, the number of output ports of the address decoding unit 242 may be smaller than the number of the data storage units 241, and a plurality of data storage units 241 may be implemented to store larger data.
Each address decoding unit 242 further includes three input ports, and the three input ports are respectively used for receiving signals, data and address information transmitted by an external port (port). Each address decoding unit 242 compiles two data according to the received signal, data, and address information.
For example, when the number of the external ports is two and the number of the corresponding address decoding units 242 is two, the data transmitted by the external ports can be stored in any one of the data storage units 241 through the address decoding units 242, so as to implement resource sharing in the data storage module 240.
The external port may be a port of a plurality of processing units, or may also be a port of a data bus, and as long as the port capable of storing data into the data storage unit and reading data from the data storage unit can be implemented, the protection scope of the embodiments of the present application is included.
Moreover, since the number of the address decoding units 242 corresponds to the number of the external ports, when two address decoding units 242 are provided, two different external ports can be supported to simultaneously store data in the data storage module 240, so that the bandwidth of the data storage module 240 can be increased, and the efficiency of the data storage module 240 in storing data can be improved.
In some embodiments, the number of the data storage units 241 and the address decoding units 242 may also be multiple, for example, three, four, and the like, and may be flexibly set according to actual needs.
Referring to fig. 2, fig. 2 is a schematic diagram of a second structure of a data storage module according to an embodiment of the present disclosure, in which the data storage module 240 according to the embodiment of the present disclosure may also include four data storage units 241 and two address decoding units 242, each address decoding unit a includes four output ports, and each output port corresponds to one data storage unit.
Four data storage units 241, such as: a data storage unit a, a data storage unit b, a data storage unit c and a data storage unit d, and two address decoding units 242, such as an address decoding unit a and an address decoding unit b, which are described in detail below by taking four data storage units and two address decoding units as examples.
Two address decoding units 242 are connected to one data storage unit 241, one address decoding unit 242 includes four output ports, the number of the output ports of one address decoding unit 242 is equal to the number of the data storage units in the data storage module 240, that is, one output port of one address decoding unit 242 corresponds to one data storage unit 241, for example, a first output port of each address decoding unit a corresponds to the data storage unit a, a second output port corresponds to the data storage unit b, a third output port corresponds to the data storage unit c, and a fourth output port corresponds to the data storage unit d.
And, the data outputted from one output port can be used for storing into one data storage unit corresponding to the output port. For example: the data output by the first output port corresponding to the address decoding unit a and the data storage unit a, and the data output by the first output port corresponding to the address decoding unit b and the data storage unit a are all stored in the data storage unit a, so that the data in each address decoding unit can be stored in any data storage unit 241, and the data storage units 241 can be shared.
One output port is used to output a type of data, and the four output ports of the same address decoding unit 242 have different data types, for example, a first output port of one address decoding unit 242 is used to output a feature map, and a second output port is used to output a feature parameter.
It should be noted that the number of output ports of each address decoding unit 242 is set according to the number of data storage units 241, there are several data storage units 241 in the data storage module 240, and each address decoding unit 242 has the number of output ports corresponding to the number of data storage units 241.
Of course, in some embodiments, the number of output ports of the address decoding unit 242 may be smaller than the number of the data storage units 241, and a plurality of data storage units 241 may be implemented to store larger data.
Each address decoding unit 242 further includes three input ports, and the three input ports are respectively used for receiving signals, data and address information transmitted by an external port (port). Each address decoding unit 242 compiles two data according to the received signal, data, and address information.
For example, when the number of the external ports is two and the number of the corresponding address decoding units 242 is two, the data transmitted by the external ports can be stored in any one of the data storage units 241 through the address decoding units 242, so as to implement resource sharing in the data storage module 240.
The external port may be a port of a plurality of processing units, or may also be a port of a data bus, and as long as the port capable of storing data into the data storage unit and reading data from the data storage unit can be implemented, the protection scope of the embodiments of the present application is included.
Moreover, since the number of the address decoding units 242 corresponds to the number of the external ports, when two address decoding units 242 are provided, two different external ports can be supported to simultaneously store data in the data storage module 240, so that the bandwidth of the data storage module 240 can be increased, and the efficiency of the data storage module 240 in storing data can be improved.
In some embodiments, the number of the data storage units 241 and the address decoding units 242 is not limited to the above example, for example, the number of the data storage units 241 and the number of the address decoding units 242 may also be three, four, and the like, and may be flexibly set according to actual needs.
Referring to fig. 3, fig. 3 is a schematic diagram of a third structure of a shared data storage module according to an embodiment of the present disclosure, in which the data storage module 240 according to the embodiment of the present disclosure may include four data storage units 241 and four address decoding units 242, each address decoding unit a includes four output ports, and each output port corresponds to one data storage unit.
Four data storage units 241, such as: a data storage unit a, a data storage unit b, a data storage unit c and a data storage unit d, and four address decoding units 242, such as an address decoding unit a, an address decoding unit b, an address decoding unit c and an address decoding unit d, which are described in detail below by taking four data storage units and four address decoding units as examples.
The four address decoding units 242 are all connected to one data storage unit 241, one address decoding unit 242 includes four output ports, the number of the output ports of one address decoding unit 242 is equal to the number of the data storage units in the data storage module 240, that is, the output port of one address decoding unit 242 corresponds to one data storage unit 241, for example, a first output port of each address decoding unit a corresponds to the data storage unit a, a second output port corresponds to the data storage unit b, a third output port corresponds to the data storage unit c, and a fourth output port corresponds to the data storage unit d.
And, the data outputted from one output port can be used for storing into one data storage unit corresponding to the output port. For example: the data output by the first output port corresponding to the address decoding unit a and the data storage unit a, the data output by the first output port corresponding to the address decoding unit b and the data storage unit a, the data output by the first output port corresponding to the address decoding unit c and the data storage unit a, and the data output by the first output port corresponding to the address decoding unit d and the data storage unit a are all stored in the data storage unit a, so that the data in each address decoding unit can be stored in any data storage unit 241, and the data storage units 241 can be shared.
One output port is used to output a type of data, and the four output ports of the same address decoding unit 242 have different data types, for example, a first output port of one address decoding unit 242 is used to output a feature map, and a second output port is used to output a feature parameter.
It should be noted that the number of output ports of each address decoding unit 242 is set according to the number of data storage units 241, there are several data storage units 241 in the data storage module 240, and each address decoding unit 242 has the number of output ports corresponding to the number of data storage units 241.
Of course, in some embodiments, the number of output ports of the address decoding unit 242 may be smaller than the number of the data storage units 241, and a plurality of data storage units 241 may be implemented to store larger data.
Each address decoding unit 242 further includes three input ports, and the three input ports are respectively used for receiving signals, data and address information transmitted by an external port (port). Each address decoding unit 242 compiles four data according to the received signal, data, and address information.
For example, when the number of the external ports is four and the number of the corresponding address decoding units 242 is four, the data transmitted by the external ports can be stored in any one of the data storage units 241 through the address decoding units 242, so as to implement resource sharing in the data storage module 240.
The external port may be a port of a plurality of processing units, or may also be a port of a data bus, and as long as the port capable of storing data into the data storage unit and reading data from the data storage unit can be implemented, the protection scope of the embodiments of the present application is included.
In some embodiments, the number of the data storage units 241 and the address decoding units 242 is not limited to the above example, for example, the number of the data storage units 241 and the number of the address decoding units 242 may also be three, six, eight, and the like, and may be flexibly set according to actual needs.
Referring to fig. 4, fig. 4 is a fourth schematic structural diagram of a data storage module according to an embodiment of the present disclosure, where the data storage module 240 further includes at least two data merging units 243, each data merging unit 243 includes at least two data input ends and one data output end, and each data merging unit 243 receives all data corresponding to one data storage unit 241 through the at least two data input ends and stores all data into the data storage unit 241 corresponding to the data after processing, so that the data storage module 240 can regularly process the data, the efficiency of data processing can be improved, and meanwhile, a phenomenon of data storage confusion can be avoided.
Each data merging unit 243 corresponds to one data storage unit 241, one data input end of each data merging unit 243 is connected to the output ports of all address decoding units 242 corresponding to one data storage unit 241, that is, one data merging unit 243 is connected to all address decoding units 242, and data of a plurality of address decoding units 242 is processed by one data merging unit 243, so that the data storage efficiency can be improved.
The data merging unit 243 counts data by bit or by operation, and performs a bit-wise or binocular operation, where the two numbers involved in the operation each correspond to a binary bit or. The result bit is 1 as long as one of the two corresponding bins is 1. The bitwise or operation logic is relatively simple, the operation speed is relatively high, the processing efficiency of the data merging unit 243 can be improved, and the storage efficiency of the data storage module 240 can be further improved.
One data merging unit 243 corresponds to one data storage unit 241, for example, the data merging unit a corresponds to the data storage unit a, the data merging unit b corresponds to the data storage unit b, one data decoded by the address decoding unit a is transmitted to the data merging unit a corresponding to the data storage unit a for processing, and the processed data can be transmitted to the data storage unit a for storage. The data storage module 240 can be used for storing data quickly and efficiently.
It should be noted that the number of the data merging units 243 is equal to the number of the data storage units 241, for example, when the number of the data storage units 241 is two, the number of the data merging units 243 is also two, and when the number of the data storage units 241 is four, the number of the data merging units 243 is also four.
Referring to fig. 5, fig. 5 is a fifth structural schematic diagram of a shared data storage module according to an embodiment of the present disclosure, when an external port reads data from the data storage module 240, the data storage module 240 further includes at least two data selecting units 244, each data selecting unit 244 is connected to the address decoding unit 242, and the data selecting unit 244 is configured to select corresponding data from the data storage unit 241 according to a delay signal generated by the address decoding unit 242 for output.
The number of the data selecting units 244 is equal to the number of the address decoding units 242, for example, when the number of the address decoding units 242 is two, the number of the data selecting units 244 is also two, and when the number of the address decoding units 242 is four, the number of the data selecting units 244 is also four.
In the embodiment of the present application, one data selecting unit 244 is connected to one address decoding unit 242, and when data is stored in any one of the data storage units 241 through the address decoding unit 242, data can be read from the data storage unit 241 through the address decoding unit 242 according to the data selecting unit 244, so that data can be moved from any one of the data storage units 241 through any one of the external ports, and the storage space in the data storage module 240 can be shared.
The detailed process of simultaneously moving data from a plurality of external ports to the data storage module 240 in the embodiment of the present application is as follows:
when the external port needs to store data into the data storage unit 241, the external port sends a write data signal, a write address and a write data signal to the three input ports of the address decoding unit 242 through the write data port, and each address decoding unit 242 generates a signal corresponding to each data storage unit 241 according to the number of the data storage units 241.
The data merging unit 243 receives all signals corresponding to a data storage unit 241, processes the received signals, and transmits the processed signals to the corresponding data storage unit 241 through the data output end of the data merging unit 243.
After receiving the signal transmitted by the data merging unit 243, the data storage unit 241 writes the data into the corresponding data storage unit 241 for storage.
When an external port needs to read data from the data storage unit 241, the external port transmits a read data signal to one input port of the address decoding unit 242 through a write data port, and simultaneously transmits a read address signal through the other input port, and the address decoding unit 242 generates a signal corresponding to each data storage unit 241 according to the read address signal.
The data merging unit 243 receives a signal corresponding to a data storage unit 241, processes the received signal, and transmits the processed signal to the corresponding data storage unit 241 through the data output end of the data merging unit 243.
The data storage unit 241 receives the signal transmitted by the data merge unit 243 and then provides read data.
The data selecting unit 244 selects corresponding read data according to the read delay time of the address decoding unit 242 and transmits the read data to the external port.
It should be noted that, since each data storage unit 241 includes one write data port and one read data port, there is no conflict when the data storage unit 241 reads and writes data simultaneously.
Fig. 6 shows a schematic structural diagram of a neural network processor according to an embodiment of the present application. A Neural Network Process Unit (NPU) 200 may include a data storage module 240 and a processing Unit 230. The processing units 230 are all connected to the data storage module 240, and the processing units 230 are configured to process data and store the processed data in the data storage module 240. The data storage module 240, such as the data storage module 240, is not described in detail here.
The neural network processor 200 may further include a data mover 250 and a system bus interface 270, the system bus interface 270 being coupled to a system bus, which may be a system bus of an electronic device such as a smartphone. The system bus interface 270 is connected to the system bus to enable data transmission between the processor and the memory. The system bus interface 270 may convert the internal read and write requests into bus read and write requests that conform to a bus interface protocol, such as the advanced extensible interface (AXI) protocol.
The data transfer unit 250 is connected to the system bus interface 270 and the data storage module 240, and the data transfer unit 250 is used for transferring data, and may transfer external data to the data storage module 240 or transfer data of the data storage module 240 to the outside. Such as a data mover, reads data from the system bus through the system bus interface 270 and writes the read data to the data storage module 240. The data moving unit 250 may also transmit the data buffered by the data storage module 240 to an external outgoing memory or a processor. That is, the data transfer unit 250 can realize data transfer between the internal cache data and the external storage through the system bus interface 270.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 20 may include a neural network processor 200, a system bus 400, a memory 600, and a central processor 800. The neural network processor 200, the memory 600 and the central processing unit 800 are all connected to the system bus 400, so that the neural network processor 200 and the memory 600 can realize data transmission, and the neural network processor 200 and the central processing unit 800 can realize instruction transmission.
The system bus 400 is connected to the neural network processor 200 via the system bus interface 270. The system bus 400 may be connected to the cpu 800 and the memory 600 through other system bus interfaces.
When data processing by the neural network processor 200 is required, upper layer driver software of the electronic device 20, such as the processor 800, writes the configuration of the currently required execution program into the corresponding register, for example: an operation mode, an initial value of a Program Counter (PC), a configuration parameter, and the like. Then, the data moving unit 250 reads data to be processed, such as image data and weight data, from the external memory 600 through the system bus interface 270, and writes the data to the data storage module 240.
The register is a configuration status register of the neural network processor 200, which can set an operation mode of the neural network processor 200, such as a bit width of input data, a position of a program initialization PC, and the like.
The data storage module, the neural network processor and the electronic device provided by the embodiment of the application are described in detail above. The principles and implementations of the present application are described herein using specific examples, which are presented only to aid in understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (12)
1. A shared data storage module, comprising:
at least two data storage units, each for storing data; and
each address decoding unit comprises at least two output ports, the number of the output ports of each address decoding unit is equal to that of the data storage units, and data output by one output port is used for being stored in one data storage unit.
2. The shared data storage module of claim 1, wherein the number of data storage units is four, the number of address decoding units is two, and the number of output ports of each address decoding unit is four.
3. The shared data storage module of claim 1, wherein the number of the data storage units and the number of the address decoding units are four, and the number of each address decoding unit is four.
4. The shared data storage module of any of claims 1-3, further comprising:
the data merging unit is connected with the data storage unit and all the address decoding units, each data merging unit comprises at least two data input ends and a data output end, one data input end is connected with a plurality of address decoding units, and each data merging unit receives all data corresponding to one data storage unit, processes all the data and stores all the data in the data storage unit corresponding to the data.
5. A shared data storage module, comprising:
at least two data storage units, each for storing data; and
each address decoding unit is used for decoding the received data into at least two data and storing all the data corresponding to one data storage unit into the data storage unit;
the number of the at least two data decoded by the address decoding unit is equal to the number of the at least two data storage units.
6. The shared data storage module of claim 5, wherein the number of the data storage units is four, and the number of the address decoding units is two, wherein each address decoding unit is configured to decode the data received by the address decoding unit into four data.
7. The shared data storage module of claim 6, wherein the number of the data storage units is four, and the number of the address decoding units is four, wherein each address decoding unit is configured to decode the data received by the address decoding unit into four data.
8. The shared data storage module of any of claims 5-7, further comprising:
and each data merging unit is used for processing all data corresponding to one data storage unit and storing the processed data to the data storage unit corresponding to the data.
9. The shared data storage module of any of claims 5-7, wherein when reading data to the data storage unit, the data storage module further comprises:
and the data selection unit is used for selecting corresponding data from the data storage unit according to the delay signal generated by the address decoding unit and outputting the corresponding data.
10. The shared data storage module of any of claims 5-7, wherein the memory size of all of the data storage units is the same.
11. A neural network processor, comprising:
a data storage module for storing data, the data storage module being as claimed in any one of claims 1 to 10.
12. An electronic device, comprising:
a neural network processor, as claimed in claim 11, connected to the system bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201911252997.9A CN110889500A (en) | 2019-12-09 | 2019-12-09 | Shared data storage module, neural network processor and electronic device |
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| CN104090859A (en) * | 2014-06-26 | 2014-10-08 | 北京邮电大学 | Address decoding method based on multi-valued logic circuit |
| CN108986862A (en) * | 2017-06-02 | 2018-12-11 | 瑞萨电子株式会社 | Semiconductor device and memory module |
| CN109117415A (en) * | 2017-06-26 | 2019-01-01 | 上海寒武纪信息科技有限公司 | Data-sharing systems and its data sharing method |
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| CN1060731A (en) * | 1990-10-01 | 1992-04-29 | 国际商业机器公司 | The Memory Controller direct or interleave memory accessing is used |
| CN104090859A (en) * | 2014-06-26 | 2014-10-08 | 北京邮电大学 | Address decoding method based on multi-valued logic circuit |
| CN108986862A (en) * | 2017-06-02 | 2018-12-11 | 瑞萨电子株式会社 | Semiconductor device and memory module |
| CN109117415A (en) * | 2017-06-26 | 2019-01-01 | 上海寒武纪信息科技有限公司 | Data-sharing systems and its data sharing method |
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