CN110880809A - Dual-battery selection circuit and electronic device - Google Patents

Dual-battery selection circuit and electronic device Download PDF

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Publication number
CN110880809A
CN110880809A CN201911292157.5A CN201911292157A CN110880809A CN 110880809 A CN110880809 A CN 110880809A CN 201911292157 A CN201911292157 A CN 201911292157A CN 110880809 A CN110880809 A CN 110880809A
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China
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resistor
power supply
battery power
nmos transistor
electrode
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CN201911292157.5A
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Chinese (zh)
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雷里庭
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Shanghai Wingtech Electronic Technology Co Ltd
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Shanghai Wingtech Electronic Technology Co Ltd
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Priority to CN201911292157.5A priority Critical patent/CN110880809A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/30—Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
    • Y04S20/20—End-user application control systems

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  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

The invention discloses a double-battery selection circuit, which relates to the technical field of electronic circuits and comprises a double-way switch, a first fast-switch slow-switch circuit and a second fast-switch slow-switch circuit, wherein the double-way switch is provided with two input ends and two output ends, and the two input ends are connected to a main battery power supply, a standby battery power supply and a battery switching signal through a logic circuit; the two output ends respectively output a first enable signal and a second enable signal; the main battery power supply is connected to the public output end through the first fast-switching slow-switching circuit, and the first enabling signal is connected to the enabling end of the first fast-switching slow-switching circuit; the standby battery power supply is connected to the common output end through the second fast-switching slow-switching circuit, and the second enabling signal is connected to the enabling end of the second fast-switching slow-switching circuit. The embodiment of the invention also discloses electronic equipment comprising the double-battery selection circuit. The embodiment of the invention realizes the intelligent switching of the double batteries through the matching structure of the fast-switching slow-switching circuit and the double-circuit switch.

Description

Dual-battery selection circuit and electronic device
Technical Field
The embodiment of the invention relates to the technical field of electronic circuits, in particular to a double-battery selection circuit and electronic equipment.
Background
The existing intelligent equipment is internally provided with a rechargeable battery, and along with the increasing and more powerful functions of the intelligent equipment, the electric quantity of the rechargeable battery is gradually increased so as to improve the cruising ability. In fact, situations often occur where a single battery situation affects normal operation, learning, or play. Therefore, the situation can be avoided to a great extent under the condition of double batteries, and the switching of the existing double-battery power supply mode is not intelligent enough, so that the possibility of power failure during switching is easy to occur.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a double-battery selection circuit and an electronic device, which realize intelligent switching of double batteries through a fast-switching slow-switching circuit and a matched structure of a two-way switch.
In a first aspect, an embodiment of the present invention provides a dual battery selection circuit, configured to select an output of a main battery power supply or an auxiliary battery power supply, including: the double-way switch is provided with two input ends and two output ends which are in one-to-one correspondence with the two input ends, and the two input ends are connected to a main battery power supply, a standby battery power supply and a battery switching signal through a logic circuit; the two output ends respectively output a first enable signal and a second enable signal; the main battery power supply is connected to the common output end of the double-battery selection circuit through the first fast-switch slow-switch circuit, and the first enabling signal is connected to the enabling end of the first fast-switch slow-switch circuit and used for controlling the output of the main battery power supply; the standby battery power supply is connected to the public output end through a second fast-switch slow-switch circuit, and the second enabling signal is connected to the enabling end of the second fast-switch slow-switch circuit and used for controlling the output of the standby battery power supply.
In a preferred embodiment, the two input terminals are a first input terminal and a second input terminal, respectively, and the two output terminals are a first output terminal corresponding to the first input terminal and a second output terminal corresponding to the second input terminal, respectively; the first input end and the second input end are connected to a main battery power supply, a standby battery power supply and a battery switching signal through a logic circuit; the first output end outputs a first enable signal, and the second output end outputs a second enable signal.
In a preferred embodiment, the logic circuit comprises an auxiliary power supply, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, an NMOS transistor Q11, an NMOS transistor Q12, an NMOS transistor Q13, an NMOS transistor Q14, wherein an output end of the auxiliary power supply is connected to a first input end through a resistor R15, and an output end of the auxiliary power supply is connected to a second input end through a resistor R16; the drain electrode of the NMOS transistor Q11, the gate electrode of the NMOS transistor Q12 and the drain electrode of the NMOS transistor Q13 are all connected to a first input end, the drain electrode of the NMOS transistor Q12 is connected to a second input end, and the gate electrode of the NMOS transistor Q11 is connected to a battery switching signal through a resistor R17; the grid electrode of the NMOS tube Q13 is connected to a standby battery power supply through a resistor R18; the grid electrode of the NMOS transistor Q14 is connected to a main battery power supply through a resistor R19, and the drain electrode of the NMOS transistor Q14 is connected to the grid electrode of an NMOS transistor Q13; the source electrode of the NMOS transistor Q11, the source electrode of the NMOS transistor Q12, the source electrode of the NMOS transistor Q13 and the source electrode of the NMOS transistor Q14 are all grounded.
In a preferred embodiment, the first fast-switching slow-switching circuit comprises an NMOS transistor Q15, an NMOS transistor Q5, a PMOS transistor Q1, a PMOS transistor Q2, an NPN transistor Q3, a PNP transistor Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, and a resistor R7; the grid electrode of the NMOS transistor Q15 and the grid electrode of the NMOS transistor Q5 are both connected to a first enabling signal, and the source electrode of the NMOS transistor Q15 and the source electrode of the NMOS transistor Q5 are both grounded; the drain electrode of the NMOS tube Q15 is connected to a main battery power supply through a resistor R1; the drain electrode of the PMOS tube Q1 is connected to a main battery power supply, the source electrode of the PMOS tube Q1 is connected to the source electrode of the PMOS tube Q2, and the drain electrode of the PMOS tube Q2 is connected to a common output end; the drain electrode of the NMOS transistor Q5 is connected between the source electrode of the PMOS transistor Q1 and the source electrode of the PMOS transistor Q2 through a resistor R7 and a resistor R6 in sequence; the grid electrode of the PMOS transistor Q1 and the grid electrode of the PMOS transistor Q2 are connected between the resistor R6 and the resistor R7; the base electrode of the NPN triode Q3 is connected between the resistor R1 and the drain electrode of the NMOS transistor Q15 through a resistor R2, the base electrode of the NPN triode Q3 is connected to the emitter electrode of the NPN triode Q3 through a resistor R3, and the emitter electrode of the NPN triode Q3 is grounded; the collector of the NPN triode Q3 is connected to the base of a PNP triode Q4 through a resistor R4, a resistor R5 is connected between the base of the PNP triode Q4 and the emitter of the PNP triode Q4, the emitter of the PNP triode Q4 is also connected between the source of a PMOS transistor Q1 and the source of the PMOS transistor Q2, and the collector of the PNP triode Q4 is connected between the resistor R6 and the resistor R7.
In a preferred embodiment, the second fast-switching slow-switching circuit includes an NMOS transistor Q16, an NMOS transistor Q10, a PMOS transistor Q6, a PMOS transistor Q7, an NPN transistor Q8, a PNP transistor Q9, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a resistor R14; the grid electrode of the NMOS transistor Q16 and the grid electrode of the NMOS transistor Q10 are both connected to a second enabling signal, and the source electrode of the NMOS transistor Q16 and the source electrode of the NMOS transistor Q10 are both grounded; the drain electrode of the NMOS tube Q16 is connected to a standby battery power supply through a resistor R8; the drain electrode of the PMOS tube Q6 is connected to a standby battery power supply, the source electrode of the PMOS tube Q6 is connected to the source electrode of the PMOS tube Q7, and the drain electrode of the PMOS tube Q7 is connected to a common output end; the drain electrode of the NMOS transistor Q10 is connected between the source electrode of the PMOS transistor Q6 and the source electrode of the PMOS transistor Q7 through a resistor R14 and a resistor R13 in sequence; the grid electrode of the PMOS transistor Q6 and the grid electrode of the PMOS transistor Q7 are connected between the resistor R13 and the resistor R14; the base electrode of the NPN triode Q8 is connected between the resistor R8 and the drain electrode of the NMOS transistor Q16 through a resistor R9, the base electrode of the NPN triode Q8 is connected to the emitter electrode of the NPN triode Q8 through a resistor R10, and the emitter electrode of the NPN triode Q8 is grounded; the collector of the NPN triode Q8 is connected to the base of a PNP triode Q9 through a resistor R11, a resistor R12 is connected between the base of the PNP triode Q9 and the emitter of the PNP triode Q9, the emitter of the PNP triode Q9 is also connected between the source of a PMOS transistor Q6 and the source of the PMOS transistor Q7, and the collector of the PNP triode Q9 is connected between the resistor R13 and the resistor R14.
In a preferred embodiment, the battery switching signal is generated by the EC or the AP;
when no charger charges the main battery power supply and the standby battery power supply, if the electric quantity of the main battery power supply is greater than a first preset threshold value, the battery switching signal is at a low level; if the electric quantity of the main battery power supply is smaller than a first preset threshold value and the electric quantity of the standby battery power supply is larger than a second preset threshold value, the battery switching signal is at a high level.
In a preferred embodiment, when there is a charger, then:
when the main battery power supply is in place and the electric quantity of the main battery power supply is smaller than a third preset threshold value, the battery switching signal controls the charger to charge the main battery power supply;
when the standby battery power supply is in place and the following optional conditions are met, the battery switching signal controls the charger to charge the standby battery power supply:
condition 1: the main battery power supply is not in place, and the electric quantity of the standby battery power supply is smaller than a fourth preset threshold value;
condition 2: the electric quantity of the main battery power supply is greater than or equal to a third preset threshold, and the electric quantity of the standby battery power supply is less than a fourth preset threshold.
In a second aspect, an embodiment of the present invention provides an electronic device, which includes the dual battery selection circuit according to the first aspect of the present invention.
Compared with the prior art, the embodiment of the invention realizes intelligent switching of double batteries through the matching structure of the fast-switching slow-switching circuit and the double-way switch.
Drawings
Fig. 1 is a circuit schematic diagram of a two-way switch of embodiment 1;
FIG. 2 is a schematic circuit diagram of a main battery power supply of embodiment 1;
fig. 3 is a schematic circuit diagram of the backup battery power supply of embodiment 1.
Detailed description of the preferred embodiments
The embodiments of the present invention are further described below with reference to the drawings and the specific embodiments, and it should be noted that, in the premise of no conflict, any combination between the embodiments or technical features described below may form a new embodiment. Except as specifically noted, the materials and equipment used in this example are commercially available.
Example 1:
referring to fig. 1-3, a dual battery selection circuit for selecting an output of a main battery power supply (VBATT _ M) or a backup battery power supply (VBATT _ SEC) includes: the dual-way switch is provided with two input ends and two output ends which are in one-to-one correspondence with the two input ends, and the two input ends are connected to a main battery power supply, a standby battery power supply and a battery switching signal (BATT _ SW) through a logic circuit; the two output ends respectively output a first enable signal (VBATT _ M) and a second enable signal (VBATT _ SEC); the main battery power supply is connected to the common output end of the double-battery selection circuit through the first fast-switch slow-switch circuit, and the first enabling signal is connected to the enabling end of the first fast-switch slow-switch circuit and used for controlling the output of the main battery power supply; the main battery power supply is connected to the public output end through the second fast-switching slow-switching circuit, and the second enabling signal is connected to the enabling end of the second fast-switching slow-switching circuit and used for controlling the output of the standby battery power supply.
The two-way switch comprises a two-way selection chip U1, two input ends of the two-way selection chip U1 are a first input end (1Z) and a second input end (2Z), and two output ends of the two-way selection chip U1 are a first output end (1Y) corresponding to the first input end, the level of the first output end follows 1Z, and a second output end (2Y) corresponding to the second input end, the level of the second output end follows 2Z. The first input end and the second input end are connected to a main battery power supply, a standby battery power supply and a battery switching signal through a logic circuit; the first output terminal outputs a first enable signal, and the second output terminal outputs a second enable signal.
The two-way select chip U1 also has enable pins (1E and 2E) that are active high. The enable pin is directly connected to the auxiliary power supply.
Referring to fig. 1, the logic circuit includes an auxiliary power supply (5V _ VCC), a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, an NMOS transistor Q11, an NMOS transistor Q12, an NMOS transistor Q13, an NMOS transistor Q14, an output terminal of the auxiliary power supply is connected to a first input terminal through a resistor R15, and an output terminal of the auxiliary power supply is connected to a second input terminal through a resistor R16; the drain electrode of the NMOS tube Q11, the grid electrode of the NMOS tube Q12 and the drain electrode of the NMOS tube Q13 are all connected to the first input end, the drain electrode of the NMOS tube Q12 is connected to the second input end, and the grid electrode of the NMOS tube Q11 is connected to a battery switching signal through a resistor R17; the grid of the NMOS tube Q13 is connected to the standby battery power supply through a resistor R18; the grid electrode of the NMOS tube Q14 is connected to a main battery power supply through a resistor R19, and the drain electrode of the NMOS tube Q14 is connected to the grid electrode of the NMOS tube Q13; the source electrode of the NMOS transistor Q11, the source electrode of the NMOS transistor Q12, the source electrode of the NMOS transistor Q13 and the source electrode of the NMOS transistor Q14 are all grounded.
The battery switching signal is generated by the EC or the AP. EC (embedded Controller) is widely used in notebook computers, tablet computers and various industrial personal computers, and is also called KBC (keyboard Controller) in notebook computers and tablet computers. The EC is high in the system. The EC controls the timing of most important signals during system start-up. After the computer is started, the EC controls equipment such as a keyboard, an indicator light, a fan, a touch panel and the like. In addition, the EC also controls the standby, dormant and other states of the system; the ap (wireless Access point) is a wireless Access point, and can receive battery power and generate a battery switching signal according to the battery power.
When no charger is used for charging the main battery power supply and the backup battery power supply, if the electric quantity of the main battery power supply is greater than a first preset threshold (for example, the first preset threshold is set to be 5% of the total electric quantity of the main battery power supply), the battery switching signal is at a low level; if the electric quantity of the main battery power supply is smaller than the first preset threshold value and the electric quantity of the backup battery power supply is larger than the second preset threshold value (for example, the second preset threshold value is set to be 5% of the total electric quantity of the backup battery power supply), the battery switching signal is at a high level, namely the battery switching signal defaults to be at a low level.
The first and second output operation truth tables are shown in table 1:
TABLE 1 truth table
VBATT_M VBATT_SEC BATT_SW 1Y 2Y
1 0 0 1 0
1 1 0 1 0
0 1 0 0 1
0 0 0 1 0
1 0 1 0 1
1 1 1 0 1
0 1 1 0 1
0 0 1 0 1
Taking the example that the main battery power supply is at a high level, the backup battery power supply is at a high level, and the battery switching signal is at a high level, the main battery power supply is at a high level, so that the NMOS transistor Q14 is turned on, thereby pulling down the voltage of the gate of the NMOS transistor Q13, so that the NMOS transistor Q13 is turned off, the battery switching signal is at a high level, so that the NMOS transistor Q11 is turned on, the level of 1Z is pulled down to a low level, and 1Y is also at a low level, because 1Z is at a low level, the NMOS transistor Q12 is turned off, and because 2Z is at a high level, 2Y is also at a high level.
When a charger is present, the charger can charge the main battery power supply and the backup battery power supply, then:
when the main battery power supply is in place and the electric quantity of the main battery power supply is smaller than a third preset threshold (for example, the third preset threshold is 90% of the total electric quantity of the main battery power supply), the battery switching signal controls the charger to charge the main battery power supply.
When the standby battery power supply is in place and the following optional conditions are met, the battery switching signal controls the charger to charge the standby battery power supply:
condition 1: the main battery power supply is not in place, and the electric quantity of the standby battery power supply is smaller than a fourth preset threshold value;
condition 2: the main battery power is greater than or equal to a third predetermined threshold, and the backup battery power is less than a fourth predetermined threshold (e.g., the fourth predetermined threshold is 90% of the total power of the backup battery).
Electronic switches are respectively arranged between the charger and the main battery power supply and between the charger and the standby battery power supply, and the switches of the electronic switches are controlled through battery switching signals, for example, a PMOS (P-channel metal oxide semiconductor) tube is arranged between the charger and the main battery power supply, and when the battery switching signals are low level, the charger charges the main battery power supply; and an NMOS tube is arranged between the charger and the standby battery power supply, and the charger charges the standby battery power supply when the battery switching signal is at a low level.
Referring to fig. 2, the first fast turn-off slow turn-on circuit includes an NMOS transistor Q15, an NMOS transistor Q5, a PMOS transistor Q1, a PMOS transistor Q2, an NPN transistor Q3, a PNP transistor Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, and a resistor R7; the grid electrode of the NMOS transistor Q15 and the grid electrode of the NMOS transistor Q5 are both connected to a first enabling signal, and the source electrode of the NMOS transistor Q15 and the source electrode of the NMOS transistor Q5 are both grounded; the drain electrode of the NMOS tube Q15 is connected to a main battery power supply through a resistor R1; the drain electrode of the PMOS tube Q1 is connected to a main battery power supply, the source electrode of the PMOS tube Q1 is connected to the source electrode of the PMOS tube Q2, and the drain electrode of the PMOS tube Q2 is connected to a common output end; the drain electrode of the NMOS tube Q5 is connected between the source electrode of the PMOS tube Q1 and the source electrode of the PMOS tube Q2 through a resistor R7 and a resistor R6 in sequence; the grid electrode of the PMOS transistor Q1 and the grid electrode of the PMOS transistor Q2 are connected between the resistor R6 and the resistor R7; the base electrode of the NPN triode Q3 is connected between the resistor R1 and the drain electrode of the NMOS transistor Q15 through a resistor R2, the base electrode of the NPN triode Q3 is connected to the emitter electrode of the NPN triode Q3 through a resistor R3, and the emitter electrode of the NPN triode Q3 is grounded; the collector of NPN triode Q3 is connected to the base of PNP triode Q4 through resistor R4, resistor R5 is connected between the base of PNP triode Q4 and the emitter of PNP triode Q4, the emitter of PNP triode Q4 is also connected between the source of PMOS transistor Q1 and the source of PMOS transistor Q2, and the collector of PNP triode Q4 is connected between resistor R6 and resistor R7.
When the MAIN battery power source is on (i.e., there is a voltage output available) and V _ MAIN is high: the NMOS tube Q5 is connected with the NMOS tube Q15, the voltage of the resistor R6 and the resistor R7 is divided, VGS of the PMOS tube Q1 and VGS of the PMOS tube Q2 are both negative potential, the PMOS tube Q1 is connected with the PMOS tube Q2, the common output end is directly connected with the main battery power supply, and the main battery power supply supplies power to the load through the common output end. When V _ MAIN changes from high to low: the NMOS tube Q5 and the NMOS tube Q15 are cut off, the resistor R2, the resistor R1 and the resistor R3 divide voltage, the NPN triode Q3 is conducted, then the resistor R5 and the resistor R4 divide voltage, at the moment, the PNP triode Q4 is conducted, the voltage difference between the two ends of the resistor R6 is discharged to 0V instantly, and therefore the PMOS tube Q1 and the PMOS tube Q2 are cut off quickly, and the purpose of quick switching is achieved.
Referring to fig. 3, the second fast turn-off slow turn-on circuit includes an NMOS transistor Q16, an NMOS transistor Q10, a PMOS transistor Q6, a PMOS transistor Q7, an NPN transistor Q8, a PNP transistor Q9, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a resistor R14; the grid electrode of the NMOS transistor Q16 and the grid electrode of the NMOS transistor Q10 are both connected to a second enabling signal, and the source electrode of the NMOS transistor Q16 and the source electrode of the NMOS transistor Q10 are both grounded; the drain electrode of the NMOS tube Q16 is connected to a standby battery power supply through a resistor R8; the drain electrode of the PMOS tube Q6 is connected to a standby battery power supply, the source electrode of the PMOS tube Q6 is connected to the source electrode of the PMOS tube Q7, and the drain electrode of the PMOS tube Q7 is connected to the common output end; the drain electrode of the NMOS tube Q10 is connected between the source electrode of the PMOS tube Q6 and the source electrode of the PMOS tube Q7 through a resistor R14 and a resistor R13 in sequence; the grid electrode of the PMOS transistor Q6 and the grid electrode of the PMOS transistor Q7 are connected between the resistor R13 and the resistor R14; the base electrode of the NPN triode Q8 is connected between the resistor R8 and the drain electrode of the NMOS transistor Q16 through a resistor R9, the base electrode of the NPN triode Q8 is connected to the emitter electrode of the NPN triode Q8 through a resistor R10, and the emitter electrode of the NPN triode Q8 is grounded; the collector of NPN triode Q8 is connected to the base of PNP triode Q9 through resistor R11, resistor R12 is connected between the base of PNP triode Q9 and the emitter of PNP triode Q9, the emitter of PNP triode Q9 is also connected between the source of PMOS transistor Q6 and the source of PMOS transistor Q7, and the collector of PNP triode Q9 is connected between resistor R13 and resistor R14.
When the backup battery power is on (i.e., there is a voltage output available) and V _ SEC is high: the NMOS transistor Q10 is connected with the NMOS transistor Q16, the voltage of the resistor R13 and the resistor R14 is divided, VGS of the PMOS transistor Q6 and VGS of the PMOS transistor Q7 are both negative potential, the PMOS transistor Q6 is connected with the PMOS transistor Q7, the common output end and the standby battery power supply are directly connected, and the standby battery power supply supplies power to the load through the common output end. When V _ SEC changes from high to low: the NMOS tube Q10 and the NMOS tube Q16 are cut off, the resistor R9, the resistor R8 and the resistor R10 divide voltage, the NPN triode Q8 is conducted, then the resistor R12 and the resistor R11 divide voltage, at the moment, the PNP triode Q9 is conducted, the voltage difference between the two ends of the resistor R13 is discharged to 0V instantly, and therefore the PMOS tube Q6 and the PMOS tube Q7 are cut off quickly, and the purpose of quick switching is achieved.
Example 2:
embodiment 2 discloses an electronic device, which may be a notebook computer, a tablet computer, a mobile phone, or a mobile power supply. In addition to the dual battery selection circuit in the above embodiment, the electronic device further includes necessary components, such as a PCB board for mounting components of the dual battery selection circuit and a housing for mounting the PCB board, an output interface, an indicator light, a display screen, etc., and may further include other components, such as a heat sink, etc., as needed.
The above embodiments are only preferred embodiments of the present invention, and the scope of the embodiments of the present invention should not be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the embodiments of the present invention are within the scope of the claims of the embodiments of the present invention.

Claims (8)

1. A dual battery selection circuit for selecting an output of a main battery power supply or a backup battery power supply, comprising: the double-way switch is provided with two input ends and two output ends which are in one-to-one correspondence with the two input ends, and the two input ends are connected to a main battery power supply, a standby battery power supply and a battery switching signal through a logic circuit; the two output ends respectively output a first enable signal and a second enable signal; the main battery power supply is connected to the common output end of the double-battery selection circuit through the first fast-switch slow-switch circuit, and the first enabling signal is connected to the enabling end of the first fast-switch slow-switch circuit and used for controlling the output of the main battery power supply; the standby battery power supply is connected to the public output end through a second fast-switch slow-switch circuit, and the second enabling signal is connected to the enabling end of the second fast-switch slow-switch circuit and used for controlling the output of the standby battery power supply.
2. The dual cell selection circuit of claim 1, wherein the two input terminals are a first input terminal and a second input terminal, respectively, and the two output terminals are a first output terminal corresponding to the first input terminal and a second output terminal corresponding to the second input terminal, respectively; the first input end and the second input end are connected to a main battery power supply, a standby battery power supply and a battery switching signal through a logic circuit; the first output end outputs a first enable signal, and the second output end outputs a second enable signal.
3. The dual battery selection circuit of claim 2, wherein the logic circuit includes an auxiliary power supply, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, an NMOS transistor Q11, an NMOS transistor Q12, an NMOS transistor Q13, an NMOS transistor Q14, an output of the auxiliary power supply being connected to a first input terminal through a resistor R15, an output of the auxiliary power supply being connected to a second input terminal through a resistor R16; the drain electrode of the NMOS transistor Q11, the gate electrode of the NMOS transistor Q12 and the drain electrode of the NMOS transistor Q13 are all connected to a first input end, the drain electrode of the NMOS transistor Q12 is connected to a second input end, and the gate electrode of the NMOS transistor Q11 is connected to a battery switching signal through a resistor R17; the grid electrode of the NMOS tube Q13 is connected to a standby battery power supply through a resistor R18; the grid electrode of the NMOS transistor Q14 is connected to a main battery power supply through a resistor R19, and the drain electrode of the NMOS transistor Q14 is connected to the grid electrode of an NMOS transistor Q13; the source electrode of the NMOS transistor Q11, the source electrode of the NMOS transistor Q12, the source electrode of the NMOS transistor Q13 and the source electrode of the NMOS transistor Q14 are all grounded.
4. The dual-battery selection circuit of claim 1, wherein the first fast-off slow-on circuit comprises an NMOS transistor Q15, an NMOS transistor Q5, a PMOS transistor Q1, a PMOS transistor Q2, an NPN transistor Q3, a PNP transistor Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7; the grid electrode of the NMOS transistor Q15 and the grid electrode of the NMOS transistor Q5 are both connected to a first enabling signal, and the source electrode of the NMOS transistor Q15 and the source electrode of the NMOS transistor Q5 are both grounded; the drain electrode of the NMOS tube Q15 is connected to a main battery power supply through a resistor R1; the drain electrode of the PMOS tube Q1 is connected to a main battery power supply, the source electrode of the PMOS tube Q1 is connected to the source electrode of the PMOS tube Q2, and the drain electrode of the PMOS tube Q2 is connected to a common output end; the drain electrode of the NMOS transistor Q5 is connected between the source electrode of the PMOS transistor Q1 and the source electrode of the PMOS transistor Q2 through a resistor R7 and a resistor R6 in sequence; the grid electrode of the PMOS transistor Q1 and the grid electrode of the PMOS transistor Q2 are connected between the resistor R6 and the resistor R7; the base electrode of the NPN triode Q3 is connected between the resistor R1 and the drain electrode of the NMOS transistor Q15 through a resistor R2, the base electrode of the NPN triode Q3 is connected to the emitter electrode of the NPN triode Q3 through a resistor R3, and the emitter electrode of the NPN triode Q3 is grounded; the collector of the NPN triode Q3 is connected to the base of a PNP triode Q4 through a resistor R4, a resistor R5 is connected between the base of the PNP triode Q4 and the emitter of the PNP triode Q4, the emitter of the PNP triode Q4 is also connected between the source of a PMOS transistor Q1 and the source of the PMOS transistor Q2, and the collector of the PNP triode Q4 is connected between the resistor R6 and the resistor R7.
5. The dual battery selection circuit of claim 1, wherein the second fast turn-off slow turn-on circuit comprises an NMOS transistor Q16, an NMOS transistor Q10, a PMOS transistor Q6, a PMOS transistor Q7, an NPN transistor Q8, a PNP transistor Q9, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14; the grid electrode of the NMOS transistor Q16 and the grid electrode of the NMOS transistor Q10 are both connected to a second enabling signal, and the source electrode of the NMOS transistor Q16 and the source electrode of the NMOS transistor Q10 are both grounded; the drain electrode of the NMOS tube Q16 is connected to a standby battery power supply through a resistor R8; the drain electrode of the PMOS tube Q6 is connected to a standby battery power supply, the source electrode of the PMOS tube Q6 is connected to the source electrode of the PMOS tube Q7, and the drain electrode of the PMOS tube Q7 is connected to a common output end; the drain electrode of the NMOS transistor Q10 is connected between the source electrode of the PMOS transistor Q6 and the source electrode of the PMOS transistor Q7 through a resistor R14 and a resistor R13 in sequence; the grid electrode of the PMOS transistor Q6 and the grid electrode of the PMOS transistor Q7 are connected between the resistor R13 and the resistor R14; the base electrode of the NPN triode Q8 is connected between the resistor R8 and the drain electrode of the NMOS transistor Q16 through a resistor R9, the base electrode of the NPN triode Q8 is connected to the emitter electrode of the NPN triode Q8 through a resistor R10, and the emitter electrode of the NPN triode Q8 is grounded; the collector of the NPN triode Q8 is connected to the base of a PNP triode Q9 through a resistor R11, a resistor R12 is connected between the base of the PNP triode Q9 and the emitter of the PNP triode Q9, the emitter of the PNP triode Q9 is also connected between the source of a PMOS transistor Q6 and the source of the PMOS transistor Q7, and the collector of the PNP triode Q9 is connected between the resistor R13 and the resistor R14.
6. The dual battery selection circuit of any of claims 1-5, wherein the battery switching signal is generated by an EC or an AP;
when no charger charges the main battery power supply and the standby battery power supply, if the electric quantity of the main battery power supply is greater than a first preset threshold value, the battery switching signal is at a low level; if the electric quantity of the main battery power supply is smaller than a first preset threshold value and the electric quantity of the standby battery power supply is larger than a second preset threshold value, the battery switching signal is at a high level.
7. The dual battery selection circuit of claim 6, wherein when there is a charger, then:
when the main battery power supply is in place and the electric quantity of the main battery power supply is smaller than a third preset threshold value, the battery switching signal controls the charger to charge the main battery power supply;
when the standby battery power supply is in place and the following optional conditions are met, the battery switching signal controls the charger to charge the standby battery power supply:
condition 1: the main battery power supply is not in place, and the electric quantity of the standby battery power supply is smaller than a fourth preset threshold value;
condition 2: the electric quantity of the main battery power supply is greater than or equal to a third preset threshold, and the electric quantity of the standby battery power supply is less than a fourth preset threshold.
8. An electronic device, characterized in that it comprises a dual battery selection circuit according to any of claims 1-7.
CN201911292157.5A 2019-12-16 2019-12-16 Dual-battery selection circuit and electronic device Pending CN110880809A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080150362A1 (en) * 2006-12-26 2008-06-26 Hon Hai Precision Industry Co., Ltd. Switch-mode power supply
CN107166648A (en) * 2017-05-22 2017-09-15 青岛海尔空调器有限总公司 A kind of air conditioner supply self adaptation control device and air conditioner
CN208028649U (en) * 2018-02-01 2018-10-30 深圳市迈迪杰电子科技有限公司 A kind of alternative power supply circuit
CN208508605U (en) * 2018-05-31 2019-02-15 烽火通信科技股份有限公司 A kind of main secondary power switching circuit
CN211183521U (en) * 2019-12-16 2020-08-04 上海闻泰电子科技有限公司 Dual-battery selection circuit and electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080150362A1 (en) * 2006-12-26 2008-06-26 Hon Hai Precision Industry Co., Ltd. Switch-mode power supply
CN107166648A (en) * 2017-05-22 2017-09-15 青岛海尔空调器有限总公司 A kind of air conditioner supply self adaptation control device and air conditioner
CN208028649U (en) * 2018-02-01 2018-10-30 深圳市迈迪杰电子科技有限公司 A kind of alternative power supply circuit
CN208508605U (en) * 2018-05-31 2019-02-15 烽火通信科技股份有限公司 A kind of main secondary power switching circuit
CN211183521U (en) * 2019-12-16 2020-08-04 上海闻泰电子科技有限公司 Dual-battery selection circuit and electronic device

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