CN110880469B - Optimization method of silicon wafer alignment mark layout - Google Patents
Optimization method of silicon wafer alignment mark layout Download PDFInfo
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- CN110880469B CN110880469B CN201911178873.0A CN201911178873A CN110880469B CN 110880469 B CN110880469 B CN 110880469B CN 201911178873 A CN201911178873 A CN 201911178873A CN 110880469 B CN110880469 B CN 110880469B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/682—Mask-wafer alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Abstract
A method for optimizing the layout of silicon chip alignment marks comprises initializing the number of alignment marks, and selecting the field lattice where the alignment marks are located; optimizing the field lattice where the alignment mark is located according to the deformation data of the silicon wafer; optimizing the position of the alignment mark in the field grid; and calculating the minimum number of the alignment marks, namely finishing the layout optimization of the silicon chip alignment marks. The invention provides the optimal alignment mark position through an optimization method, thereby improving the alignment performance of the overlay; the least number of the alignment mark measurement is given by the optimization method, so that the measurement time of the alignment system is reduced, and the possibility of improving the yield is provided.
Description
Technical Field
The invention belongs to the technical field of integrated circuits or other precision manufacturing, and particularly relates to a method for optimizing the layout of a silicon wafer alignment mark.
Background
In the field of integrated circuit manufacturing, mask patterns are copied onto silicon wafers in a certain proportion by using a photoetching device. In the photolithography process, mask silicon wafer alignment is one of the most critical steps. Typically, the alignment marks are exposed with the circuit pattern on the mask in scribe lanes at the edges of the field cells, such as in the upper right hand corner of the field cells (as shown in fig. 2). And before the next layer of pattern is exposed, the position of the pattern to be exposed on the silicon wafer is calculated by measuring the position of the alignment mark on the silicon wafer, so that the precise alignment between the two layers of patterns is realized. Since it takes a long time to measure more alignment marks, the yield is affected. Therefore, to balance yield and alignment accuracy, it is currently common to choose to measure tens of alignment marks. However, a silicon wafer to be exposed generally has a certain degree of deformation before entering a lithography machine, when the deviation between the actual silicon wafer surface and the ideal plane is larger, the error of the silicon wafer surface fitted by an alignment algorithm is larger, and the accuracy of an alignment model strongly depends on the number of alignment marks and the positions of the marks. In order to better fit the silicon surface and reduce the influence of the silicon deformation on the alignment model, the optimal alignment mark position must be designed. In particular, with the continuous decrease of process nodes, the EUV (extreme ultraviolet) lithography technology has become a necessary trend to realize process nodes below 10 nm. EUV lithography equipment is more critical to alignment accuracy. Therefore, the method has great significance for reducing grid correction errors caused by silicon wafer deformation and improving the accuracy of the alignment model.
In order to solve the problem of low fitting accuracy of an alignment grid correction model caused by silicon wafer deformation, the invention provides a silicon wafer alignment mark layout optimization method, which realizes the distribution of alignment marks on a silicon wafer surface and the reasonable optimization of the number of the alignment marks.
Disclosure of Invention
It is therefore one of the primary objectives of the claimed invention to provide a method for optimizing the layout of silicon wafer alignment marks, so as to at least partially solve at least one of the above-mentioned problems.
In order to achieve the above object, the present invention provides a method for optimizing the layout of silicon wafer alignment marks, comprising:
initializing the number of the alignment marks, and selecting a field grid where the alignment marks are located;
optimizing the field lattice where the alignment mark is located according to the deformation data of the silicon wafer;
optimizing the position of the alignment mark in the field grid;
and calculating the minimum number of the alignment marks, namely finishing the layout optimization of the silicon chip alignment marks.
Based on the technical scheme, the optimization method of the silicon wafer alignment mark layout has at least one of the following advantages compared with the prior art:
1. the invention provides the optimal alignment mark position through an optimization method, thereby improving the alignment performance of the overlay;
2. the invention gives the least number of measurement of the alignment marks by the optimization method, thereby reducing the measurement time of the alignment system and providing possibility for improving the yield.
Drawings
FIG. 1 is a flow chart of a method for optimizing the layout of silicon wafer alignment marks according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a layout of field patterns and alignment marks in a silicon wafer according to an embodiment of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
The invention discloses an optimization method of silicon wafer alignment mark layout, which comprises the following steps:
initializing the number of the alignment marks, and selecting a field grid where the alignment marks are located;
optimizing the field lattice where the alignment mark is located according to the deformation data of the silicon wafer;
optimizing the position of the alignment mark in the field grid;
and calculating the minimum number of the alignment marks, namely finishing the layout optimization of the silicon chip alignment marks.
In some embodiments of the present invention, the method for optimizing the field pattern in which the alignment mark is located includes performing least square fitting according to the alignment mark measurement value and the alignment mark actual position value, traversing the field patterns on the silicon wafer, and selecting a combination with the smallest fitting error as the optimized field pattern in which the alignment mark is located.
In some embodiments of the invention, the alignment mark measurements are measured directly.
In some embodiments of the present invention, the actual position value of the alignment mark is obtained by analyzing silicon wafers in the same batch or in the same process flow, obtaining deformation data of the silicon wafers, and then performing an interpolation algorithm.
In some embodiments of the invention, the interpolation algorithm comprises a polynomial interpolation algorithm, a newton interpolation algorithm, a spline interpolation algorithm.
In some embodiments of the present invention, optimizing the position of the alignment mark in the field grid specifically comprises:
design value (x) for aligning the position of the mark in the exposure field gridm，ym) As a variable, the sum of squared errors E ═ Σ (R) is calculated by an optimization algorithmx-Mx)2+∑(Ry-My)2When E is minimum, the optimal mark position (x) is obtainedm，ym)；
Wherein (M)x(xm)，My(ym) Is a measure of the exposure field grid in which the alignment mark is located.
In some embodiments of the invention, the optimization algorithm comprises a least squares method.
In some embodiments of the present invention, calculating the minimum number of alignment marks comprises:
and traversing the selected grids according to the optimized grid where the alignment mark is positioned and the position of the optimized alignment mark in the grid, sequentially reducing the number of the alignment marks, and selecting the combination which meets an error threshold and has the smallest number of the alignment marks, so as to obtain the optimal number of the alignment marks.
In some embodiments of the invention, the error threshold is determined from an alignment error budget.
The technical solution of the present invention is further illustrated by the following specific embodiments in conjunction with the accompanying drawings. It should be noted that the following specific examples are given by way of illustration only and the scope of the present invention is not limited thereto.
In the method for optimizing the layout of the silicon wafer alignment marks, the deformation of the silicon wafer is considered, and a set of complete optimization process is provided by fitting a measured value and an actual value through a least square method. The method comprises the steps of optimizing a field lattice where an alignment mark is located, optimizing the position of the alignment mark in the field lattice, minimizing the number of the alignment marks, and giving the optimal number and position distribution of the alignment marks.
The alignment system selects a limited number of alignment marks on the silicon wafer, measures the positions of the alignment marks, calculates the position of a field to be exposed through an alignment algorithm, and finally moves the silicon wafer stage to a specified position for exposure. Because the fitting accuracy of the alignment model is influenced by the deformation of the real silicon wafer surface to a certain degree, the deformation factor of the silicon wafer is necessary to be considered, the distribution of the alignment marks on the silicon wafer surface is optimized, and the fitting accuracy is improved. The optimization process is shown in fig. 1, and specifically includes the following steps:
the first step is as follows: initializing the number N of the alignment marks, and initially selecting the positions of the exposure field grids where the alignment marks are located.
And setting the number N of the alignment marks, and primarily selecting the positions of the exposure field grids where the alignment marks are located, such as the exposure field grids close to the edge of the silicon wafer.
The second step is that: and optimizing the field lattice where the alignment mark is located according to the deformation data of the silicon wafer.
Theoretical position of field to be exposed (I)x，Iy) Generally, the exposure field is at the position on the silicon wafer surface when the silicon wafer is assumed to be in an ideal plane without deformation. Actual position of exposure field (R)x，Ry) The silicon wafer deformation data can be obtained by analyzing silicon wafers in the same batch or in the same process flow, and then the silicon wafer deformation data can be obtained by calculation through an interpolation algorithm, such as polynomial interpolation, Newton interpolation, spline interpolation and other algorithms. The measured values (M) of the N exposure fields selected in the first stepx，My) This can be obtained by measuring the corresponding alignment marks. The traditional alignment algorithm adopts alignment mark measured values and theoretical values for fitting, and the method adopts alignment mark measured values and actual positions for least square fitting. And traversing the field grids on the silicon wafer and selecting the combination with the minimum fitting error.
The third step: after the optimization of the position of the field grid where the alignment mark is positioned is completed, the optimization of the position (x) of the alignment mark in the field grid is continuedm，ym)。
The position design value (x) of the alignment mark in the exposure field as shown in FIG. 2m，ym) Combining the measurement results of the alignment marks to obtain the measurement value of the exposure field where the alignment mark is located, (M)x(xm)，My(ym)). Will (x)m，ym) As a variable, the sum of squared errors E ═ Σ (R) is calculated by an optimization algorithm, such as the least squares methodx-Mx)2+∑(Ry-My)2When E is minimum, the optimum mark position (x) is obtainedm，ym)。
The fourth step: and calculating the minimum number N of the alignment marks.
Based on the grid positions of the exposure field selected in the second step and the optimal mark positions calculated in the third step. And traversing the selected grids, sequentially reducing the number of the alignment marks, setting a smaller error threshold epsilon, determining the threshold according to the alignment error budget, and selecting the combination which meets epsilon and has the smallest number of the alignment marks, so as to obtain the optimal N.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A method for optimizing the layout of a silicon wafer alignment mark is characterized by comprising the following steps:
initializing the number of the alignment marks, and selecting a field grid where the alignment marks are located;
optimizing the field lattice where the alignment mark is located according to the deformation data of the silicon wafer; the method for optimizing the field lattice of the alignment mark comprises the steps of performing least square fitting according to an alignment mark measurement value and an alignment mark actual position value, traversing the field lattices on the silicon wafer, and selecting a combination with the minimum fitting error to be the optimized field lattice of the alignment mark; the alignment mark measurement is measured directly; the actual position value of the alignment mark is obtained by analyzing silicon wafers in the same batch or in the same process flow, acquiring deformation data of the silicon wafers and then performing an interpolation algorithm;
optimizing the position of the alignment mark in the field grid; the method specifically comprises the following steps:
actual position of exposure field (R)x,Ry) Design value (x) of the position of the alignment mark in the exposure field gridm,ym) Combining the measurement results of the alignment marks to obtain the measurement values of the exposure field grids in which the alignment marks are located, (M)x(xm),My(ym) Will (x)m,ym) As a variable, the sum of squared errors E ═ Σ (R) is calculated by an optimization algorithmx-Mx)2+∑(Ry-My)2When E is minimum, the optimal mark position (x) is obtainedm,ym)；
Calculating the minimum number of the alignment marks, namely finishing the layout optimization of the silicon wafer alignment marks; wherein calculating the minimum number of alignment marks comprises:
and traversing the selected grids according to the optimized grid where the alignment mark is positioned and the position of the optimized alignment mark in the grid, sequentially reducing the number of the alignment marks, and selecting the combination which meets an error threshold and has the smallest number of the alignment marks, so as to obtain the optimal number of the alignment marks.
2. The optimization method according to claim 1,
the interpolation algorithm comprises a polynomial interpolation algorithm, a Newton interpolation algorithm and a spline interpolation algorithm.
3. The optimization method according to claim 1,
the optimization algorithm comprises a least squares method.
4. The optimization method according to claim 1,
the error threshold is determined from an alignment error budget.
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