CN113777893B - Overlay error compensation method, overlay error compensation device, photoetching machine and storage medium - Google Patents

Overlay error compensation method, overlay error compensation device, photoetching machine and storage medium Download PDF

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CN113777893B
CN113777893B CN202110996234.6A CN202110996234A CN113777893B CN 113777893 B CN113777893 B CN 113777893B CN 202110996234 A CN202110996234 A CN 202110996234A CN 113777893 B CN113777893 B CN 113777893B
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interpolated
mark
ith
error
alignment
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CN113777893A (en
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曾健忠
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Shenzhen Sirius Semiconductor Co ltd
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Shenzhen Sirius Semiconductor Co ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7019—Calibration
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7046—Strategy, e.g. mark, sensor or wavelength selection
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The application is applicable to the technical field of semiconductors and provides a compensation method and device for overlay errors, a photoetching machine and a storage medium. The compensation method comprises the following steps: determining M mark groups to be interpolated from the N alignment marks, wherein the mark groups to be interpolated comprise at least two alignment marks; acquiring overlay errors of N alignment marks; for the ith mark group to be interpolated, the ith mark group to be interpolated is any mark group to be interpolated in M mark groups to be interpolated, and according to the overlay errors of all the alignment marks in the ith mark group to be interpolated, determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated; and performing error compensation on the wafer according to the overlay errors of the N alignment marks and the overlay errors of interpolation points corresponding to the M mark groups to be interpolated. Through can this application can be on not increasing the basis of alignment mark on the wafer, obtain more overlay error, based on these overlay errors, carry out error compensation to the wafer, can improve the overlay precision.

Description

Overlay error compensation method, overlay error compensation device, photoetching machine and storage medium
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a compensation method and device for overlay errors, a photoetching machine and a storage medium.
Background
There are two important flows of wafers in the photolithography process, alignment and exposure, respectively. In aligning a wafer, a more common method is to provide an alignment mark on the wafer, and the wafer is aligned by scanning and aligning the alignment mark.
The alignment marks on the wafer can be used for searching the overlay error so as to perform error compensation and improve the overlay accuracy. However, due to the limitation of the area of the wafer, the number of alignment marks arranged on the wafer is limited, and thus the number of overlay errors is limited, and the overlay accuracy is low.
Disclosure of Invention
The embodiment of the application provides a compensation method, a compensation device, a photoetching machine and a storage medium for alignment errors, which are used for solving the problems of limited number of alignment marks, limited alignment errors and lower alignment precision in the prior art.
In a first aspect, an embodiment of the present application provides a method for compensating an overlay error, where N alignment marks are disposed on a wafer, N is an integer greater than 1, and the method includes:
determining M mark groups to be interpolated from N alignment marks, wherein M is an integer greater than zero, and the mark groups to be interpolated comprise at least two alignment marks;
Acquiring overlay errors of N alignment marks;
for the ith symbol group to be interpolated, determining the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated according to the overlay error of all the alignment marks in the ith symbol group to be interpolated, wherein the ith symbol group to be interpolated is any one of the M symbol groups to be interpolated;
and performing error compensation on the wafer according to the overlay errors of the N alignment marks and the overlay errors of interpolation points corresponding to the M mark groups to be interpolated.
In a second aspect, an embodiment of the present application provides a compensation device for overlay error, where N alignment marks are disposed on a wafer, N is an integer greater than 1, and the compensation device includes:
the mark group determining module is used for determining M mark groups to be interpolated from N alignment marks, M is an integer greater than zero, and the mark groups to be interpolated comprise at least two alignment marks;
the error acquisition module is used for acquiring the overlay errors of the N alignment marks;
the error determining module is used for determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the overlay error of all the alignment marks in the ith mark group to be interpolated for the ith mark group to be interpolated, wherein the ith mark group to be interpolated is any one of the M mark groups to be interpolated;
And the error compensation module is used for carrying out error compensation on the wafer according to the overlay errors of the N alignment marks and the overlay errors of the interpolation points corresponding to the M mark groups to be interpolated.
In a third aspect, embodiments of the present application provide a lithographic apparatus comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the compensation method according to the first aspect described above when the computer program is executed.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the compensation method according to the first aspect described above.
In a fifth aspect, embodiments of the present application provide a computer program product for, when run on a lithographic machine, causing the lithographic machine to perform the steps of the compensation method as described in the first aspect above.
From the above, according to the method and the device, the M to-be-interpolated mark groups are determined from the N to-be-interpolated mark groups arranged on the wafer, each to-be-interpolated mark group comprises at least two alignment marks, the overlay errors of the N alignment marks are obtained, any to-be-interpolated mark group (such as the ith to-be-interpolated mark group) in the M to-be-interpolated mark groups can be subjected to error compensation, the overlay errors of the interpolation points corresponding to the ith to-be-interpolated mark group are determined according to the overlay errors of all the alignment marks in the ith to-be-interpolated mark group, so that the overlay errors of the interpolation points corresponding to the M to-be-interpolated mark groups can be obtained, more overlay errors (including the overlay errors of the alignment marks and the overlay errors of the interpolation points) can be obtained on the basis of not increasing the alignment marks on the wafer, and the overlay accuracy can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic implementation flow chart of an overlay error compensation method according to an embodiment of the present application;
FIG. 2a is an exemplary graph of overlay error of an alignment mark on a wafer;
FIG. 2b is a simplified illustration of overlay error of an alignment mark on a wafer;
fig. 3 is a schematic implementation flow chart of a method for compensating an overlay error according to a second embodiment of the present application;
FIG. 4a is an exemplary diagram of error compensation for a first order compensation algorithm;
FIG. 4b is an exemplary diagram of error compensation for a second order compensation algorithm;
fig. 5 is a schematic structural diagram of an overlay error compensation device according to a third embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a lithographic apparatus according to a fourth embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between the descriptions and not necessarily for indicating or implying relative importance.
Before describing the present application, for the convenience of the reader, the terms involved in the present application will be explained.
The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, and the original material of the wafer is silicon.
The photoetching machine, which can also be called as an exposure machine, an alignment machine and the like, is core equipment for manufacturing chips, is used for printing fine patterns on a mask plate on a wafer through light exposure, and is equipment for realizing pattern copying by exposing photoresist on the surface of a silicon wafer after aligning the patterns on the mask plate with the patterns etched on the silicon wafer in the previous procedure.
Photolithography machines are generally classified into optical and non-optical ones. The optical lithography machine uses ultraviolet light as an exposure light source. Non-optical lithography machines use other components of the electromagnetic spectrum (e.g., X-rays, electron beams, etc.) as exposure light sources.
Multiple layers of high-definition plate making generally need to be manufactured by multiple times of exposure, namely, one mask is needed for each exposure of a layer of pattern, and the exposed pattern (i.e., the pattern etched on the wafer in the previous process) needs to be precisely aligned before each mask is used for exposure, so that the correct relative position of each layer of pattern can be ensured.
On the wafer there is a pattern, called overlay mark, i.e. alignment mark, specially used for measuring overlay error.
It should be understood that the sequence number of each step in this embodiment does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.
In order to illustrate the technical solutions described in the present application, the following description is made by specific examples.
Referring to fig. 1, a schematic implementation flow chart of a method for compensating overlay error according to an embodiment of the present application is provided, and the method is applied to a lithography machine. As shown in fig. 1, the compensation method may include the steps of:
step 101, determining M mark groups to be interpolated from N alignment marks.
Wherein N is an integer greater than 1, M is an integer greater than zero, and the group of marks to be interpolated comprises at least two alignment marks.
The wafer is provided with N alignment marks, and M mark groups to be interpolated can be obtained by combining at least two alignment marks in the N alignment marks. Wherein, a specific value of M may be preset, for example, M is five.
When at least two of the N alignment marks are combined, the combination may be performed according to a selection operation or may be performed according to a preset rule, and is not limited herein. Combining according to the selection operation may refer to displaying N marks of the alignment marks (for example, the marks are numbers of the alignment marks, one alignment mark corresponds to one mark, and marks of different alignment marks are different), and when the selection operation of at least two marks in the N marks is detected, the alignment marks corresponding to the selected at least two marks are used as a mark group to be interpolated. The preset rule may be a preset combination rule, for example, for any alignment mark, the alignment mark and the alignment mark having a distance within a preset range from the alignment mark are combined into a to-be-interpolated mark group.
Optionally, all the alignment marks in the M groups of marks to be interpolated may be determined according to the marks of the alignment marks input by the user in the lithography machine, for example, M windows are displayed on the lithography machine, where each of the M windows corresponds to one of the groups of marks to be interpolated, and when the marks of the alignment marks filled in each of the windows by the user are detected, the alignment mark corresponding to the filled mark is determined to be the alignment mark in the group of marks to be interpolated corresponding to the window.
The number of alignment marks in the M mark groups to be interpolated may be the same or different, and is not limited herein. At least one different alignment mark exists between any two mark groups to be interpolated.
For example, eight alignment marks are provided on the wafer, which are a first alignment mark, a second alignment mark, a third alignment mark, a fourth alignment mark, a fifth alignment mark, a sixth alignment mark, a seventh alignment mark, and an eighth alignment mark, respectively; the five to-be-interpolated symbol groups are a first to-be-interpolated symbol group, a second to-be-interpolated symbol group, a third to-be-interpolated symbol group, a fourth to-be-interpolated symbol group and a fifth to-be-interpolated symbol group respectively, wherein the first to-be-interpolated symbol group can comprise a first alignment symbol and a second alignment symbol, the second to-be-interpolated symbol group can comprise a first alignment symbol, a second alignment symbol and a third alignment symbol, the third to-be-interpolated symbol group can comprise a fourth alignment symbol, a fifth alignment symbol and a sixth alignment symbol, the fourth to-be-interpolated symbol group can comprise a fourth alignment symbol, a fifth alignment symbol and a seventh alignment symbol, and the fifth to-be-interpolated symbol group can comprise a seventh alignment symbol and an eighth alignment symbol.
Step 102, obtaining overlay errors of the N alignment marks.
The overlay error of the N alignment marks refers to the overlay error of each of the N alignment marks.
In one embodiment, the overlay error of the alignment marks may be measured using reflection of light. Specifically: and (3) aligning the mask plate with the alignment marks on the wafer by using a high-resolution microscope, and then photographing to obtain corresponding images, and calculating the reflected light signals based on the images to obtain the overlay errors of the alignment marks.
In another embodiment, diffraction of light may be used to measure overlay errors of the alignment marks. Specifically: and a uniform light beam is injected into the alignment mark, the light beam is diffracted when passing through the alignment mark, the diffracted light beam is reflected after reaching the mask and the wafer, and the reflected diffraction light spot is analyzed to obtain the overlay error of the alignment mark.
The overlay error of the alignment mark may refer to an overlay error measured based on the alignment mark. For example, the overlay error of the first alignment mark may refer to an overlay error measured based on the first alignment mark.
And 103, determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the overlay errors of all the alignment marks in the ith mark group to be interpolated.
The i-th symbol group to be interpolated is any symbol group to be interpolated in M symbol groups to be interpolated, and i is an integer greater than zero and less than or equal to M.
In one embodiment, a correspondence between M to-be-interpolated symbol groups and L interpolation points may be pre-established, where L is an integer greater than or equal to M, that is, one to-be-interpolated symbol group may correspond to one interpolation point, or may correspond to at least two interpolation points, where different interpolation points have different positions on the wafer. For the ith symbol group to be interpolated, the interpolation point corresponding to the ith symbol group to be interpolated may be determined from the above correspondence.
Fig. 2a is an exemplary diagram of overlay errors of alignment marks on a wafer, and a line segment marked with an arrow in fig. 2a represents the overlay errors of the alignment marks, and the overlay errors of the alignment marks are a vector. As shown in FIG. 2b, which is a simplified example of overlay error of alignment marks on a wafer, the Egyptian in FIG. 2b shows four dies, V 1 The alignment error of the alignment mark on the die A is represented by A, the alignment error of the interpolation point on the die B is represented by A, the alignment error of the interpolation point on the die C is represented by B, and V 2 Indicating overlay errors of the alignment marks on the dice.
And 104, performing error compensation on the wafer according to the overlay errors of the N alignment marks and the overlay errors of the interpolation points corresponding to the M mark groups to be interpolated.
Error compensation of a wafer may refer to error compensation of dies on the wafer. By adding interpolation points on the basis of the existing alignment marks on the wafer, more overlay errors can be obtained, and error compensation is performed on the wafer based on the more overlay errors, so that the compensation precision can be improved, the overlay precision is improved, and the high-quality wafer is obtained.
In one embodiment, the overlay error of the alignment mark includes an X component and a Y component of the overlay error of the alignment mark, the X component of the overlay error refers to a component of the overlay error in a horizontal direction, and the Y component of the overlay error refers to a component of the overlay error in a vertical direction; according to the overlay errors of all the alignment marks in the ith mark group to be interpolated, determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated comprises:
determining the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated;
determining Y components of the overlay errors of interpolation points corresponding to the ith mark group to be interpolated according to Y components of the overlay errors of all the alignment marks in the ith mark group to be interpolated;
And determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component and the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated.
The component of the overlay error in the horizontal direction may refer to the overlay error of the corresponding alignment mark in the horizontal direction. For example, the component of the overlay error of the first alignment mark in the horizontal direction refers to the overlay error of the first alignment mark in the horizontal direction.
The component of the overlay error in the vertical direction may refer to the overlay error of the corresponding alignment mark in the horizontal direction. For example, the component of the overlay error of the first alignment mark in the vertical direction refers to the overlay error of the first alignment mark in the vertical direction.
For the ith mark group to be interpolated, estimating the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the known quantity such as the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated; the Y component of the overlay error of the interpolation point corresponding to the ith to-be-interpolated cluster can be estimated according to the known amount of the Y component of the overlay error of all the alignment marks in the ith to-be-interpolated cluster. For one interpolation point, the overlay error of the interpolation point can be obtained by adding the two obtained vectors after multiplying the X component of the overlay error of the interpolation point by the unit vector in the horizontal direction and the Y component of the overlay error of the interpolation point by the unit vector in the vertical direction.
In one embodiment, before determining the overlay error of the interpolation point corresponding to the ith to-be-interpolated symbol group according to the overlay errors of all the alignment symbols in the ith to-be-interpolated symbol group, the method further includes:
obtaining distances between all alignment marks in the ith mark group to be interpolated and corresponding interpolation points respectively;
according to the distance between the jth alignment mark in the ith to-be-interpolated mark group and the corresponding interpolation point, determining the weight corresponding to the jth alignment mark in the ith to-be-interpolated mark group, wherein the weight corresponding to the jth alignment mark in the ith to-be-interpolated mark group is inversely proportional to the distance between the jth alignment mark and the corresponding interpolation point, and the jth alignment mark in the ith to-be-interpolated mark group is any one of all the alignment marks in the ith to-be-interpolated mark group;
according to the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated, determining the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated comprises:
determining the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated and the corresponding weight;
According to the Y component of the overlay error of all the alignment marks in the ith mark group to be interpolated, determining the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated comprises:
and determining the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the Y component of the overlay error of all the alignment marks in the ith mark group to be interpolated and the corresponding weight.
The lithography machine stores the positions of interpolation points corresponding to the N alignment marks and the M mark groups to be interpolated on the wafer, and since all the alignment marks in the M mark groups to be interpolated are derived from the N alignment marks, the positions of all the alignment marks in the M mark groups to be interpolated on the wafer are also known. Taking the ith mark group to be interpolated as an example, according to the positions of all the alignment marks in the ith mark group to be interpolated and the corresponding interpolation points (i.e. the interpolation points corresponding to the ith mark group to be interpolated) on the wafer, the distances between all the alignment marks in the ith mark group to be interpolated and the corresponding interpolation points can be determined. The distance between the alignment mark and the interpolation point may be referred to as a euclidean distance.
Since the closer the alignment mark is to the interpolation point, the larger the effect of the overlay error on the overlay error of the interpolation point is, i.e., the degree of the effect of the overlay error of the alignment mark on the overlay error of the interpolation point is inversely proportional to the distance (i.e., the distance between the alignment mark and the interpolation point), the inverse of the distance between the alignment mark and the interpolation point can be used as the weight corresponding to the alignment mark. For example, taking the jth alignment mark in the ith to-be-interpolated mark group as an example, j is greater than zero and less than or equal to the total number of alignment marks in the ith to-be-interpolated mark group, the inverse of the distance between the jth alignment mark and the interpolation point corresponding to the ith to-be-interpolated mark group may be used as the weight of the jth alignment mark.
Taking the ith to-be-interpolated symbol group as an example, based on weights corresponding to all the alignment marks in the ith to-be-interpolated symbol group, the overlay errors of all the alignment marks in the ith to-be-interpolated symbol group can be distributed to the interpolation points corresponding to the ith to-be-interpolated symbol group, so that the overlay errors of the interpolation points corresponding to the ith to-be-interpolated symbol group can be obtained.
Specifically, according to a first formula, calculating an X component of an overlay error of an interpolation point corresponding to an ith symbol group to be interpolated; the Y component of the overlay error of the interpolation point corresponding to the ith to-be-interpolated cluster may be calculated according to the second formula.
Wherein the first formula isAx represents the X component, q of the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated j Representing the weight corresponding to the j-th alignment mark in the i-th mark group to be interpolated, V j X represents an X component of an overlay error of a j-th alignment mark in the i-th to-be-interpolated mark group, and H represents a total number of alignment marks in the i-th to-be-interpolated mark group;
the second formula isAy represents the Y component, V, of the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated j Y represents the Y component of the overlay error of the j-th alignment mark in the i-th to-be-interpolated mark group.
When the reciprocal of the distance between the jth alignment mark and the interpolation point corresponding to the ith symbol group to be interpolated is used as the weight of the jth alignment mark, the weight of the jth alignment markd j And representing the distance between the j-th alignment mark and the interpolation point corresponding to the i-th mark group to be interpolated.
According to the method and the device, the M to-be-interpolated mark groups are determined from N to-be-interpolated mark groups arranged on the wafer, each to-be-interpolated mark group comprises at least two to-be-interpolated mark groups, and the overlay errors of the N to-be-interpolated mark groups are obtained, so that for any to-be-interpolated mark group (such as the ith to-be-interpolated mark group) in the M to-be-interpolated mark groups, the overlay errors of the interpolation points corresponding to the ith to-be-interpolated mark group are determined according to the overlay errors of all the to-be-interpolated mark groups, so that the overlay errors of the interpolation points corresponding to the M to-be-interpolated mark groups can be obtained, more overlay errors can be obtained on the basis of not increasing the alignment mark on the wafer, and the wafer can be subjected to error compensation based on the overlay errors, so that the overlay accuracy can be improved.
Fig. 3 is a schematic implementation flow chart of a method for compensating overlay error according to a second embodiment of the present application, where the method is applied to a lithography machine. As shown in fig. 3, the compensation method may include the steps of:
Step 301, determining M groups of marks to be interpolated from the N alignment marks.
The step is the same as step 101, and specific reference may be made to the description related to step 101, which is not repeated here.
Step 302, the overlay errors of the N alignment marks are obtained.
The step is the same as step 102, and the detailed description of step 102 is omitted here.
Step 303, determining the overlay error of the interpolation point corresponding to the ith to-be-interpolated symbol group according to the overlay errors of all the alignment symbols in the ith to-be-interpolated symbol group.
The step is the same as step 103, and specific reference may be made to the related description of step 103, which is not repeated here.
And step 304, performing error compensation on the wafer through a high-order compensation algorithm according to the overlay errors of the N alignment marks and the overlay errors of the interpolation points corresponding to the M mark groups to be interpolated.
The higher-order compensation algorithm refers to a compensation algorithm with an order greater than 1. For example, the higher-order compensation algorithm in the present embodiment may be a second-order compensation algorithm. The embodiment adopts a high-order compensation algorithm, so that the wafer can be precisely compensated for errors during exposure, and the high-quality wafer can be obtained.
From the overlay errors of the N alignment marks and the overlay errors of the interpolation points corresponding to the M mark groups to be interpolated, the overlay errors of the target points corresponding to each die on the wafer can be determined, wherein the target points corresponding to each die can be the alignment marks and/or the interpolation points used when error compensation is performed on the die, and the number of the target points corresponding to each die is at least three; according to the overlay error of the target point corresponding to each crystal grain, the compensation coefficient corresponding to the crystal grain when a high-order compensation algorithm is adopted can be determined; according to the compensation coefficient corresponding to each die, error compensation can be performed on the die, and error compensation can be performed on the whole wafer by performing error compensation on all the dies on the wafer.
For each grain, an alignment mark and/or an interpolation point near the grain can be used as a target point corresponding to the grain, for example, an alignment mark and/or an interpolation point with a distance within a specified range from the grain is used as a target point corresponding to the grain, and when the number of the target points within the specified range is less than 3, at least three target points can be obtained by expanding the specified range, so that the grain can be guaranteed to be subjected to error compensation by adopting a high-order compensation algorithm. In the error compensation of the die b as shown in fig. 2b, the alignment mark on the die a, the interpolation point on the die c, and the alignment mark on the die d near the die b may be selected as the corresponding target points of the die b.
The performing error compensation on each die according to the compensation coefficient corresponding to the die may be to adjust an exposure parameter of the mask according to the compensation coefficient corresponding to the die, and perform exposure on the die according to the adjusted exposure parameter.
Fig. 4a is an exemplary diagram of error compensation of a first order compensation algorithm, and fig. 4b is an exemplary diagram of error compensation of a second order compensation algorithm. Fig. 4a and 4b illustrate a first symbol group to be interpolated, which includes a first alignment mark and a second alignment mark, the first symbol group to be interpolated corresponds to two interpolation points, V in fig. 4a and 4b 1 Y represents the Y component of the overlay error of the first alignment mark, V 2 Y represents the Y component of the overlay error of the second alignment mark, ay and By represent the Y component of the overlay error of the two interpolation points corresponding to the first mark group to be interpolated, as can be seen from fig. 4a, the Y component of the overlay error of the two interpolation points is not on the straight line determined By the first-order compensation algorithm, so that the error compensation effect is poor when the error compensation is performed on the crystal grains where the two interpolation points are located in fig. 4a, and the broken line in fig. 4a represents the straight line determined By the first-order compensation algorithm; as can be seen from fig. 4b, the Y components of the overlay errors of the first alignment mark, the second alignment mark and the two interpolation points are all on a straight line determined by the second order compensation algorithm, so that the error compensation effect is better when the error compensation is performed on the crystal grains where the first alignment mark, the second alignment mark and the two interpolation points are located in fig. 4b, and the broken line in fig. 4b represents the straight line determined by the second order compensation algorithm. Where c, e, and f in fig. 4a and 4b represent compensation coefficients, the abscissa d represents the distance between alignment marks and interpolation points on the wafer, and the ordinate Y represents the Y component of the overlay error.
Based on the first embodiment, the present embodiment can make the wafer obtain accurate error compensation during exposure by using a high-order compensation algorithm, so as to obtain a high-quality wafer.
Referring to fig. 5, a schematic structural diagram of an overlay error compensation device provided in the third embodiment of the present application is shown, for convenience of explanation, only the portions related to the embodiments of the present application are shown.
The compensation device comprises:
the token group determining module 51 is configured to determine M token groups to be interpolated from N alignment tokens, where M is an integer greater than zero, and the token groups to be interpolated include at least two alignment tokens;
the error obtaining module 52 is configured to obtain overlay errors of the N alignment marks;
the error determining module 53 is configured to determine, for the ith symbol group to be interpolated, an overlay error of an interpolation point corresponding to the ith symbol group to be interpolated according to overlay errors of all alignment marks in the ith symbol group to be interpolated, where the ith symbol group to be interpolated is any one of the M symbol groups to be interpolated;
the error compensation module 54 is configured to perform error compensation on the wafer according to the overlay errors of the N alignment marks and the overlay errors of the interpolation points corresponding to the M mark groups to be interpolated.
Optionally, the overlay error of the alignment mark includes an X component and a Y component of the overlay error of the alignment mark, the X component of the overlay error refers to a component of the overlay error in a horizontal direction, and the Y component of the overlay error refers to a component of the overlay error in a vertical direction; the error determination module includes:
The first determining unit is used for determining the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated;
the second determining unit is used for determining the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the Y component of the overlay error of all the alignment marks in the ith mark group to be interpolated;
and the third determining unit is used for determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component and the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated.
Optionally, the compensation device further includes:
the distance acquisition module is used for acquiring the distances between all the alignment marks in the ith mark group to be interpolated and the corresponding interpolation points respectively;
the weight determining module is used for determining the weight corresponding to the jth alignment mark in the ith to-be-interpolated mark group according to the distance between the jth alignment mark in the ith to-be-interpolated mark group and the corresponding interpolation point, wherein the weight corresponding to the jth alignment mark in the ith to-be-interpolated mark group is inversely proportional to the distance between the jth alignment mark and the corresponding interpolation point, and the jth alignment mark in the ith to-be-interpolated mark group is any one alignment mark in all the ith to-be-interpolated mark groups;
The first determining unit is specifically configured to determine an X component of an overlay error of an interpolation point corresponding to the ith to-be-interpolated symbol group according to the X component of the overlay error of all the alignment symbols in the ith to-be-interpolated symbol group and the corresponding weight;
the second determining unit is specifically configured to determine, according to the Y component of the overlay error of all the alignment marks in the ith to-be-interpolated mark group and the corresponding weight, the Y component of the overlay error of the interpolation point corresponding to the ith to-be-interpolated mark group.
Optionally, the first determining unit is specifically configured to:
according to the first formula, calculating an X component of an overlay error of an interpolation point corresponding to the ith mark group to be interpolated;
wherein the first formula isAx represents the X component, q of the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated j Representing the weight corresponding to the j-th alignment mark in the i-th mark group to be interpolated, V j x represents the overlay error of the jth alignment mark in the ith group of marks to be interpolatedX component, H represents the total number of alignment marks in the ith mark group to be interpolated;
the second determining unit is specifically configured to:
according to the second formula, calculating Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated;
Wherein the second formula isAy represents the Y component, V, of the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated j Y represents the Y component of the overlay error of the j-th alignment mark in the i-th to-be-interpolated mark group.
Optionally, the error compensation module 54 is specifically configured to:
and performing error compensation on the wafer through a high-order compensation algorithm according to the overlay errors of the N alignment marks and the overlay errors of interpolation points corresponding to the M mark groups to be interpolated.
Optionally, the error compensation module 54 is specifically configured to:
determining the overlay error of a target point corresponding to each grain on the wafer from the overlay errors of N alignment marks and the overlay errors of interpolation points corresponding to M mark groups to be interpolated, wherein the target point corresponding to each grain refers to the alignment mark and/or the interpolation point used for error compensation of the grain, and the number of the target points corresponding to each grain is at least three;
determining a compensation coefficient corresponding to each crystal grain when a high-order compensation algorithm is adopted according to the overlay error of the target point corresponding to each crystal grain;
and carrying out error compensation on each crystal grain according to the compensation coefficient corresponding to the crystal grain.
The alignment error compensation device provided in the embodiment of the present application may be applied to the first and second embodiments of the foregoing method, and details refer to the description of the first and second embodiments of the foregoing method, which are not repeated herein.
Fig. 6 is a schematic structural diagram of a lithographic apparatus according to a fourth embodiment of the present application. As shown in fig. 6, the lithography machine 6 of this embodiment includes: one or more processors 60 (only one shown), a memory 61, and a computer program 62 stored in the memory 61 and executable on the processor 60. The steps of the various compensation method embodiments described above are implemented by the processor 60 when executing the computer program 62.
The lithography machine 6 may include, but is not limited to, a processor 60, a memory 61. It will be appreciated by those skilled in the art that fig. 6 is merely an example of a lithographic apparatus 6 and is not limiting of the lithographic apparatus 6, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the lithographic apparatus may also include input and output devices, network access devices, buses, etc.
The processor 60 may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 61 may be an internal storage unit of the lithography machine 6, such as a hard disk or a memory of the lithography machine 6. The memory 61 may be an external storage device of the lithography machine 6, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the lithography machine 6. Further, the memory 61 may also include both an internal storage unit and an external storage device of the lithography machine 6. The memory 61 is used for storing the computer program as well as other programs and data required by the lithography machine. The memory 61 may also be used for temporarily storing data that has been output or is to be output. It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided herein, it should be understood that the disclosed apparatus/lithographic machine and method may be implemented in other ways. For example, the apparatus/lithographic machine embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each method embodiment described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
The present application may also be implemented as a computer program product for implementing all or part of the steps of the method embodiments described above, when the computer program product is run on a lithographic apparatus, so that the lithographic apparatus is executed to implement the steps of the method embodiments described above.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (8)

1. The method for compensating the overlay error is characterized in that N alignment marks are arranged on a wafer, N is an integer larger than 1, and the method comprises the following steps:
determining M mark groups to be interpolated from N alignment marks, wherein M is an integer greater than zero, and the mark groups to be interpolated comprise at least two alignment marks;
Acquiring overlay errors of N alignment marks;
for the ith symbol group to be interpolated, determining the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated according to the overlay error of all the alignment marks in the ith symbol group to be interpolated, wherein the ith symbol group to be interpolated is any one of the M symbol groups to be interpolated;
performing error compensation on the wafer according to the overlay errors of the N alignment marks and the overlay errors of interpolation points corresponding to the M mark groups to be interpolated;
the alignment error of the alignment mark comprises an X component and a Y component of the alignment error of the alignment mark, wherein the X component of the alignment error refers to a component of the alignment error in the horizontal direction, and the Y component of the alignment error refers to a component of the alignment error in the vertical direction; according to the overlay error of all the alignment marks in the ith mark group to be interpolated, determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated comprises:
determining the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated;
Determining Y components of the overlay errors of interpolation points corresponding to the ith mark group to be interpolated according to Y components of the overlay errors of all the alignment marks in the ith mark group to be interpolated;
and determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component and the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated.
2. The compensation method of claim 1, further comprising, before determining an overlay error of an interpolation point corresponding to the ith symbol group to be interpolated according to the overlay errors of all the alignment symbols in the ith symbol group to be interpolated:
obtaining distances between all the alignment marks in the ith mark group to be interpolated and corresponding interpolation points respectively;
according to the distance between the jth alignment mark in the ith symbol group to be interpolated and the corresponding interpolation point, determining the weight corresponding to the jth alignment mark in the ith symbol group to be interpolated, wherein the weight corresponding to the jth alignment mark in the ith symbol group to be interpolated is inversely proportional to the distance between the jth alignment mark and the corresponding interpolation point, and the jth alignment mark in the ith symbol group to be interpolated is any alignment mark in all the ith symbol groups to be interpolated;
The determining the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated comprises:
determining the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated and the corresponding weight;
the determining the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the Y component of the overlay error of all the alignment marks in the ith mark group to be interpolated comprises:
and determining the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the Y component of the overlay error of all the alignment marks in the ith mark group to be interpolated and the corresponding weight.
3. The compensation method of claim 2, wherein the determining the X component of the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated according to the X component of the overlay error of all the alignment symbols in the ith symbol group to be interpolated and the corresponding weights comprises:
according to a first formula, calculating an X component of an overlay error of an interpolation point corresponding to the ith mark group to be interpolated;
Wherein the first formula isAx represents the X component, q of the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated j Representing the weight corresponding to the j-th alignment mark in the i-th mark group to be interpolated, V j X represents the X component of the overlay error of the j-th alignment mark in the i-th mark group to be interpolated, and H represents the total number of the alignment marks in the i-th mark group to be interpolated;
the determining the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the Y component of the overlay error of all the alignment marks in the ith mark group to be interpolated and the corresponding weight comprises:
according to a second formula, calculating the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated;
wherein the second formula isAy represents the Y component, V of the overlay error of the interpolation point corresponding to the ith symbol group to be interpolated j Y represents the Y component of the overlay error of the j-th alignment mark in the i-th mark group to be interpolated.
4. The method according to any one of claims 1 to 3, wherein the performing error compensation on the wafer according to overlay errors of the N alignment marks and overlay errors of interpolation points corresponding to the M mark groups to be interpolated includes:
And performing error compensation on the wafer through a high-order compensation algorithm according to the overlay errors of the N alignment marks and the overlay errors of interpolation points corresponding to the M mark groups to be interpolated.
5. The method of claim 4, wherein performing error compensation on the wafer by a high-order compensation algorithm according to overlay errors of the N alignment marks and overlay errors of interpolation points corresponding to the M mark groups to be interpolated comprises:
determining the overlay error of a target point corresponding to each crystal grain on the wafer from the overlay errors of N alignment marks and the overlay errors of interpolation points corresponding to M mark groups to be interpolated, wherein the target point corresponding to each crystal grain refers to the alignment mark and/or the interpolation point used when error compensation is carried out on the crystal grain, and the number of the target points corresponding to each crystal grain is at least three;
determining a compensation coefficient corresponding to each crystal grain when the high-order compensation algorithm is adopted according to the overlay error of the target point corresponding to each crystal grain;
and carrying out error compensation on each crystal grain according to the compensation coefficient corresponding to the crystal grain.
6. The utility model provides a compensation arrangement of overlay error is provided with N alignment mark on the wafer, N is the integer that is greater than 1, its characterized in that, compensation arrangement includes:
The mark group determining module is used for determining M mark groups to be interpolated from N alignment marks, M is an integer greater than zero, and the mark groups to be interpolated comprise at least two alignment marks;
the error acquisition module is used for acquiring the overlay errors of the N alignment marks;
the error determining module is used for determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the overlay error of all the alignment marks in the ith mark group to be interpolated for the ith mark group to be interpolated, wherein the ith mark group to be interpolated is any one of the M mark groups to be interpolated;
the error compensation module is used for carrying out error compensation on the wafer according to the overlay errors of the N alignment marks and the overlay errors of interpolation points corresponding to the M mark groups to be interpolated;
the alignment error of the alignment mark comprises an X component and a Y component of the alignment error of the alignment mark, wherein the X component of the alignment error refers to a component of the alignment error in the horizontal direction, and the Y component of the alignment error refers to a component of the alignment error in the vertical direction; the error determination module includes:
the first determining unit is used for determining the X component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component of the overlay error of all the alignment marks in the ith mark group to be interpolated;
The second determining unit is used for determining the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the Y component of the overlay error of all the alignment marks in the ith mark group to be interpolated;
and the third determining unit is used for determining the overlay error of the interpolation point corresponding to the ith mark group to be interpolated according to the X component and the Y component of the overlay error of the interpolation point corresponding to the ith mark group to be interpolated.
7. A lithographic machine comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the compensation method according to any one of claims 1 to 5 when the computer program is executed.
8. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the compensation method according to any one of claims 1 to 5.
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