CN110875193A

CN110875193A - Wafer level packaging method and packaging structure

Info

Publication number: CN110875193A
Application number: CN201811028263.8A
Authority: CN
Inventors: 罗海龙; 克里夫.德劳利
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2018-09-04
Filing date: 2018-09-04
Publication date: 2020-03-10
Anticipated expiration: 2038-09-04
Also published as: CN110875193B

Abstract

A wafer level packaging method and a packaging structure are provided, the method comprises the following steps: providing a device wafer with a first chip, wherein the device wafer comprises a first front side with the first chip and a first back side opposite to the first front side; providing a bearing substrate, and temporarily bonding a plurality of second chips on the bearing substrate, wherein each second chip comprises a second front surface and a second back surface, the second front surface is provided with a first bonding pad, the second back surface is opposite to the second front surface, and the second front surface faces the bearing substrate; forming a first packaging layer covering the second chip on the bearing substrate; removing the bearing substrate; the first front surface and the second front surface are oppositely arranged, and the bonding of the device wafer and the second chip is realized by adopting a low-temperature fusion bonding process; forming a first opening in the first packaging layer to expose at least one second chip; and forming a back gold layer to cover the second chip, the bottom and the side wall of the first opening and the first packaging layer. The invention improves the packaging yield and the service performance.

Description

Wafer level packaging method and packaging structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a wafer level packaging method and a packaging structure.

Background

With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), three-dimensional Package (3D), System In Package (SiP), and the like.

At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packaging, an advanced packaging method mainly adopts Wafer Level Package System In Package (WLPSiP), and compared with the conventional System packaging, the Wafer Level System packaging completes a packaging integration process on a Wafer, so that the Wafer Level System packaging has the advantages of greatly reducing the area of a packaging structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment.

Disclosure of Invention

The embodiment of the invention provides a wafer level packaging method and a packaging structure, which can improve the service performance and the packaging yield of the wafer level packaging structure.

To solve the above problems, an embodiment of the present invention provides a wafer level packaging method, including: providing a device wafer, wherein a plurality of first chips are formed in the device wafer, and the device wafer comprises a first front side on which the first chips are formed and a first back side opposite to the first front side; providing a bearing substrate, and temporarily bonding a plurality of second chips on the bearing substrate, wherein the second chips comprise a second front surface and a second back surface, the second front surface is formed with first bonding pads, the second back surface is opposite to the second front surface, and the second front surface faces the bearing substrate; forming a first packaging layer covering the plurality of second chips on the bearing substrate; after the first packaging layer is formed, removing the bearing substrate; after the bearing substrate is removed, the first front surface and the second front surface are oppositely arranged, and the bonding of the device wafer and the second chip is realized by adopting a low-temperature fusion bonding process; after the low-temperature fusion bonding process, forming a first opening exposing at least one second chip in the first packaging layer, wherein the second back surface exposed by the first opening is suitable for loading signals; and forming a back gold layer to cover the second chip exposed from the first opening, the bottom and the side wall of the first opening and the first packaging layer.

Accordingly, an embodiment of the present invention further provides a wafer level package structure, including: the chip packaging structure comprises a device wafer, a first chip and a second chip, wherein a plurality of first chips are formed in the device wafer, and the device wafer comprises a first front side on which the first chips are formed and a first back side opposite to the first front side; the second chips are bonded on the device wafer and comprise second front surfaces and second back surfaces, the second front surfaces are formed with first bonding pads, the second back surfaces are opposite to the second front surfaces, and the second front surfaces and the first front surfaces are oppositely arranged and bonded through a low-temperature melting bonding process; the first packaging layer is positioned on part of the device wafer, a first opening for exposing at least one second chip is formed in the first packaging layer, and a second back surface exposed from the first opening is suitable for loading signals; and the back gold layer covers the second chip exposed from the first opening, the bottom and the side wall of the first opening and the first packaging layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the embodiment of the invention, the bonding of the device wafer and the second chip is realized by adopting a low-temperature fusion bonding process, and in the process of the low-temperature fusion bonding process, the first packaging layer is used for effectively supporting the second chip, so that the operability of the low-temperature fusion bonding process is improved; moreover, the device wafer and the second chip have higher bonding strength through the fusion bonding process; in addition, after the low-temperature fusion bonding process, a first opening is formed in the first packaging layer, a second back surface suitable for loading signals is exposed, a second chip exposed by the first opening, the bottom and the side wall of the first opening and a back gold layer of the first packaging layer are formed, and the back gold layer of the second back surface is used as a back electrode of the second chip, so that signals (such as grounding signals) can be loaded on the second back surface suitable for loading signals according to actual process requirements, and the usability of the wafer-level packaging structure is further improved.

In an alternative scheme, a second bonding pad is formed on the surface, facing the second chip, of the first chip, the first opening further exposes the second bonding pad, so that the back gold layer is further formed on the surface of the second bonding pad, and therefore the second back surface and the second bonding pad are electrically connected, and further a voltage signal can be loaded on the second back surface through the first chip.

Drawings

Fig. 1 to 16 are schematic structural diagrams corresponding to steps of a first embodiment of a wafer level packaging method according to the present invention;

fig. 17 to 19 are schematic structural diagrams corresponding to steps of the second embodiment of the wafer level packaging method of the present invention.

Detailed Description

At present, the service performance and the packaging yield of the wafer level packaging structure need to be improved. The reason for this analysis is:

the wafer level packaging structure mainly comprises a device wafer, a bare chip bonded on the device wafer and a packaging layer which is positioned on the device wafer and covers the bare chip; the packaging layer wraps the bare chip, so that it is difficult to load a signal (e.g., a ground signal or a voltage signal) to the back surface of the bare chip in the wafer level packaging structure.

Moreover, the device wafer and the bare chip are usually physically connected through an adhesive layer (such as an adhesive film or a dry film), but the adhesive layer has poor temperature resistance, and when the process temperature in the subsequent process is too high, the adhesive layer is easily failed, so that the adhesiveness of the adhesive layer is reduced, and even the device wafer and the bare chip are peeled off, thereby seriously affecting the packaging yield.

In order to solve the technical problem, in the embodiment of the invention, a low-temperature fusion bonding process is adopted to realize bonding of a device wafer and a second chip, and in the process of the low-temperature fusion bonding process, the first packaging layer is used for effectively supporting the second chip, so that the operability of the low-temperature fusion bonding process is improved; moreover, the device wafer and the second chip have higher bonding strength through the fusion bonding process; in addition, after the low-temperature fusion bonding process, a first opening is formed in the first packaging layer, a second back surface suitable for loading signals is exposed, a second chip exposed by the first opening, the bottom and the side wall of the first opening and a back gold layer of the first packaging layer are formed, and the back gold layer of the second back surface is used as a back electrode of the second chip, so that signals (such as grounding signals) can be loaded on the second back surface suitable for loading signals according to actual process requirements, and the usability of the wafer-level packaging structure is further improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 to 16 are schematic structural diagrams corresponding to steps of the first embodiment of the wafer level packaging method of the present invention.

Referring to fig. 1, a device Wafer (CMOS Wafer)100 is provided, the device Wafer 100 having a plurality of first chips 110 formed therein, the device Wafer 100 including a first front side 101 having the first chips 110 formed therein and a first back side 102 opposite the first front side 101.

In this embodiment, the wafer level packaging method is used to implement wafer level system packaging, and the device wafer 100 is used to bond with a chip to be integrated in a subsequent process.

The device wafer 100 is a wafer for completing device fabrication, and the device wafer 100 may be fabricated by using an integrated circuit fabrication technology, for example, NMOS devices, PMOS devices and other devices are formed on a semiconductor substrate through deposition, etching and other processes, and structures such as a dielectric layer, a metal interconnection structure, and a pad electrically connected to the metal interconnection structure are formed on the devices, so that at least one first chip 110 is integrated in the device wafer 100.

It should be noted that, when the first chip 110 is a plurality of chips, the plurality of first chips 110 may be chips of the same type or different types.

It should be noted that, for convenience of illustration, the device wafer 100 of the present embodiment is described by taking three first chips 110 as an example. The number of the first chips 110 is not limited to three.

In this embodiment, the substrate of the device wafer 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, the device wafer 100 includes a first front side 101 formed with the first chips 110 and a first back side 102 opposite to the first front side 101, where the first back side 102 refers to a substrate bottom surface of the device wafer 100.

In this embodiment, a second Pad (Pad)120 is formed on a surface of the first chip 110 facing the first front surface 101. The second bonding pads 120 may be Bond pads (Bond pads), and the second bonding pads 120 are used for electrically connecting the first chip 110 and other semiconductor devices.

Referring to fig. 2, a carrier substrate 10 is provided, a plurality of second chips 200 are temporarily bonded on the carrier substrate 10, the second chips 200 include a second front surface 201 formed with first pads 210 and a second back surface 202 opposite to the second front surface 201, and the second front surface 202 faces the carrier substrate 10.

The carrier substrate 10 is used for supporting the plurality of second chips 200, so that the subsequent process is facilitated, and the operability of the subsequent process is improved; and the subsequent separation of the second chip 200 and the carrier substrate 10 is also facilitated by means of Temporary Bonding (Temporary Bonding).

In this embodiment, the Carrier substrate 10 is a Carrier Wafer (Carrier Wafer). Specifically, the carrier substrate 10 may be a semiconductor substrate (e.g., a silicon substrate), an organic glass wafer, an inorganic glass wafer, a resin wafer, a semiconductor material wafer, an oxide crystal wafer, a ceramic wafer, a metal wafer, an organic plastic wafer, an inorganic oxide wafer, or a ceramic material wafer.

In this embodiment, the second front surface 201 of the second chip 200 is attached to the carrier substrate 10 by an adhesive layer 15.

The adhesive layer 15 is used to temporarily bond the second chip 200 and the carrier substrate 10, so as to facilitate the subsequent separation of the second chip 200 and the carrier substrate 10. Specifically, the adhesive layer 15 is one or both of a Film (DAF) and a Dry Film (Dry Film).

The dry film is a sticky photoresist film used for semiconductor chip packaging or printed circuit board manufacturing, and the dry film photoresist is manufactured by coating solvent-free photoresist on a polyester film base and then coating a polyethylene film; when the dry film photoresist is used, the polyethylene film is uncovered, the solvent-free photoresist is pressed on the base plate, and a pattern can be formed in the dry film photoresist through exposure and development treatment.

The adhesive film is an ultra-thin film adhesive used for connecting a semiconductor chip and a packaging substrate and connecting the chip and the chip in a semiconductor packaging process, has high reliability and convenient process performance, and is beneficial to realizing the lamination and thinning of the semiconductor packaging.

It should be noted that, in other embodiments, the second front surface of the second chip may also be temporarily bonded to the carrier substrate through electrostatic bonding. The electrostatic bonding technology is a method for realizing bonding without any adhesive, in the bonding process, a chip to be bonded and a bearing substrate are respectively connected with different electrodes, electric charges are formed on the surfaces of the chip and the bearing substrate under the action of voltage, and the electric charges on the surfaces of the chip and the bearing substrate are different, so that a larger electrostatic attraction is generated in the bonding process of the chip and the bearing substrate, and the physical connection of the chip and the bearing substrate is realized.

The second chips 200 are used as chips to be integrated in a wafer level system package, and the number of the second chips 200 is the same as that of the first chips 110 (shown in fig. 1).

The second chip 200 may be one or more of an active element, a passive element, a micro electro mechanical system, an optical element, and the like. Specifically, the second chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the second chip may also be other functional chips.

In this embodiment, the wafer level system package is used to combine a plurality of second chips 200 with different functions into one package structure, so that the second chips 200 are obtained by cutting a plurality of wafers with different function types. In other embodiments, the functional types of the plurality of second chips may also be the same according to actual process requirements.

The second chip 200 may be manufactured by using an integrated circuit manufacturing technology, and the second chip 200 generally includes devices such as NMOS devices or PMOS devices formed on a semiconductor substrate, and further includes structures such as a dielectric layer, a metal interconnection structure, and a bonding pad.

In this embodiment, the second chip 200 includes a second front surface 201 formed with a first pad 210 and a second back surface 202 opposite to the second front surface 201; wherein the second back side 202 refers to a semiconductor substrate bottom surface of the second chip 200.

Specifically, the first bonding pad 210 may be a wire bonding pad, and the first bonding pad 210 is used for electrically connecting the second chip 200 with other semiconductor devices.

It should be noted that the wafer level packaging method of the present embodiment is used to implement heterogeneous integration, and therefore the plurality of second chips 200 are chips made of silicon wafers. In other embodiments, the second chip may also be a chip formed by other materials.

It should be noted that, for convenience of illustration, in the present embodiment, the number of the second chips 200 is three for example. The number of the second chips 200 is not limited to three.

Referring to fig. 3, a first encapsulation layer 300 covering the plurality of second chips 200 is formed on the carrier substrate 10.

The first package layer 300 is used for protecting the second chip 200, and can play a role in sealing and moisture protection, and can also play a role in protecting the device wafer 100 after the second chip 200 and the device wafer 100 (shown in fig. 1) are bonded in the following process, so that the probability that the first chip 110 (shown in fig. 1) and the second chip 200 are damaged, polluted or oxidized is reduced, and further, the performance of the formed wafer-level package structure is optimized; moreover, the first encapsulation layer 300 covers the plurality of second chips 200, and can also support the second chips 200, thereby improving the operability of the subsequent fusion bonding process.

In this embodiment, the material of the first encapsulation layer 300 is Epoxy resin (Epoxy). Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, low cost and the like, and is widely used as a packaging material for electronic devices and integrated circuits. In other embodiments, the material of the encapsulation layer may also be a thermosetting material such as polyimide or silicone.

In this embodiment, the first encapsulation layer 300 is formed by using a liquid molding compound or a solid molding compound through an injection molding process. The filling performance of the injection molding process is good, so that the molding compound can be filled among the plurality of second chips 200 well, thereby improving the packaging effect of the first packaging layer 300 on the second chips 200. In other embodiments, other processes may be used to form the first encapsulation layer.

Referring to fig. 4, after the first encapsulation layer 300 is formed, the carrier substrate 10 is removed (as shown in fig. 3).

By removing the carrier substrate 10, the first encapsulation layer 300 is exposed from the second front surface 201, thereby providing a process foundation for a subsequent fusion bonding process.

Specifically, the second chip 200 and the carrier substrate 10 may be subjected to a De-bonding (De-bonding) process by a chemical method or a mechanical peeling method to remove the carrier substrate 10 and the adhesive layer 15 (as shown in fig. 3). In other embodiments, the carrier substrate may be separated from the second chip in other manners.

With continuing reference to fig. 1 and with combined reference to fig. 5 to 9, after removing the carrier substrate 10, the first front surface 101 and the second front surface 201 are disposed opposite to each other, and a low-temperature fusion bonding process is used to bond the device wafer 100 and the second chip 200.

The fusion bonding is a process for completing bonding by mainly utilizing interfacial chemical force, so that the reliability of the bonding process is improved, the bonding strength of the device wafer 100 and the second chip 200 is further improved, the subsequent process has small influence on the bonding strength, and the packaging yield is correspondingly improved.

Moreover, since the first encapsulation layer 300 is also exposed to the process environment of the fusion bonding process, the process temperature of the annealing treatment in the fusion bonding process is reasonably reduced by adopting the low-temperature fusion bonding process, so that the influence of the fusion bonding process on the first encapsulation layer 300 is reduced.

Correspondingly, for the low-temperature fusion bonding process, the packaging method further comprises the following steps:

with combined reference to fig. 1 and 5, a first oxide layer 150 is formed on the first front surface 101; a second oxide layer 250 is formed on the second front surface 201.

The first oxide layer 150 and the second oxide layer 250 serve as Bonding layers of a subsequent Fusion Bonding (Fusion Bonding) process for achieving physical connection between the device wafer 100 and the second chip 200. In the process of the fusion bonding process, unsaturated bonded Si atoms are formed on the surfaces of the first oxide layer 150 and the second oxide layer 250, and covalent bonding can be achieved, so that through the fusion bonding process, the contact surfaces of the first oxide layer 150 and the second oxide layer 250 are bonded in a covalent bonding manner, and the first oxide layer 150 and the second oxide layer 250 have high bonding strength, so that the reliability of the bonding process is improved, the bonding strength of the device wafer 100 and the second chip 200 is improved, the influence of subsequent processes on the bonding strength is small, and the packaging yield is correspondingly improved.

In this embodiment, the first oxide layer 150 is made of silicon oxide. By selecting the silicon oxide material, in the subsequent fusion bonding process, the device wafer 100 and the chip to be integrated can be bonded by a Si-O-Si covalent bond, and the bonding energy of the Si-O bond is larger, so that the bonding strength of the device wafer 100 and the chip to be integrated is further improved; in addition, the silicon oxide material has higher process compatibility, and the silicon oxide is a material which is commonly used in the process and has lower cost, so that the process difficulty and the process cost are favorably reduced by selecting the silicon oxide material, and the performance influence on the formed wafer-level packaging structure is favorably reduced. In other embodiments, the first oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide.

Specifically, the process of forming the first oxide layer 150 may be an Atomic Layer Deposition (ALD) process. The atomic layer deposition process refers to a deposition process in which a vapor phase precursor is alternately pulsed into a reaction chamber to chemisorb and cause a surface reaction on a substrate to be deposited. By adopting an atomic layer deposition process, the first oxide layer 150 is formed on the first front surface 101 in an atomic layer manner, so that uniformity of a deposition rate, thickness uniformity of the first oxide layer 150, and structural uniformity in the first oxide layer 150 are improved, and the first oxide layer 150 has good coverage capability; in addition, the process temperature of the ald process is usually lower, so that the Thermal Budget (Thermal Budget) is also reduced, and the probability of Wafer deformation (Wafer deformation) and device performance deviation is reduced.

In other embodiments, the process of forming the first oxide layer may also be a Low Pressure Chemical Vapor Deposition (LPCVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, a Physical Vapor Deposition (PVD) process, or a Laser pulse Deposition (PLD) process according to the material of the first oxide layer.

In this embodiment, the material of the second oxide layer 250 is the same as the material of the first oxide layer 150 (shown in fig. 1), so as to be beneficial to further improving the bonding strength between the second oxide layer 250 and the first oxide layer 150. Specifically, the second oxide layer 250 is formed by an atomic layer deposition process, and the material of the second oxide layer 250 is silicon oxide.

In other embodiments, the second oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide, and the process for forming the second oxide layer may also be a low pressure chemical vapor deposition process, a metal organic chemical vapor deposition process, a physical vapor deposition process, or a laser pulse deposition process.

For a detailed description of the second oxide layer 250, reference may be made to the foregoing description of the first oxide layer 150, and this embodiment is not repeated herein.

In this embodiment, the second oxide layer 250 further covers the first encapsulation layer 300. By covering the first packaging layer 300 with the second oxide layer 250, the difficulty of the process for forming the second oxide layer 250 can be reduced, which is beneficial to reducing the process cost; moreover, the first package layer 300 may contact with the second oxide layer 250 to achieve sealing, so that after a subsequent fusion bonding process, the probability of generating a gap between the device wafer 100 and the second chip 200 may be effectively reduced, and air and moisture may be better isolated, thereby improving a package effect, and further facilitating optimization of performance of a formed wafer-level package structure.

In other embodiments, the second oxide layer is formed on the second front surface before a plurality of second chips are temporarily bonded on the carrier substrate; accordingly, in the step of temporarily bonding a plurality of second chips on the carrier substrate 10, the second oxide layer is temporarily bonded on the carrier substrate.

Therefore, referring to fig. 6 to 9 in combination, the bonding between the device wafer 100 and the second chip 200 is achieved through the first oxide layer 150 and the second oxide layer 250 by using a low-temperature fusion bonding process.

Specifically, referring to fig. 6 and 7 in combination, the steps of the low temperature fusion bonding process include: and performing plasma activation treatment 130 on the surface of the first oxide layer 150 (shown in fig. 6) and the surface of the second oxide layer 250 (shown in fig. 7).

On one hand, the contaminants, impurities, and the like on the surfaces of the first oxide layer 150 and the second oxide layer 250 are made into a gaseous state by the plasma activation treatment 130, and are exhausted by a vacuum pump of a plasma system, thereby performing a function of removing the contaminants and impurities, for example, metal contaminants and organic contaminants can be removed well. On the other hand, the plasma of the plasma activation treatment 130 collides with the surfaces of the first oxide layer 150 and the second oxide layer 250, and energizes unstable non-bridging oxygen atoms to move the oxygen atoms away from the original bonded atoms, thereby providing a good basis for the subsequent formation of covalent bonds at the contact surfaces of the first oxide layer 150 and the second oxide layer 250.

In this embodiment, the material of the first oxide layer 150 and the second oxide layer 250 is silicon oxide, so that unsaturated bonded Si atoms are formed on the surfaces of the first oxide layer 150 and the second oxide layer 250 after the plasma activation treatment 130.

The reactive gas used in the plasma activation treatment 130 may include Ar, N₂、O₂And SF₆One or more of (a). In this embodiment, the reaction gas used for the plasma activation treatment 130 is O₂That is, the plasma activation treatment 130 is an oxygen plasma activation treatment.

The rf power of the plasma activation treatment 130 is not too low or too high. In the plasma activation process 130, electrons are accelerated by the radio frequency electric field generated by the radio frequency power source, and each electron collides with a reaction gas molecule to transfer kinetic energy, so that each reaction gas molecule is ionized to generate plasma.

If the rf power is too low, the reaction gas is difficult to be converted into plasma, which is likely to cause insufficient plasma and poor plasma stability, thereby reducing the effect of the plasma activation treatment 130, and further reducing the bonding strength between the first oxide layer 150 and the second oxide layer 250; if the rf power is too high, the kinetic energy obtained after the reaction gas is turned into plasma is too high, the bombardment effect on the first oxide layer 150 and the second oxide layer 250 is correspondingly too strong, so that the surfaces of the first oxide layer 150 and the second oxide layer 250 are easily damaged, Micro-defects (Micro-defects) are formed on the surfaces of the first oxide layer 150 and the second oxide layer 250, an annealing cavity is easily generated after subsequent annealing treatment, the bonding strength between the subsequent first oxide layer 150 and the subsequent second oxide layer 250 is easily reduced, and the rf power also consumes too much energy, thereby increasing the process cost. For this reason, in this embodiment, the rf power of the plasma activation process 130 is 20W to 200W.

The process pressure of the plasma activation treatment 130 should not be too low or too high. The process pressure affects the radio frequency power, the greater the process pressure, the shorter the mean free path of the plasma, and the greater the probability of collision between the plasmas, thereby causing the effect of the plasma activation processing 130 to be poor, and correspondingly, the higher the radio frequency power required for ensuring the effect of the plasma activation processing 130; in addition, when the process pressure is too small, the stability of the plasma is easily lowered, and accordingly, the higher the rf power required to suppress the plasma from being unstable. To this end, in this embodiment, the process pressure is adjusted to a matching value range according to the rf power of the plasma activation process 130. Specifically, the process pressure of the plasma activation treatment 130 is 0.1mBar to 10 mBar.

The processing time of the plasma activation processing 130 is not preferably too short, nor too long. If the processing time is too short, at radio frequency powerAnd the flow rate of the reaction gas is constant, the effect of the plasma activation treatment 130 is correspondingly deteriorated, thereby causing the bonding strength between the first oxide layer 150 and the second oxide layer 250 to be reduced; if the treatment time is too long, the surface of the first oxide layer 150 and the second oxide layer 250 is easily damaged, so that micro defects are formed on the surface of the first oxide layer 150 and the second oxide layer 250, and the treatment time is too long, so that an excessive amount of hydroxyl groups is generated, and an excessive amount of by-products (H) is easily generated after the subsequent annealing treatment₂O and H₂Etc.), thereby causing the generation of annealing voids, which in turn tends to decrease the bonding strength between the first oxide layer 150 and the second oxide layer 250, and further, the process cost increases due to the long process time. For this reason, in the present embodiment, the treatment time of the plasma activation treatment 130 is 0.1 minute to 10 minutes.

In this embodiment, the rf power, the process pressure, and the processing time of the plasma activation processing 130 are set within a reasonable range and cooperate with each other, so that the activation effect on the first oxide layer 150 and the second oxide layer 250 is improved while the processing efficiency and stability are improved and the process cost is reduced.

In this embodiment, the step of the fusion bonding process further includes: after the plasma activation treatment 130, performing deionized water cleaning treatment on the surfaces of the first oxide layer 150 and the second oxide layer 250; after the deionized water pre-cleaning treatment, the surfaces of the first oxide layer 150 and the second oxide layer 250 are dried.

Through the deionized water cleaning treatment and the drying treatment, the surface quality of the first oxide layer 150 and the second oxide layer 250 is improved, and thus the bonding strength of the first oxide layer 150 and the second oxide layer 250 is improved.

Specifically, the surfaces of the first oxide layer 150 and the second oxide layer 250 are rinsed with deionized water, thereby completing the deionized water cleaning process; after the deionized water cleaning treatment, N is adopted₂Blow-drying the first and second oxide layers 150 and 250, thereby completingAnd (5) drying treatment.

Referring to fig. 8 in combination, in this embodiment, the step of the fusion bonding process further includes: after the drying process, the second oxide layer 250 and the first oxide layer 150 are oppositely disposed and attached, and a bonding pressure is applied to the device wafer 100 and the second chip 200 to perform a pre-bonding process 140.

After the plasma activation treatment 130, unsaturated bonded Si atoms are formed on the surfaces of the first oxide layer 150 and the second oxide layer 250, and thus the first oxide layer 150 and the second oxide layer 250 are bonded by interfacial chemical bonding through the pre-bonding treatment 140.

Specifically, bonding pressure is applied to the first back surface 102 of the device wafer 100 and the surface of the first encapsulation layer 300 facing away from the second front surface 202 to perform the pre-bonding process 140.

In the process of the pre-bonding treatment 140, the first encapsulation layer 300 is used to effectively support the second chip 200, so as to improve the operability of the pre-bonding treatment 140, and by applying bonding pressure to the first encapsulation layer 300, it is beneficial to improve the stress uniformity of the plurality of second chips 200, and in addition, compared with a scheme of directly applying bonding pressure to the second chips 200, it is beneficial to reduce the damage caused by the pre-bonding treatment 140 to the second chips 200.

It should be noted that, although increasing the bonding pressure of the pre-bonding process 140 is beneficial to improving the chemical bond effect and strength at the interface between the first oxide layer 150 and the second oxide layer 250, if the bonding pressure is too high, the device wafer 100, the first oxide layer 150, the second oxide layer 250, the second chip 200, and the first package layer 300 may be adversely affected, for example, may be deformed. For this reason, in the present embodiment, in order to reduce the process risk while the first oxide layer 150 and the second oxide layer 250 effectively achieve interfacial chemical bond connection, the bonding pressure of the pre-bonding treatment 140 is 1 newton to 20 newton.

It should be noted that the processing time of the pre-bonding process 140 is not short, nor long. The increase of the processing time of the pre-bonding treatment 140 is also beneficial to improving the chemical bond connection effect and strength of the contact surface between the first oxide layer 150 and the second oxide layer 250, so that under the condition of a certain bonding pressure, if the processing time is too short, the problem of poor chemical bond connection effect of the interface between the first oxide layer 150 and the second oxide layer 250 is easily caused; the excessive processing time will cause waste of process time and decrease of efficiency. For this reason, in the present embodiment, in order to improve the process efficiency while the first oxide layer 150 and the second oxide layer 250 effectively achieve the interfacial chemical bond connection, the processing time of the pre-bonding treatment 140 is 1 second to 60 seconds.

Referring to fig. 9 in combination, in this embodiment, the step of the fusion bonding process further includes: after the pre-bonding process 140 (shown in fig. 8), the device wafer 100 and the second chip 200 are annealed.

By the annealing treatment, a dehydration condensation reaction occurs at the contact surface between the first oxide layer 150 and the second oxide layer 250, so that the first oxide layer 150 and the second oxide layer 250 form a covalent bond of Si-O-Si; since the silicon-oxygen bond has a large bond energy, the bonding strength between the first oxide layer 150 and the second oxide layer 250 is improved.

Wherein, the process temperature of the annealing treatment is not suitable to be too low or too high. If the process temperature is too low, the effect of dehydration condensation reaction is easily reduced, which is not favorable for improving the bonding strength of the first oxide layer 150 and the second oxide layer 250; if the process temperature is too high, the performance of the devices formed in the device wafer 100 and the second chip 200 is easily adversely affected, and the first encapsulation layer 300 is also easily adversely affected due to its generally poor high temperature resistance. For this reason, in this embodiment, the process temperature of the annealing treatment is 200 ℃ to 500 ℃.

In this embodiment, the annealing process has a lower process temperature, so that the influence of the annealing process on the device performance formed in the device wafer 100 and the second chip 200 and the first package layer 300 is also reduced.

The process time of the annealing treatment is not too short or too high. If the process time is too short, it is difficult to sufficiently complete the dehydration condensation reaction, thereby being disadvantageous to improve the bonding strength of the first and second oxide layers 150 and 250; if the process time is too long, the process time is wasted, and the efficiency is reduced, and the risk of the process increases when the device wafer 100 and the second chip 200 are placed in the annealing environment for a long time. For this reason, in this embodiment, the process time of the annealing treatment is 20 minutes to 200 minutes.

In this embodiment, the process temperature and the process time of the annealing treatment are set within a reasonable range and are matched with each other, so that the bonding strength is improved and the probability of side effects is reduced.

Referring to fig. 10, after the fusion bonding process, it further includes: the first back surface 102 is thinned.

The thickness of the device wafer 100 is reduced by thinning the first back surface 102, so that the heat dissipation effect of the device wafer 100 is improved, the subsequent packaging process is facilitated, the overall thickness of a wafer-level packaging structure formed after packaging is reduced, and the performance of the wafer-level packaging structure is improved.

In this embodiment, the thinning process may be one or more of a back grinding process, a Chemical Mechanical Polishing (CMP) process, and a wet etching process.

In order to effectively control the stop position of the thinning process, in the manufacturing process of the device wafer 100, a deep trench isolation structure for defining the stop position is generally formed in the substrate of the device wafer 100, so that the thinning process is stopped at the bottom of the deep trench isolation structure.

In another embodiment, a stop region may also be formed in the substrate of the device wafer during the fabrication process of the device wafer using neutral dopant ions (e.g., one or both of oxygen ions and nitrogen ions), such that the thinning process stops at the bottom of the stop region.

In other embodiments, when the substrate of the device wafer is a silicon-on-insulator substrate or a germanium-on-insulator substrate, the bottom substrate layer of the semiconductor substrate may also be thinned, so that the device wafer can better stop at the bottom of the insulator layer.

It should be noted that after the thinning process, the substrate thickness of the device wafer 100 should not be too small, nor too large. If the thickness is too small, the mechanical properties of the device wafer 100 are relatively poor, and devices and the like formed in the device wafer 100 are easily adversely affected; if the thickness is too large, the performance of the wafer level packaging structure is not improved favorably. For this reason, in the present embodiment, the substrate thickness of the device wafer 100 after the thinning process is 5 μm to 10 μm.

It should be further noted that, by performing the thinning process after the low-temperature fusion bonding process, the first package layer 300 can provide support during the thinning process, so as to improve the operability of the thinning process and reduce the probability of the first chip 110 falling off.

Referring to fig. 11, after the low-temperature fusion bonding process, the first packaging layer 300 is etched, a first opening 301 exposing at least one second chip 200 is formed in the first packaging layer 300, and a second back surface 202 exposed by the first opening 301 is suitable for loading signals.

By exposing the second back surface 202 to be loaded with signals, a process foundation is provided for forming a back gold layer on the second back surface 202. The back gold layer serves as a back electrode of the second chip 200 and is suitable for loading signals.

In the process of etching the first package layer 300, the device wafer 100 is used to support the second chip 200, so as to improve the operability of the etching process, and in addition, the second back surface 202 of the signal to be loaded can be selectively exposed according to the actual process requirements by forming the first opening 301 after the first package layer 300 is formed, which is beneficial to improving the process simplicity.

In this embodiment, the opening 301 exposes only one second chip 200. In other embodiments, the number of the second chips exposed by the opening is not limited to one, and may be determined according to actual process requirements.

In this embodiment, according to actual process requirements, the loading signal is a ground signal, that is, a back gold layer formed on the second back surface 202 is used to connect to a ground terminal.

It should be noted that, in order to reduce the difficulty of the process for forming the first opening 301 and reduce the influence on the device wafer 100, in the process of etching the first package layer 300, the surface of the second oxide layer 250 is used as an etching stop position, that is, the bottom of the first opening 301 is exposed out of the surface of the second oxide layer 250, so as to prevent the first opening 301 from exposing the second pad 120 of the first chip 110.

Specifically, the first encapsulation layer 300 is etched through a laser etching process.

The laser etching process is to irradiate high-energy laser beam onto the surface of the workpiece to be etched to melt and gasify the workpiece to form a groove with certain depth, so as to realize the purpose of etching. The laser etching process can realize one-time forming technology of different patterns at different angles, does not need to adopt a mask, and has the characteristics of high etching yield, high stability, good flexibility, no material consumption, simple and convenient operation, non-contact, no pollution, high precision, low process cost and the like. By adopting the laser etching mode, the size of the first opening 301 can be accurately controlled, the appearance quality of the first opening 301 can be improved, and therefore the probability that the adjacent second chip 200 or the first chip 110 is exposed is reduced.

In other embodiments, the process for etching the first encapsulation layer may also be a plasma etching process, a reactive ion etching process, or a wet etching process.

Referring to fig. 12 to 14, fig. 14 is an enlarged view of the back gold layer in the dashed line block a in fig. 13, and a back gold layer 450 (shown) is formed to cover the second chip 200 exposed from the first opening 301, the bottom and the sidewall of the first opening 301, and the first encapsulation layer 300.

The gold-backed layer 450 of the second back surface 202 is used as an electrode for loading a ground signal to the second chip 200.

In order to improve the performance of the back gold layer 450 and reduce the adverse effect on the second chip 200, the back gold layer 450 has low contact resistance and thermal resistance, and has small thermal stress and high reliability; in addition, in order to ensure good electrical performance, the back gold layer 450 has good electrical conductivity and can form ohmic contact with the second back surface 202.

Therefore, in the embodiment, the back gold layer 450 is a metal stacked structure, so that the properties of different metals can be utilized to make the subsequently formed electrode meet the process requirements.

Specifically, as shown in fig. 14, the back gold layer 450 includes a bottom metal layer 410, a transition metal layer 420 on the bottom metal layer, and a top metal layer 430 on the transition metal layer.

The material of the bottom metal layer 410 is a low barrier material, the contact resistance between the bottom metal layer 410 and the second back surface 202 is small, and the material of the bottom metal layer 410 has good wettability with the material of the second back surface 202, so that the bottom metal layer can be used as an ohmic contact layer.

For this reason, in this embodiment, the material of the bottom metal layer 410 is Ti. The Ti and the second back surface 202 material have good wettability, ohmic contact is easy to form, and the process difficulty for forming high-purity Ti is low, so that the process difficulty for forming the back gold layer 450 is reduced by selecting Ti as the bottom metal layer material; in addition, the chemical properties and mechanical properties of Ti are relatively stable and have a better thermal match with the material of the second backside 202, thus significantly improving the performance and reliability of the wafer level package structure.

In other embodiments, the bottom metal layer may also be Cr, Al, or V.

The bottom metalThe larger the thickness of the layer 410 is, the larger the resistance of the bottom metal layer 410 is, so the thickness of the bottom metal layer 410 should not be too large, otherwise the performance and reliability of the wafer level package structure are easily reduced, and the waste of process resources is caused. However, the thickness of the bottom metal layer 410 is not necessarily too small, and if the thickness of the bottom metal layer 410 is too small, the quality and performance of the back metal layer 450 are easily reduced, and accordingly, the performance and reliability of the wafer level package structure may also be reduced. For this purpose, in this embodiment, the thickness of the bottom metal layer 410 is

To

The top metal layer 430 has the characteristics of low resistivity, strong electromigration resistance, stable performance, difficulty in oxidation and the like, so that the top metal layer 430 can play a role of a conducting layer, can protect the transition metal layer 420, and reduces the probability of oxidation of the transition metal layer 420.

For this reason, in the present embodiment, the material of the top metal layer 430 is Ag. Since Ag is a material that is commonly used in the process and has a low cost, it is also beneficial to reduce the process difficulty and the process cost by selecting Ag as the material of the top metal layer 430.

In other embodiments, the material of the top metal layer 430 may also be Au.

The top metal layer 430 has a larger thickness, so that the protection effect on the transition metal layer 420 can be effectively improved, and when a ground signal is loaded on the back gold layer 450 of the second back surface 202, the reliability of the back gold layer 450 can be improved, so that the performance stability of the wafer-level packaging structure is improved; however, the thickness of the top metal layer 430 is not suitable for being too large, and if the thickness of the top metal layer 430 is too large, the resistance of the top metal layer 430 is too large, which may easily reduce the performance and reliability of the wafer level package structure and cause waste of process resources. To this end, in this embodiment, the top metalLayer 430 has a thickness of

To

The transition metal layer 420 is used for blocking the material of the top metal layer 430 from diffusing into the bottom metal layer 410, and the expansion coefficient of the transition metal layer 420 is between that of the top metal layer 430 and that of the bottom metal layer 410, so that the transition metal layer has moderate electrical and thermal conductivity, and thus the thermal matching effect can be better achieved; in addition, the transition metal layer 420 has good adhesion with the bottom metal layer 410 and the top metal layer 430, thereby being beneficial to improving the formation quality of the back gold layer 450 and reducing the probability of falling off among the metal layers. For this reason, in this embodiment, the material of the transition metal layer 420 is Ni.

Accordingly, in order to enable the transition metal layer 420 to perform good thermal matching and blocking functions, the thickness of the transition metal layer 420 is greater than that of the bottom metal layer 410, and the thickness of the transition metal layer 420 is less than that of the top metal layer 430. For this reason, in the present embodiment, the thickness of the transition metal layer 420 is set according to the thicknesses of the bottom metal layer 410 and the top metal layer 430

To

The process of forming any one of the bottom metal layer 410, the transition metal layer 420, and the top metal layer 430 is an electroplating process, a physical vapor deposition process, or an electron beam evaporation process; in order to improve the performance of the back gold layer 450, the processes for forming the bottom metal layer 410, the transition metal layer 420 and the top metal layer 430 are the same, so that good quality and appearance are ensured, and the thickness of each metal layer is well controlled.

In this embodiment, the bottom metal layer 410, the transition metal layer 420, and the top metal layer 430 are formed by an electroplating process, which is beneficial to improving the adhesion and mechanical strength of each metal layer. Accordingly, after the back gold layer 450 is formed, the back gold layer 450 conformally covers the second chip 200, the bottom and sidewalls of the first opening 301, and the top of the first encapsulation layer 300. In other embodiments, the back gold layer may be further filled in the first opening.

Specifically, the step of forming the back gold layer 450 includes: as shown in fig. 12, forming a metal layer structure 400 covering the second chip 200 exposed by the first opening 301, the bottom and the sidewall of the first opening 301, and the top of the first packaging layer 300; the metal layer structure 400 is subjected to an alloying treatment 440, and the metal layer structure 400 after the alloying treatment 440 is used as the back gold layer 450.

Accordingly, in this embodiment, the metal layer structure 400 also includes the bottom metal layer 410, the transition metal layer 420 located on the bottom metal layer 410, and the top metal layer 430 located on the transition metal layer 420.

Through the alloying treatment 410, the self resistance of the second chip 200 and the contact resistance of the second back surface 202 and the back gold layer 450 can be reduced, and accordingly, the grounding resistance can also be reduced, so that the loss of electric energy is reduced, and the performance and reliability of the formed wafer-level packaging structure are improved.

In this embodiment, the alloy treatment 440 is an annealing process. Through the annealing process, the bottom metal layer 410 and the material of the second back surface 202 are diffused and reacted with each other at the contact surface, so that alloying is realized at the contact surface.

Specifically, the material of the bottom metal layer 410 is Ti, the substrate of the second chip 200 is a silicon substrate, and accordingly, after the alloying treatment 440, a TiSi alloy is formed at the contact surface to form an ohmic contact.

Note that, the contact surface between the bottom metal layer 410 in the back gold layer 450 and the second back surface 202 is formed with TiSi alloy, so for convenience of illustration, the back gold layer 450 of the second back surface 202 and the back gold layer 450 of other areas are represented by different coatings.

Wherein, the process temperature of the alloy treatment 440 is not too low and not too high. If the process temperature is too low, the alloying rate at the contact surface of the bottom metal layer 410 and the second back surface 202 is slow, which is not favorable for reducing the contact resistance, thereby easily causing the performance degradation of the wafer level package structure; if the process temperature is too high, the performance of the devices in the second chip 200 and the device wafer 100 is easily adversely affected, and the performance of the wafer level package structure is also easily degraded. For this reason, in this embodiment, the process temperature of the alloy treatment 440 is 100 ℃ to 250 ℃.

The process time for the alloy treatment 440 should not be too short, nor too long. If the process time is too short, it is difficult to provide sufficient time to alloy the contact surface of the bottom metal layer 410 and the second back surface 202, which is not favorable for reducing the contact resistance, and thus the performance of the wafer level package structure is easily reduced; if the process time is too long, the thermal budget is increased, the efficiency is decreased, and the performance of the devices in the second chip 200 and the device wafer 100 is easily adversely affected. For this reason, in this embodiment, the process time of the alloy treatment 440 is 30 to 180 minutes.

In this embodiment, by reasonably setting the process parameters of the alloy treatment 440 and matching the process temperature and the process time with each other, the efficiency of the alloy treatment is improved and the probability of generating negative effects is reduced under the condition of effectively realizing alloying.

In this embodiment, the metal layer structure 400 is formed first, and then the alloy treatment 440 is performed. In other embodiments, after forming the bottom metal layer and completing the alloying process, the method further includes: forming a transition metal layer on the bottom metal layer; and forming a top metal layer on the transition metal layer, wherein the top metal layer, the transition metal layer and the bottom metal layer treated by the alloy are used as the back gold layer.

By performing the alloying treatment before the transition metal layer and the top metal layer are formed, the difficulty of the alloying treatment is reduced, and the alloying treatment is more efficient and remarkable.

It should be further noted that the second chip 200 and the device wafer 100 are bonded by low-temperature fusion bonding, and the bonding strength of the second chip 200 and the device wafer 100 is high, so that in the process of etching the first package layer 300 and forming the back gold layer 450, the probability of the second chip 200 and the device wafer 100 falling off is low, and adverse effects on the package yield caused by the process of etching the first package layer 300 and forming the back gold layer 450 can be effectively avoided.

Referring to fig. 15, after the alloy processing 440 (shown in fig. 14), the method further includes: a second encapsulation layer 310 covering the back gold layer 450 is formed within the first opening 301 (as shown in fig. 14), and the second encapsulation layer 310 also covers the back gold layer 450 on top of the first encapsulation layer 300.

The second package layer 310 is used to protect the back gold layer 450, so as to prevent the external environment from affecting the metal layer structure 400 and the back gold layer 450, and further avoid affecting the performance of the wafer level package structure.

For a detailed description of the second package layer 310, please refer to the corresponding description of the first package layer 300, which is not repeated herein.

Referring to fig. 16, the second package layer 310 is etched, and a second opening 311 exposing the back gold layer 450 is formed in the second package layer 310.

After the second opening 311 is formed, the second opening 311 exposes the back gold layer 450, so that the back gold layer 450 is electrically connected with other circuits.

In this embodiment, the second opening 311 exposes a portion of the back gold layer 450 of the second back surface 202. In other embodiments, the second opening may also expose the entire second backside gold layer according to actual process conditions.

In this embodiment, the second package layer 310 is etched by a laser etching process. In other embodiments, the process for etching the second encapsulation layer may also be a plasma etching process or a reactive ion etching process.

For a specific description of the process for etching the second package layer 310, reference may be made to the corresponding description of the process for etching the first package layer 300, and details are not repeated here.

The same parts of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that: the loading signal is a voltage signal.

Accordingly, referring to fig. 17, the step of forming the first opening 701 further includes: the first packaging layer 700, the second oxide layer 650 and the first oxide layer 550 are sequentially etched to expose the second pad 520 of the first chip 510.

By exposing the second bonding pads 520, a process foundation is provided for subsequently realizing the electrical connection between the second back side 602 of the second chip 600 and the second bonding pads 520.

In the process of forming the device wafer 500, the second bonding pads 520 are exposed from the first front side 501 of the device wafer 500, and the positions of the second bonding pads 520 on the first chip 510 are determined according to the relative positions of the second chip 600 and the first chip 510, so that the second chip 600 is exposed from the second bonding pads 520 after the second chip 600 is bonded to the device wafer 500; correspondingly, after the first opening 701 is formed in the first packaging layer 700, the second pad 520 can be exposed through the first opening 701, so that the process difficulty of exposing the second pad 520 is reduced.

For a detailed description of the device wafer 500, the second chip 610, the first package layer 700, and the first opening 701, please refer to the corresponding description in the foregoing embodiments, which is not repeated herein.

Referring to fig. 18, a back gold layer 850 is formed to cover the second chip 600 exposed from the first opening 701, the bottom and sidewalls of the first opening 701, and the first encapsulation layer 700.

In this embodiment, the second back surface 602 of the second chip 600 is suitable for being loaded with a voltage, so that the second back surface 602 is suitable for being electrically connected to the second bonding pads 520, and thus the voltage can be loaded on the second back surface 602 through the second bonding pads 520.

Correspondingly, in the step of forming the back gold layer 850, the back gold layer 850 is further formed on the surface of the second pad 520, and the back gold layer 850 is electrically connected to the second pad 520, so that the second back surface 602 and the second pad 520 are electrically connected through the back gold layer 850.

In this embodiment, the gold back layer 850 conformally covers the second chip 600, the bottom and sidewalls of the first opening 701, and the top of the first encapsulation layer 700.

For a detailed description of the back gold layer 850, please refer to the corresponding description in the foregoing embodiments, which is not repeated herein.

Referring to fig. 19, after the back gold layer 850 is formed, a second encapsulation layer 710 covering the back gold layer 850 is formed in the first opening 701, and the second encapsulation layer 710 also covers the metal layer structure 800 on the top of the first encapsulation layer 700.

Since the back gold layer 850 is electrically connected to the second pads 520, the second back surface 602 can be electrically connected to an external circuit by electrically connecting the second pads 520 to the external circuit, so as to apply a voltage signal to the second back surface 602.

For a detailed description of the second package layer 710, please refer to the corresponding description in the foregoing embodiments, which is not repeated herein.

Correspondingly, the invention also provides a wafer level packaging structure. With continued reference to fig. 16, a schematic structural diagram of an embodiment of the wafer level package structure of the present invention is shown.

The wafer level package structure includes: a device wafer 100, wherein a plurality of first chips 110 are formed in the device wafer 100, and the device wafer 100 includes a first front side 101 on which the first chips 110 are formed and a first back side 102 opposite to the first front side 101; a plurality of second chips 200 bonded to the device wafer 100, wherein the second chips 200 include a second front surface 201 formed with first pads 210 and a second back surface 202 opposite to the second front surface 201, and the second front surface 201 is opposite to the first front surface 101 and is bonded thereto by a low-temperature fusion bonding process; a first packaging layer 300 located on a portion of the device wafer 100, wherein a first opening 301 (as shown in fig. 14) exposing at least one second chip 200 is formed in the first packaging layer 300, and a second back surface 202 exposed by the first opening 301 is suitable for loading signals; the back gold layer 450 covers the second chip 200 exposed from the first opening 301, the bottom and the sidewall of the first opening 301, and the first encapsulation layer 300.

In this embodiment, the wafer level package structure is a wafer level system package structure.

In this embodiment, a plurality of first chips 110 are integrated in the device wafer 100, and the plurality of second chips 110 may be chips of the same type or different types.

In this embodiment, a second pad 120 is formed on a surface of the first chip 110 facing the first front surface 101. The second bonding pads 120 may be wire bonding pads, and the second bonding pads 120 are used for electrically connecting the first chip 110 and other semiconductor devices.

For convenience of illustration, the device wafer 100 of the present embodiment is described by taking three first chips 110 as an example. The number of the first chips 110 is not limited to three.

The second chip 200 is integrated in the wafer level package structure, and the second chip 200 may be one or more of an active element, a passive element, a micro electro mechanical system, an optical element, and the like. Specifically, the second chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the first chip may also be other functional chips.

In this embodiment, the second chips 200 are obtained by cutting a plurality of wafers with different function types. In other embodiments, the functional types of the plurality of first chips may also be the same according to actual process requirements.

It should be noted that the wafer level packaging method of the present embodiment is used to implement heterogeneous integration, and therefore the plurality of second chips 200 are chips made of silicon wafers. In other embodiments, the first chip may also be a chip formed by other materials.

A first bonding pad 210 is formed in the second chip 200, the first bonding pad 210 is exposed on the second front surface 201 of the second chip 200, and the first bonding pad 210 is used for electrically connecting the second chip 200 with other circuits. In this embodiment, the first pad 210 is a lead pad.

The second chip 200 and the device wafer 100 are bonded through a low-temperature fusion bonding process, and fusion bonding is a process of mainly using interfacial chemical force to complete bonding, so that the second chip 200 and the device wafer 100 have higher bonding strength, and the yield and reliability of the packaging structure are improved.

For this, in this embodiment, a first oxide layer 150 is formed on the first front surface 101, a second oxide layer 250 is formed on the second front surface 201, the second oxide layer 250 is disposed opposite to the first oxide layer 150 and is bonded by a low temperature fusion bonding process, and the second oxide layer 250 and the first oxide layer 150 are used to realize a physical connection between the device wafer 100 and the second chip 200.

The contact surfaces of the first oxide layer 150 and the second oxide layer 250 are connected in a covalent bond manner, so that the first oxide layer 150 and the second oxide layer 250 have higher bonding strength, thereby being beneficial to improving the yield and reliability of the wafer-level packaging structure.

The material of the second oxide layer 250 is the same as the material of the first oxide layer 150, so that covalent bonding can be achieved well, which is beneficial to further improving the bonding strength between the second oxide layer 250 and the first oxide layer 150.

In this embodiment, the material of the first oxide layer 150 and the second oxide layer 250 is silicon oxide. The silicon oxide material has higher process compatibility, and the silicon oxide is a material which is commonly used in the process and has lower cost, so the silicon oxide material is selected, the process difficulty and the process cost are favorably reduced, and the influence on the performance of the wafer-level packaging structure is reduced; moreover, the contact surfaces of the first oxide layer 150 and the second oxide layer 250 are bonded by covalent bonds of Si-O-Si, and since the bond energy of the Si-O bonds is large, the bonding strength between the second chip 200 and the device wafer 100 can be effectively improved.

In other embodiments, the first oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide, and the second oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide.

In this embodiment, in order to reduce the process difficulty, the following is providedThe first oxide layer 150 and the second oxide layer 250 are equal in thickness. However, the thicknesses of the first oxide layer 150 and the second oxide layer 250 are not necessarily too small, and are not necessarily too large. If the thickness is too small, the uniformity and quality of the thickness of the first oxide layer 150 and the second oxide layer 250 are easily reduced, and the bonding strength between the first oxide layer 150 and the second oxide layer 250 is also easily adversely affected; if the thickness is too large, the whole thickness of the wafer level packaging structure is correspondingly caused to be too large, which is not beneficial to improving the process integration level. For this reason, in this embodiment, the first oxide layer 150 and the second oxide layer 250 have both thicknesses

To

The first packaging layer 300 covers the second chip 200 and the device wafer 100, and can play a role in sealing and moisture protection, so that the probability that the first chip 110 and the second chip 200 are damaged, polluted or oxidized is reduced, and the performance of the wafer-level packaging structure is further optimized; moreover, the first encapsulation layer 300 encapsulates the plurality of second chips 200, and can support the second chips 200, thereby improving process operability during the preparation of the wafer level package structure.

In this embodiment, the material of the first encapsulation layer 300 is Epoxy resin (Epoxy). Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, low cost and the like, and is widely used as a packaging material for electronic devices and integrated circuits. In other embodiments, the material of the first encapsulation layer 300 may also be a thermosetting material such as polyimide or silicone.

It should be noted that, in this embodiment, the second oxide layer 250 is also located on the surface of the first oxide layer 150 exposed by the second chip 200, so that the generation of a gap between the device wafer 100 and the second chip 200 can be effectively reduced, air and moisture can be better isolated, the packaging effect is improved, and further, the performance of the wafer-level packaging structure is favorably optimized; moreover, the bonding strength between the device wafer 100 and the second chip 200 can be further improved.

A first opening 301 is formed in the first package layer 300, and the first opening 301 exposes at least the second back surface 202 suitable for loading signals, so as to provide a spatial location for forming the back gold layer 450, thereby enabling the second back surface 202 exposed by the opening 301 to be used for loading signals.

In this embodiment, the first opening 301 exposes only one second chip 200. In other embodiments, the number of the second chips exposed by the first opening is not limited to one, and may be determined according to actual process requirements.

In this embodiment, the loading signal is a ground signal.

For this reason, in this embodiment, the bottom of the first opening 301 exposes the surface of the second oxide layer 250, so as to prevent the first opening 301 from exposing the second pad 120 of the first chip 110.

The back gold layer 450 is used as a back electrode of the second chip 200, so that a signal can be loaded on the second back side 202 suitable for loading a signal according to actual process requirements, and the wafer level package structure has high usability.

In this embodiment, the loading signal is a ground signal, so the back gold layer 450 of the second back surface 202 is used as an electrode for loading the ground signal to the second chip 200.

In this embodiment, the back gold layer 450 is subjected to alloy treatment, so that the self resistance of the second chip 200 and the contact resistance between the second back surface 202 and the back gold layer 450 are relatively low, and accordingly, the ground impedance can be reduced, thereby reducing the loss of electric energy and being beneficial to improving the performance and reliability of the wafer level package structure.

Therefore, in this embodiment, the back gold layer 450 is a metal stacked structure, so that properties of different metals can be utilized to enable characteristics of the back gold layer 450 to meet process requirements.

Specifically, referring to fig. 4 in combination, an enlarged view of the back gold layer is shown, the back gold layer 450 including a bottom metal layer 410, a transition metal layer 420 on the bottom metal layer 410, and a top metal layer 430 on the transition metal layer 420.

For this reason, in this embodiment, the material of the bottom metal layer 410 is Ti. The Ti and the second back surface 202 material have good wettability, ohmic contact is easy to form, and the process difficulty for forming high-purity Ti is low, so that the process difficulty for forming the back gold layer 450 is reduced by selecting Ti as the bottom metal layer material; in addition, the chemical properties and mechanical properties of Ti are relatively stable and have a better thermal match with the material of the second backside 202, thus significantly improving the performance and reliability of the wafer level package structure. In other embodiments, the bottom metal layer may also be Cr, Al, or V.

The larger the thickness of the bottom metal layer 410 is, the larger the resistance of the bottom metal layer 410 is, so the thickness of the bottom metal layer 410 is not too large, otherwise, the performance and reliability of the wafer level package structure are easily reduced, and the waste of process resources is caused. However, the thickness of the bottom metal layer 410 is not necessarily too small, and if the thickness of the bottom metal layer 410 is too small, the quality and performance of the back metal layer 450 are easily reduced, and accordingly, the performance and reliability of the wafer level package structure may also be reduced. For this purpose, in this embodiment, the thickness of the bottom metal layer 410 is

To

For this reason, in the present embodiment, the material of the top metal layer 430 is Ag. Since Ag is a material that is commonly used in the process and has a low cost, it is also beneficial to reduce the process difficulty and the process cost by selecting Ag as the material of the top metal layer 430. In other embodiments, the material of the top metal layer 430 may also be Au.

The top metal layer 430 has a larger thickness, so that the protection effect on the transition metal layer 420 can be effectively improved, and when a ground signal is loaded on the back metal layer 450, the reliability of the back metal layer 450 can be improved, so that the performance stability of the wafer-level packaging structure is improved; however, the thickness of the top metal layer 430 is not suitable for being too large, and if the thickness of the top metal layer 430 is too large, the resistance of the top metal layer 430 is too large, which may easily reduce the performance and reliability of the wafer level package structure and cause waste of process resources. For this purpose, in this embodiment, the thickness of the top metal layer 430 is

To

To

In this embodiment, since the back gold layer 450 is subjected to an alloy treatment, an alloy (not shown) is formed on a contact surface between the bottom metal layer 410 of the back gold layer 450 and the second back surface 202.

Specifically, the bottom metal layer 410 is made of Ti, the substrate of the second chip 200 is a silicon substrate, and accordingly, a TiSi alloy is formed on a contact surface between the bottom metal layer 410 in the back gold layer 450 and the second back surface 202, so that ohmic contact is realized.

Note that, the TiSi alloy is formed on the contact surface between the bottom metal layer 410 of the back gold layer 450 and the second back surface 202, and therefore, for convenience of illustration, the back gold layer 450 of the second back surface 202 and the back gold layer 450 of other regions are represented by different coatings.

In this embodiment, the back gold layer 450 conformally covers the second chip 200 exposed by the first opening 301, the bottom and sidewalls of the first opening 301, and the top of the first encapsulation layer 300. In other embodiments, the back gold layer 450 may also be filled in the first opening.

In this embodiment, the package structure further includes: the second package layer 310 covers the back gold layer 450, a second opening 311 is formed in the second package layer 310, and the second opening 311 exposes the back gold layer 450 of the second back surface 202.

Specifically, the second package layer 310 is located in the first opening 301 and covers a portion of the back gold layer 450, and the second package layer 310 further covers the back gold layer 450 on top of the first package layer 300.

The second package layer 310 is used to protect the back gold layer 450, so as to prevent the back gold layer 450 from being affected by an external environment, and further avoid affecting the performance of the wafer level package structure.

The second opening 311 exposes the gold-backed layer 450 of the second back surface 202, thereby enabling electrical connection of the second back surface 202 to other circuits.

The wafer level package structure of this embodiment may be formed by the wafer level package method of the first embodiment, or may be formed by other package methods. In this embodiment, for specific description of the wafer level package structure, reference may be made to the corresponding description in the first embodiment, and details of this embodiment are not repeated herein.

With continuing reference to fig. 19, a schematic structural diagram of another embodiment of the wafer level package structure of the present invention is shown.

This embodiment is the same as the previous embodiment and is not as cumbersome herein. The present embodiment is different from the previous embodiment in that: the loading signal is a voltage signal.

Correspondingly, the first opening 701 (as shown in fig. 18) penetrates through the first package layer 700, the second oxide layer 650 and the first oxide layer 550, the bottom of the first opening 701 exposes the bonding pad of the first chip 510 corresponding to the second chip 600 to be loaded with a signal, and the gold-backed layer 450 is also located on the surface of the second bonding pad 520 exposed by the first opening 701.

The back gold layer 450 is electrically connected to the second pad 520, so that the second back 602 is electrically connected to the second pad 520 through the back gold layer 450, and a voltage signal can be applied to the second back 602 to which a signal is to be applied through the first chip 510 corresponding to the second chip 600 to which a signal is to be applied.

Therefore, in this embodiment, the projection of the second chip 600 on the first front surface 501 of the device wafer 500 is located on one side of the second bonding pad 520, so that the first opening 701 is exposed out of the second bonding pad 520, and the process difficulty of exposing the second bonding pad 520 is reduced.

The wafer level package structure of this embodiment may be formed by the wafer level package method of the second embodiment, or by other package methods. In this embodiment, for specific description of the wafer level package structure, reference may be made to corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A wafer level packaging method, comprising:

providing a device wafer, wherein a plurality of first chips are formed in the device wafer, and the device wafer comprises a first front side on which the first chips are formed and a first back side opposite to the first front side;

providing a bearing substrate, and temporarily bonding a plurality of second chips on the bearing substrate, wherein the second chips comprise a second front surface and a second back surface, the second front surface is formed with first bonding pads, the second back surface is opposite to the second front surface, and the second front surface faces the bearing substrate;

forming a first packaging layer covering the plurality of second chips on the bearing substrate;

after the first packaging layer is formed, removing the bearing substrate;

after the bearing substrate is removed, the first front surface and the second front surface are oppositely arranged, and the bonding of the device wafer and the second chip is realized by adopting a low-temperature fusion bonding process;

after the low-temperature fusion bonding process, forming a first opening exposing at least one second chip in the first packaging layer, wherein the second back surface exposed by the first opening is suitable for loading signals;

and forming a back gold layer to cover the second chip exposed from the first opening, the bottom and the side wall of the first opening and the first packaging layer.

2. The packaging method of claim 1, further comprising: forming a first oxide layer on the first front surface; forming a second oxide layer on the second front surface;

and carrying out the low-temperature melting bonding process through the first oxide layer and the second oxide layer.

3. The packaging method according to claim 2, wherein the second oxide layer is formed on the second front surface before the plurality of second chips are temporarily bonded on the carrier substrate; or after removing the bearing substrate, forming the second oxide layer covering the first packaging layer and the second front surface.

4. The packaging method of claim 1, wherein the step of forming the back gold layer comprises: forming a metal layer structure to cover the second chip exposed by the first opening, the bottom and the side wall of the first opening and the top of the first packaging layer; and carrying out alloying treatment on the metal layer structure.

5. The wafer level packaging method of claim 1, wherein the packaging method further comprises: and forming a second packaging layer to cover the back gold layer.

6. The wafer level packaging method of claim 5, wherein the loading signal is a ground signal; after the second packaging layer is formed, the method further comprises the following steps: and forming a second opening in the second packaging layer to expose the back gold layer on the second back surface.

7. The wafer-level packaging method of claim 1, wherein the loading signal is a voltage signal; a second bonding pad is formed on the surface, facing the first front surface, of the first chip;

the step of forming the first opening further comprises: sequentially etching the first packaging layer, the second oxidation layer and the first oxidation layer to expose the second bonding pad;

in the step of forming the gold back gold layer, the back gold layer is also formed on the surface of the second bonding pad.

8. The wafer-level packaging method of claim 2, wherein the step of the low-temperature fusion bonding process comprises: sequentially carrying out plasma activation treatment, deionized water cleaning treatment and drying treatment on the surface of the first oxidation layer and the surface of the second oxidation layer;

after the drying treatment, the second oxidation layer and the first oxidation layer are oppositely arranged and attached, and bonding pressure is applied to the device wafer and the second chip to carry out pre-bonding treatment;

and after the pre-bonding treatment, annealing the device wafer and the second chip.

9. The wafer level packaging method of claim 1, wherein the back gold layer comprises a bottom metal layer, a transition metal layer on the bottom metal layer, and a top metal layer on the transition metal layer.

10. The wafer-level packaging method of claim 8, wherein the reactive gas used in the plasma activation process comprises Ar, N₂、O₂And SF₆One or more of (a).

11. The wafer-level packaging method of claim 9, wherein the bottom metal layer is made of Ti, Cr, Al or V, the transition metal layer is made of Ni, and the top metal layer is made of Ag or Au.

12. The wafer-level packaging method of claim 4, wherein the alloying process is an annealing process.

13. A wafer level package structure, comprising:

the chip packaging structure comprises a device wafer, a first chip and a second chip, wherein a plurality of first chips are formed in the device wafer, and the device wafer comprises a first front side on which the first chips are formed and a first back side opposite to the first front side;

the second chips are bonded on the device wafer and comprise second front surfaces and second back surfaces, the second front surfaces are formed with first bonding pads, the second back surfaces are opposite to the second front surfaces, and the second front surfaces and the first front surfaces are oppositely arranged and bonded through a low-temperature melting bonding process;

the first packaging layer is positioned on part of the device wafer, a first opening for exposing at least one second chip is formed in the first packaging layer, and a second back surface exposed from the first opening is suitable for loading signals;

and the back gold layer covers the second chip exposed from the first opening, the bottom and the side wall of the first opening and the first packaging layer.

14. The wafer level package structure of claim 13, wherein the package structure further comprises: and the second packaging layer covers the back gold layer.

15. The wafer level package structure of claim 14, wherein the loading signal is a ground signal; a second opening is formed in the second packaging layer, and the second opening exposes the back gold layer on the second back surface.

16. The wafer-level package structure of claim 13, wherein the loading signal is a voltage signal;

a second bonding pad is formed on the surface, facing the first front surface, of the first chip;

the first opening penetrates through the first packaging layer and the first oxidation layer, and the second bonding pad is exposed;

the metal layer structure is positioned on the surface of the second bonding pad exposed by the first opening.

17. The wafer level package structure of claim 13, wherein the back gold layer comprises a bottom metal layer, a transition metal layer on the bottom metal layer, and a top metal layer on the transition metal layer.

18. The wafer-level package structure of claim 17, wherein the bottom metal layer is made of Ti, Cr, Al, or V, the transition metal layer is made of Ni, and the top metal layer is made of Ag or Au.

19. The wafer-level package structure of claim 13, wherein the first front surface is formed with a first oxide layer; a second oxide layer is formed on the second front surface;

the second oxide layer is arranged opposite to the first oxide layer and bonded through a low-temperature melting bonding process.

20. The wafer-level package structure of claim 19, wherein the second oxide layer is further located on a surface of the first oxide layer exposed by the second chip.