CN110869863A - Signal processing method and system and related equipment - Google Patents
Signal processing method and system and related equipment Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
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Abstract
The embodiment of the invention discloses a signal processing method, a signal processing system and related equipment, which are used for intelligently positioning a fault input port of an FPGA (401). The method provided by the embodiment of the invention comprises the following steps: a field-editable gate array (FPGA) (401) receives an input signal (101); the FPGA (401) judges whether the input signal meets a preset input condition (102), and if not, the input signal is determined to be an interference signal; the FPGA (401) judges whether the frequency of sending the interference signal by the input port in the preset time exceeds a preset critical value (103), and if so, the FPGA reports the input port (104) corresponding to the interference signal. The embodiment of the invention can intelligently position the fault input port of the FPGA (401), and can ensure the normal operation of the FPGA (401) when the fault input port occurs.
Description
The present invention relates to the field of industrial control, and in particular, to a signal processing method and system and related devices.
An FPGA (Field Programmable Gate Array) is a semi-custom circuit in the Field of Application Specific Integrated Circuits (ASICs), which not only solves the disadvantages of custom circuits, but also overcomes the drawback of limited Gate circuits of the original Programmable devices, and is a main hardware platform for the current digital system design.
In the field of industrial control, a plurality of signals are generated to form a group of input signals, and the input signals are input into the FPGA for processing. In the industrial control field, the control system receives a group of multiple wrong signals due to the fact that the interference signals or input switching signals are failed, and therefore control failure of the system is caused.
In the prior art, when an interference signal or an input switching signal fails, the control system receives a group of multiple wrong signals, so that system control fails, and when the industrial system needs to be waited for stopping working for removing the fault, each input signal is manually checked, so that manpower is wasted, and the working efficiency of the industrial system is reduced.
Disclosure of Invention
A first aspect of an embodiment of the present invention provides a signal processing method, which may include:
receiving an input signal by a field-editable gate array FPGA;
the FPGA judges whether the input signal meets preset input conditions or not, and if not, the input signal is determined to be an interference signal;
the FPGA determines an input port corresponding to the input signal according to the interference signal;
and the FPGA judges whether the frequency of sending the interference signal by the input port exceeds a preset critical value within a preset time, and if so, the input port corresponding to the interference signal is reported.
A second aspect of the embodiments of the present invention provides a field-editable gate array FPGA, which is characterized by comprising an input device, an output device, a processor and a memory, wherein,
the input device is used for receiving an input signal;
the processor is configured to perform the method of:
judging whether the input signal meets a preset input condition or not, and if not, determining that the input signal is an interference signal;
and judging whether the frequency of sending the interference signal by the input port in preset time exceeds a preset critical value, and if so, reporting the input port corresponding to the interference signal.
A third aspect of the embodiments of the present invention provides a signal processing system, including a field-programmable gate array FPGA and an upper computer, where the FPGA is configured to:
receiving an input signal;
judging whether the input signal meets a preset input condition or not, and if not, determining that the input signal is an interference signal;
and judging whether the frequency of sending the interference signal by the input port in preset time exceeds a preset critical value, and if so, reporting the input port corresponding to the interference signal.
It can be seen from the above that, in the technical scheme provided in the embodiment of the present invention, when an input port of the FPGA fails and sends an interference signal to the FPGA at a high frequency, the FPGA can detect and record the number of times of occurrence of the interference signal within the preset time and the input port of the interference signal, and when the number of times of sending the interference signal within the preset time of the input port exceeds a preset critical value, the FPGA reports the input port to the host computer, and intelligently locates the failed input port, thereby avoiding a situation that the failed input port is manually checked one by one, and saving human resources.
FIG. 1 is a diagram illustrating an embodiment of a signal processing method according to an embodiment of the present invention;
FIG. 2 is a diagram of another embodiment of a signal processing method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of one embodiment of an FPGA in an embodiment of the present invention;
fig. 4 is a schematic diagram of an embodiment of a signal processing system according to the embodiment of the present invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention and the above-described drawings, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
For convenience of understanding, a specific flow of the embodiment of the present invention is described below, and referring to fig. 1, an embodiment of a signal processing method in the embodiment of the present invention includes:
101. the FPGA receives an input signal;
the FPGA can detect whether input signals exist in each input port or not in the operation process, and when the input signals exist in the input ports, the FPGA can receive the input signals.
102. The FPGA judges whether the input signal meets a preset input condition or not;
in practical application, the FPGA needs to detect the interference signal, the FPGA may preset an input condition, when the input signal does not meet the preset input condition, the input signal is determined to be the interference signal, step 103 is executed, and if the preset input condition is met, step 106 is executed.
103. The FPGA judges whether the frequency of sending interference signals by the input port in preset time exceeds a preset critical value or not;
in the time preset by the FPGA, the FPGA records the number of times of sending the interference signal by the same input port, when the number of times of sending the interference signal by the input port in the preset time exceeds the number of times of a preset critical value of the FPGA, the input port possibly fails, step 104 is executed, and if the number of times of sending the interference signal by the input port does not exceed the preset critical value, step 105 is executed.
104. The FPGA reports an input port to an upper computer;
when the FPGA judges that a certain input port has a fault, the FPGA can report the input port to the corresponding upper computer.
105. And the FPGA records the times of the interference signals again.
And when the times of the interference signals do not exceed a preset critical value within the preset time, the FPGA clears the recorded times and restarts recording the times of the interference signals.
106. The FPGA processes an input signal according to preset logic;
according to the technical scheme provided by the embodiment of the invention, when a certain input port of the FPGA has a fault and sends an interference signal to the FPGA at a high frequency, the FPGA can detect and record the times of the interference signal in the preset time and the input port of the interference signal, and when the times of sending the interference signal in the preset time of the input port exceeds a preset critical value, the FPGA reports the input port to an upper computer and intelligently positions the fault input port, so that the condition that the fault input port is manually checked one by one is avoided, and the manpower resource is saved.
The above embodiment describes a flow of a signal processing method in an embodiment of the present invention, and for convenience of understanding, the following describes in detail the signal processing method in an embodiment of the present invention, with reference to fig. 2, and another embodiment of the signal processing method in an embodiment of the present invention includes:
201. the FPGA receives an input signal;
the FPGA can detect whether each input port has level change in the operation process, for example, if a certain port is changed from low level to high level or from high level to low level, the FPGA can receive a level pulse signal of the port as an input signal.
202. The FPGA judges whether the pulse width of the input signal meets a preset width or not;
when the input port of the input signal is changed from low level to high level, the pulse width of the input signal is detected after the input signal is received, and the pulse width of the input signal is compared with the preset width, when the pulse width of the input signal is smaller than the preset width, the FPGA can judge that the input signal is an interference signal, the FPGA can not respond to the interference signal, and step 203 is executed, when the pulse width of the input signal is larger than the preset pulse width, the FPGA can judge that the input signal is a valid input signal, the FPGA can change the input value of the corresponding input port according to the input signal, the low level is changed into the high level, and step 207 is executed.
When the input port of the input signal is changed from high level to low level, the pulse width of the input signal is detected after the input signal is received, and the pulse width of the input signal is compared with the preset width, when the pulse width of the input signal is not less than the preset width, the FPGA can judge that the input signal is an interference signal, and execute step 203, when the pulse width of the input signal is less than the preset pulse width, the FPGA can judge that the input signal is a valid input signal, the FPGA can change the input value of the corresponding input port according to the input signal, change from high level to low level, and execute step 207.
Specifically, in an actual FPGA operation, when an existing input value of an input port is a low level and a preset pulse width is 1 second, when the FPGA detects that the input port is changed from the low level to the high level and the pulse width of the high level is 0.8 second, the FPGA can determine that an input signal of the input port is an interference signal, the FPGA keeps the input value of the input port at the low level, when the FPGA detects that the input port is changed from the low level to the high level and the pulse width of the high level is not less than 1 second, the FPGA can determine that the input signal of the input port is a valid input signal, and the FPGA changes the input value of the input port from the low level to the high level.
It is understood that the specific preset width parameter in practical application can be determined according to the practical requirement of the user, and is not limited herein.
203. The FPGA outputs the last effective output value to an upper computer or outputs an initial default value to the upper computer;
under the prior art, the effective input signal of every input port input of FPGA has corresponded an input value in FPGA, the input value of input port is high level or low level, the current value of these input values can be stored on FPGA's register, when FPGA judges the input signal of input port input and is interference signal, FPGA can last effective output value export for the host computer, it is special, when FPGA system first operation, when not storing last effective output value, FPGA can export initial default value for the host computer, in order to guarantee industrial system's operation.
204. The FPGA judges whether the frequency of sending interference signals by the input port in preset time exceeds a preset critical value or not;
in the time preset by the FPGA, the FPGA records the number of times of sending the interference signal by the same input port, when the number of times of sending the interference signal by the input port in the preset time exceeds a critical value preset by the FPGA, the input port may have a fault, step 205 is executed, and if the number of times of sending the interference signal by the input port does not exceed the critical value, step 206 is executed.
Specifically, the FPGA can start a timer with preset time to start timing when detecting that the input port has level change, the FPGA increases the number of times of recording the number of times of sending the interference signal by 1 when the FPGA determines that the input signal of the input port is the interference signal, and the FPGA can determine that the input port has a fault when the number of times of recording the number of times of sending the interference signal by the input port exceeds a preset critical value within the time of the timer.
205. And the FPGA reports the input port to the upper computer.
When the FPGA judges that a certain input port has a fault, the FPGA can report the input port to the corresponding upper computer.
206. And the FPGA records the times of the interference signals again.
And when the times of the interference signals do not exceed a preset critical value within the preset time, the FPGA clears the recorded times and restarts recording the times of the interference signals.
207. The FPGA processes effective input signals according to preset logic;
the embodiment may further include:
208. and the FPGA clears the numerical value for recording the frequency of sending the interference signal by the input port.
When the frequency of sending the interference signal by the input port does not exceed the preset critical value frequency of the FPGA within the preset time, the FPGA can judge that the input port is not in fault, the FPGA can clear the numerical value recording the frequency of sending the interference signal by the input port, re-record the frequency of the interference signal and circularly detect the fault of the FPGA system.
According to the technical scheme provided by the embodiment of the invention, when a certain input port of the FPGA has a fault and sends an interference signal to the FPGA at a high frequency, the FPGA can detect and record the times of the interference signal in the preset time and the input port of the interference signal, and when the times of sending the interference signal in the preset time of the input port exceeds a preset critical value, the FPGA reports the input port to an upper computer and intelligently positions the fault input port, so that the condition that the fault input port is manually checked one by one is avoided, and the manpower resource is saved.
Secondly, in this embodiment, when a certain input port breaks down and inputs an interference signal, the FPGA can output the last effective output value to the host computer or output the initial default value to the host computer, so that the normal operation of the FPGA system is ensured without shutdown maintenance, and the efficiency of the FPGA industrial system is improved.
The foregoing embodiment describes a signal processing method in an embodiment of the present invention, and referring to fig. 3, an FPGA in an embodiment of the present invention is described, where the FPGA in the embodiment of the present invention includes an input device 301, an output device 302, a processor 303, and a memory 304, where,
the input device 301 is for receiving an input signal;
the processor 303 is configured to perform the following steps:
judging whether the input signal meets a preset input condition or not, and if not, determining the input signal as an interference signal;
and judging whether the frequency of sending the interference signal by the input port in the preset time exceeds a preset critical value, and if so, reporting the input port corresponding to the interference signal.
The specific functions of the FPGA shown in this embodiment are similar to those described in the embodiment shown in fig. 1, and please refer to the embodiment shown in fig. 1 for details, which are not described herein again.
Optionally, the processor 303 is further configured to:
and when the input signal is judged to be the interference signal, outputting the initial default value to the upper computer or outputting the last effective output value to the upper computer when the input signal is judged to be the interference signal.
Preferably, the processor 303 determines whether the input signal satisfies a preset input condition the preset input condition includes:
and judging that the pulse width of the input signal meets a preset width condition.
Optionally, the processor 303 is further configured to perform the following steps:
and when the frequency of sending the interference signal by the input port does not exceed a preset critical value within preset time, resetting the numerical value for recording the frequency of inputting the interference signal by the input port.
The foregoing embodiment describes a signal processing method and an FPGA in the embodiment of the present invention, and a signal processing system in the embodiment of the present invention is described below, referring to fig. 4, an embodiment of the signal processing system in the embodiment of the present invention may include:
a field-programmable gate array FPGA401 and an upper computer 402, the FPGA401 being configured to perform the steps of:
receiving an input signal;
judging whether the input signal meets a preset input condition or not, and if not, determining the input signal as an interference signal;
and judging whether the frequency of sending the interference signal by the input port in the preset time exceeds a preset critical value, and if so, reporting the input port corresponding to the interference signal.
Optionally, when the input signal is determined to be an interference signal, the FPGA401 is further configured to perform the following steps:
and outputting the initial default value to the upper computer, or outputting the last effective output value to the upper computer.
Preferably, the determining, by the FPGA401, whether the input signal satisfies a preset input condition includes:
and judging that the pulse width of the input signal meets a preset width condition.
Optionally, the FPGA401 is further configured to perform the following steps:
and when the frequency of sending the interference signal by the input port does not exceed a preset critical value within preset time, resetting the numerical value for recording the frequency of inputting the interference signal by the input port.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (12)
- A signal processing method, comprising:receiving an input signal by a field-editable gate array FPGA;the FPGA judges whether the input signal meets preset input conditions or not, and if not, the input signal is determined to be an interference signal;and the FPGA judges whether the frequency of sending the interference signal by the input port exceeds a preset critical value within a preset time, and if so, the input port corresponding to the interference signal is reported.
- The signal processing method according to claim 1, wherein when the input signal is determined to be an interference signal, the method further comprises:the FPGA outputs the initial default value to an upper computer;or,and the FPGA outputs the last effective output value to an upper computer.
- The signal processing method of claim 1 or 2, wherein the preset input conditions comprise:the pulse width of the input signal meets a preset width condition.
- The signal processing method according to claim 1 or 2, wherein when the number of times the input port transmits the interference signal does not exceed a preset threshold value within a preset time, the method further comprises:and the FPGA clears the numerical value for recording the frequency of inputting the interference signal by the input port.
- A field-editable gate array FPGA, comprising an input device, an output device, a processor and a memory, wherein,the input device is used for receiving an input signal;the processor is configured to perform the method of:judging whether the input signal meets a preset input condition or not, and if not, determining that the input signal is an interference signal;and judging whether the frequency of sending the interference signal by the input port in preset time exceeds a preset critical value, and if so, reporting the input port corresponding to the interference signal.
- The FPGA of claim 5, wherein the processor is further configured to perform the steps of:and when the input signal is judged to be an interference signal, outputting the initial default value to the upper computer, or outputting the last effective output value to the upper computer.
- The FPGA of claim 5 or 6, wherein said preset input conditions comprise:the pulse width of the input signal meets a preset width condition.
- The FPGA of claim 5 or 6, wherein said processor is further configured to perform the steps of:and when the frequency of sending the interference signal by the input port does not exceed a preset critical value within preset time, clearing the numerical value recording the frequency of inputting the interference signal by the input port.
- A signal processing system comprises a field-editable gate array FPGA and an upper computer, wherein the FPGA is used for executing the following steps:receiving an input signal;judging whether the input signal meets a preset input condition or not, and if not, determining that the input signal is an interference signal;determining an input port corresponding to the interference signal;and judging whether the frequency of sending the interference signal by the input port in preset time exceeds a preset critical value, and if so, reporting the input port corresponding to the interference signal.
- The system of claim 8, wherein the FPGA is further configured to perform the steps of:and when the input signal is judged to be an interference signal, outputting the initial default value to the upper computer, or outputting the last effective output value to the upper computer.
- The system of claim 9 or 10, wherein the preset input conditions comprise:the pulse width of the input signal meets a preset width condition.
- The system of claim 9 or 10, wherein the FPGA is further configured to perform the steps of:and when the frequency of sending the interference signal by the input port does not exceed a preset critical value within preset time, clearing the numerical value recording the frequency of inputting the interference signal by the input port.
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| PCT/CN2017/085294 WO2018213973A1 (en) | 2017-05-22 | 2017-05-22 | Signal processing method and system, and relevant device |
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Application publication date: 20200306 |