CN110867910B - Charge-discharge activation circuit - Google Patents
Charge-discharge activation circuit Download PDFInfo
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- CN110867910B CN110867910B CN201810980928.9A CN201810980928A CN110867910B CN 110867910 B CN110867910 B CN 110867910B CN 201810980928 A CN201810980928 A CN 201810980928A CN 110867910 B CN110867910 B CN 110867910B
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- 230000004913 activation Effects 0.000 title claims abstract description 127
- 230000002093 peripheral effect Effects 0.000 claims abstract description 27
- 230000003213 activating effect Effects 0.000 claims abstract description 21
- 230000000087 stabilizing effect Effects 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000007599 discharging Methods 0.000 abstract description 24
- 230000007246 mechanism Effects 0.000 abstract description 4
- 230000004044 response Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 238000001514 detection method Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Abstract
The embodiment of the invention provides a charge-discharge activation circuit. In an embodiment of the present invention, a charge-discharge activation circuit includes: discharge activation circuit, charge activation circuit and gating circuit. The charging and discharging activating circuit can activate the BMS module to perform discharging management under the triggering of the triggering signal provided by the peripheral control circuit; the charge-discharge activation circuit can activate the BMS module to carry out charge management under the triggering of a direct current signal provided by an external power supply. The charge-discharge activation circuit provided by the embodiment of the invention combines the charge activation circuit and the discharge activation circuit through the gating circuit, can realize charge-discharge management of the BMS module, has a simple structure, can avoid a complex response mechanism, and is beneficial to improving the activation speed of the BMS.
Description
Technical Field
The invention relates to the technical field of battery management, in particular to a charge-discharge activation circuit.
Background
With the development of battery technology, the electric storage capacity of batteries is more and more powerful, so that the battery is widely applied to equipment such as mobile terminals, intelligent robots, electric automobiles and the like which need long-term power supply, and the battery can be ensured to be capable of long-term cruising.
With the increasing demands on battery endurance, multi-string battery packs are becoming increasingly popular. Along with the increase of the number of battery strings in the battery pack, the number of components is increased, the application circuit is more complex, and the stability of the battery pack is gradually reduced. In order to improve the stability and the utilization rate of the battery pack, a battery management system (Battery Management System, BMS) is developed, which can timely protect the battery from over-discharge, over-charge, over-temperature and other anomalies, so that the utilization rate of the battery pack is improved, and the service life of the battery pack is prolonged. However, the discharge activation circuit and the charge activation circuit in the existing activation circuit of the BMS are separately provided, and the structure is complicated, resulting in difficulty in charge-discharge activation of the BMS. There is a need to provide a new activation circuit for rapidly activating the BMS to perform charge and discharge management.
Disclosure of Invention
Aspects of the present invention provide a charge and discharge activation circuit for rapidly activating and charge and discharge managing a BMS of a battery pack.
The embodiment of the invention provides a charge-discharge activation circuit, which comprises: a discharge activation circuit, a charge activation circuit, and a gate circuit; the discharge activating circuit is electrically connected with the gating circuit and is electrically connected with the trigger signal output end of the peripheral control circuit; the charging activation circuit is electrically connected with the gating circuit and is electrically connected with a charging anode of the battery pack; and the gating circuit is electrically connected with the BMS module of the battery pack;
the gating circuit is used for operating in a first gating mode according to a gating signal from the discharging activating circuit so as to communicate the discharging activating circuit with the BMS module, or operating in a second gating mode according to a gating signal from the charging activating circuit so as to communicate the charging activating circuit with the BMS module;
the discharging activating circuit is used for outputting a gating signal to the gating circuit under the triggering of a triggering signal from the triggering signal output end so as to output the first activating signal to the BMS module through the gating circuit to activate the BMS module for discharging management;
the charging activation circuit is used for outputting a gating signal to the gating circuit under the triggering of a direct current signal provided by an external power supply, so that the gating circuit outputs the second activation signal to the BMS module to activate the BMS module for charging management.
The charge-discharge activation circuit provided by the embodiment of the invention comprises: discharge activation circuit, charge activation circuit and gating circuit. The discharge activating circuit is electrically connected with the gating circuit and is electrically connected with the trigger signal output end of the peripheral control circuit; the charging activation circuit is electrically connected with the gating circuit and is electrically connected with a charging anode of the battery pack; and the gating circuit is electrically connected with the BMS module of the battery pack. In this way, when the charge-discharge activating circuit is triggered by the trigger signal provided by the peripheral control circuit, a first activating signal is output to the BMS module to activate the BMS module for discharge management; and the charging and discharging activation circuit outputs a second activation signal to the BMS module under the triggering of a direct current signal provided by an external power supply so as to activate the BMS module to carry out charging management. The charge-discharge activation circuit provided by the embodiment of the invention can realize charge-discharge management of the BMS module at the same time, has a simple structure, can avoid a complex response mechanism, and is beneficial to improving the activation speed of the BMS.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1a is a schematic diagram of a charge-discharge activation circuit according to an embodiment of the present invention;
fig. 1b is a schematic diagram of a charge-discharge activation circuit with a charge-discharge port according to an embodiment of the present invention;
fig. 1c is a schematic diagram of a charge-discharge activation circuit with different charge-discharge ports according to an embodiment of the present invention;
fig. 2a is a schematic diagram of a charge-discharge activation circuit according to an embodiment of the present invention;
fig. 2b is a schematic structural diagram of a battery pack according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an operation of a peripheral control circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments of the present invention and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Aiming at the problem that the prior BMS is difficult to activate due to the complex structure of a charge-discharge activation circuit of the BMS, the embodiment of the invention provides the charge-discharge activation circuit. The charge-discharge activation circuit includes: discharge activation circuit, charge activation circuit and gating circuit. The discharge activating circuit is electrically connected with the gating circuit and is electrically connected with the trigger signal output end of the peripheral control circuit; the charging activation circuit is electrically connected with the gating circuit and is electrically connected with a charging anode of the battery pack; and the gating circuit is electrically connected with the BMS module of the battery pack. In this way, when the charge-discharge activating circuit is triggered by the trigger signal provided by the peripheral control circuit, a first activating signal is output to the BMS module to activate the BMS module for discharge management; and the charging and discharging activation circuit outputs a second activation signal to the BMS module under the triggering of a direct current signal provided by an external power supply so as to activate the BMS module to carry out charging management. The charge-discharge activation circuit provided by the embodiment of the invention combines the charge activation circuit and the discharge activation circuit through the gating circuit, can realize charge-discharge management of the BMS module, has a simple structure, can avoid a complex response mechanism, and is beneficial to improving the activation speed of the BMS.
The following describes in detail the technical solutions provided by the embodiments of the present invention with reference to the accompanying drawings.
It should be noted that: like reference numerals denote like objects in the following figures and examples, and thus once an object is defined in one figure, no further discussion thereof is required in the subsequent figures.
Fig. 1a is a schematic diagram of a charge-discharge activation circuit according to an embodiment of the present invention. As shown in fig. 1a, the charge-discharge activation circuit 100 includes: discharge activation circuit 100a, charge activation circuit 100b, and gate circuit 100c. The discharging activating circuit 100a is electrically connected with the gating circuit 100c and is electrically connected with a trigger signal output terminal TRIG of the peripheral control circuit 101; and the charge activation circuit 100b is electrically connected with the gate circuit 100C and with the charge positive electrode c+ of the battery pack 102, and the gate circuit is electrically connected with the BMS module 103 of the battery pack.
For the BMS module with the same charge and discharge port, the charge positive electrode c+ and the discharge positive electrode p+ of the battery pack are the same port, and are electrically connected with the positive electrode b+ of the battery pack 102; for a BMS module with different charge points, the charge positive electrode c+ and the discharge positive electrode p+ of the battery pack are two different ports, wherein the discharge positive electrode p+ is electrically connected with the positive electrode b+ of the battery pack 102. In this embodiment, the BMS module 103 includes an analog front end and an MCU. The analog front end is used for collecting the voltage of each battery cell of the battery pack 102 under the control of the MCU, and outputting MOS driving signals to the charge-discharge MOS tube under the control of the MCU. This part will be described in detail below.
Based on the charge and discharge activation circuit 100 shown in fig. 1a described above, the gate circuit 100c may operate in a first gate mode according to a gate signal from the discharge activation circuit 100a to communicate the discharge activation circuit 100a with the BMS module 103, or in a second gate mode according to a gate signal from the charge activation circuit 100b to communicate the charge activation circuit 100b with the BMS module 103. Accordingly, the discharge activation circuit 100a may output a gating signal to the gating circuit 100c under the triggering of the triggering signal output thereto by the peripheral control circuit 101, so as to output a first activation signal to the BMS module 103 through the gating circuit 100c, thereby enabling the BMS module 103 to perform discharge management. Also, the charging activation circuit may output a gating signal to the gating circuit 100c under the triggering of a direct current signal provided from an external power supply (not shown in fig. 1 a) to output a second activation signal to the BMS module 103 through the gating circuit 100c, thereby enabling the BMS module 103 to perform charging management.
The charge-discharge activation circuit provided by the embodiment combines the charge activation circuit and the discharge activation circuit through the gating circuit, so that charge-discharge management of the BMS module can be realized, the structure is simple, a complex response mechanism can be avoided, and the activation speed of the BMS can be improved.
It should be noted that, the charge-discharge activation circuit provided in this embodiment is not only suitable for the BMS module with the same charge-discharge port, but also suitable for the BMS module with different charge-discharge ports. For the BMS module with the same charge and discharge port, the schematic structure of the charge and discharge activation circuit is shown in fig. 1b. The discharging MOS tube 100d and the charging MOS tube 100e are located on the same branch, a first end of a charging and discharging MOS branch formed after the discharging MOS tube 100d and the charging MOS tube 100e are connected is connected with a negative electrode B-of the battery pack 102 and then grounded, and a second end of the charging and discharging MOS branch is electrically connected with a discharging negative electrode P-of the battery pack 102; and the third end of the charge-discharge MOS branch circuit is electrically connected with the BMS module 103, and the BMS module 103 provides a gating signal for the charge-discharge MOS branch circuit to perform MOS driving.
For the BMS with different charge and discharge ports, a schematic structure of the charge and discharge activation circuit is shown in fig. 1 c. The discharging MOS transistor and the charging MOS transistor are not on the same branch, i.e., the discharging MOS transistor 100f and the charging MOS transistor 100g shown in fig. 1 c. The first end of the discharging MOS tube 100f is electrically connected to the negative electrode B of the battery pack 102, the second end is electrically connected to the discharging negative electrode P of the battery pack 102, and the third end is electrically connected to the BMS module 103. The first end of the charging MOS tube 100g is electrically connected to the positive electrode b+ of the battery pack 102, the second end is connected to the charging positive electrode c+, and the third end is electrically connected to the BMS module 103. Thus, when the charge-discharge activation circuit 100 outputs the first activation signal to the BMS module 103, the BMS module 103 outputs the MOS drive to the discharge MOS tube 100f to operate the discharge MOS tube 100f, and the BMS module 103 performs the discharge management. When the charge-discharge activation circuit 100 outputs the second activation signal to the BMS module 103, the BMS module 103 outputs MOS driving to the charge MOS transistor 100g and the discharge MOS transistor 100f to operate the charge MOS transistor 100g and the discharge MOS transistor 100f, thereby causing the BMS module 103 to perform charge management.
Next, a specific circuit structure of the charge-discharge activation circuit will be described for the BMS of the same charge-discharge port.
Fig. 2a is a schematic diagram of a charge-discharge activation circuit according to an embodiment of the present invention. As shown in fig. 2a, the discharge activating circuit 100a includes: PNP triode circuit and N-MOS switch circuit. The emitter of the PNP triode circuit is electrically connected with the trigger signal output end TRIG of the peripheral control circuit 101; the base electrode of the PNP triode circuit is grounded; the collector of the PNP triode circuit is electrically connected with the grid electrode of the N-MOS switching circuit; and a capacitor C8 is connected in series between the collector and the emitter of the PNP triode circuit.
Correspondingly, the drain electrode of the N-MOS switch circuit is electrically connected with the gating circuit 100c and the positive electrode Bn of the nth battery of the battery pack 102 respectively; the source electrode of the N-MOS switch circuit is grounded; wherein n is a positive integer, and n is more than or equal to 1 and less than or equal to the total number of the battery pack.
Optionally, as shown in fig. 2a, the PNP transistor circuit includes: PNP transistor Q2 and diode D3. The emitter of the PNP transistor Q2 is electrically connected to the cathode of the diode D3, and the anode of the diode D3 is electrically connected to the trigger signal output terminal TRIG of the peripheral control circuit 101. The base of the PNP transistor Q2 is connected in series with the resistor R11 and is connected to the ground, and the series point of the base of the PNP transistor Q2 and the resistor R11 is electrically connected to the trigger signal output terminal TRIG of the peripheral control circuit 101. The collector of the PNP triode Q2 is connected with the ground after being connected with two pull-down resistors R12 and R13 in series, and the serial connection point of the two resistors R12 and R13 is electrically connected with the grid electrode of the N-MOS switching circuit.
Accordingly, as shown in fig. 2a, the N-MOS switch circuit includes: an N-MOS transistor Q3 and a voltage stabilizing transistor ZD2. The voltage stabilizing tube ZD2 is connected in series between the series connection point of the two pull-down resistors R12 and R13 and the ground, the negative electrode of the voltage stabilizing tube ZD2 is connected with the series connection point of the two resistors R12 and R13, and the positive electrode of the voltage stabilizing tube ZD2 is grounded. Specifically, after the voltage stabilizing tube ZD2 is connected in parallel with the resistor R13, one end of the negative electrode of the voltage stabilizing tube ZD2 is grounded; one end of the positive electrode of the voltage stabilizing tube ZD2 is electrically connected with the grid electrode of the N-MOS tube Q3. Thus, the gate electrode of the N-MOS transistor Q3 can be protected. The voltage stabilizing tube ZD2 can limit the grid voltage of the N-MOS tube Q3 to be below the voltage stabilizing value of the voltage stabilizing tube ZD2, and the grid of the N-MOS tube Q3 is protected from breakdown; the resistor R13 can release the electric charge of the grid electrode of the N-MOS tube Q3, prevent the electric charge from accumulating and further protect the grid electrode of the N-MOS tube Q3.
Further, the drain of the N-MOS transistor Q3 is electrically connected to the gate 100c, and the drain is electrically connected to the positive electrode Bn of the N-th battery after being connected in series to the resistor R14.
Accordingly, as shown in fig. 2a, the gating circuit 100c includes: P-MOS transistor Q4. The grid electrode of the P-MOS transistor Q4 is electrically connected with the drain electrode of the N-MOS switching circuit; the source electrode is electrically connected with the anode Bn of the nth battery; the drain electrode of the P-MOS transistor Q4 is connected with two pull-down resistors R16 and R17 in series and then grounded, and the serial connection point of the R16 and R17 of the two pull-down resistors is electrically connected with the BMS module 103.
Optionally, the gating circuit 100c further includes: and a filter capacitor C4. As shown in fig. 2a, one end of the filter capacitor C4 is connected to the series connection point of the two resistors R16 and R17, and the other end of the filter capacitor C4 is grounded.
Accordingly, as shown in fig. 2a, the charge activation circuit 100b includes: RC parallel circuit and opto-coupler isolator U1. The RC parallel circuit is formed by connecting a resistor R15 and a capacitor C5 in parallel, and a first end of the formed RC parallel circuit is electrically connected to the charging positive electrode c+ of the battery pack 102.
Correspondingly, the positive electrode of the light emitting diode in the opto-isolator U1 is connected to the second end of the RC parallel circuit, the negative electrode of the light emitting diode is connected in series with the diode D4 and then is also connected to the second end of the RC parallel circuit, the negative electrode of the diode D4 is electrically connected with the second end of the RC parallel circuit, and the positive electrode of the diode D4 is connected with the negative electrode of the light emitting diode. An emitter of the photosensitive PNP triode in the opto-coupler isolator U1 is electrically connected with a drain of the P-MOS transistor Q4 in the gating circuit 100c, and a collector of the photosensitive PNP triode is electrically connected with a source of the P-MOS transistor Q4.
For convenience in distinguishing and describing the positive and negative electrodes of the battery pack 102 and the positive and negative electrodes of the nth battery, the description will be made with reference to the schematic structure of the battery pack shown in fig. 2 b. As shown in FIG. 2b, the battery pack comprises m cells, m is equal to or greater than n, and m is a positive integer, the m cells are connected in series to form the battery pack, and the voltage of each cell is assumed to be U 0 . Wherein, the positive electrode of the battery pack 102 represents the positive electrode b+ of the 1 st battery after the m batteries are connected in series, the negative electrode of the battery pack 102 represents the negative electrode B-of the m battery after the m batteries are connected in series, and the voltage difference between the positive electrode b+ and the negative electrode B-of the battery pack 102 is the total voltage m×u of the battery pack 102 0 . When the negative electrode B of the battery pack 102 is grounded, then the total voltage of the battery pack 102 is the positive voltage of the battery pack 102. When the negative electrode B of the mth battery is grounded, the positive electrode voltage of the nth battery is the total voltage from the nth battery to the mth battery, namely the total voltage (m-n+1) of the m-n+1 batteries 0 。
It should be noted that, in the charge-discharge activation circuit shown in fig. 2a, each ground terminal is connected to the negative electrode B-of the mth battery and is grounded through the negative electrode B-of the mth battery.
In order to more clearly understand the specific operation principle of the charge-discharge activation circuit, the following is an exemplary description in connection with the operation principle diagram of the peripheral control circuit shown in fig. 3 and the charge-discharge activation circuit shown in fig. 2 a.
First, the operation principle of the peripheral control circuit shown in fig. 3 will be described. As shown in fig. 3, the peripheral control circuit 101 includes a switching circuit 101a. Wherein the switching circuit 101a includes: a switch K1, a voltage regulator ZD1 and a diode D1; one end A1 of the switch K1 is connected with the positive electrode of the voltage stabilizing tube ZD1, and the other end A2 is electrically connected with the positive electrode of the diode D1; the negative electrode of the voltage stabilizing tube ZD1 is electrically connected with the discharging positive electrode P+ of the battery pack 102; and the negative electrode of the diode D1 is connected in series with the resistor R1 and then electrically connected to the charge/discharge activation circuit 100. Thus, when the switch K1 is pressed, the voltage regulator ZD1 is reverse-broken down and turned on, and accordingly, the diode D1 is turned on, and the switching circuit 101a is turned on, and a trigger signal is output to the charge/discharge activation circuit 100, so that the charge/discharge activation circuit 100 activates the BMS module 103 to perform discharge management.
Optionally, as shown in fig. 3, the peripheral control circuit 101 further includes: a switch detection circuit 101b. The switch detection circuit 101b includes an N-MOS transistor Q1. The grid electrode of the N-MOS tube Q1 is connected with two resistors R2 and R3 in series and then is electrically connected with the positive electrode of the diode D1, specifically, the grid electrode of the N-MOS tube Q1 is connected with the two resistors R2 and R3 in series and then is connected with the A2 end of the switch K1; furthermore, the series connection point of the two resistors R2 and R3 is grounded through the resistor R4. Correspondingly, the source electrode of the N-MOS tube Q1 is grounded; the drain electrode of the N-MOS transistor Q1 is connected IN series with a pull-up resistor R5, and then electrically connected to an internal power supply VCC of the tool board MCU (not shown IN fig. 3), and is grounded through a series capacitor C1, and is electrically connected to a KEY detection end KEY-IN of the tool board MCU. The main working principle is as follows: when the switch K1 is turned off, the N-MOS transistor Q1 works IN a cut-off state, and the drain voltage of the N-MOS transistor Q1 is high under the action of the pull-up resistor R5, so that the KEY detection end KEY-IN of the tool board MCU detects that the level is high. When the switch K1 is turned on, since the gate of the N-MOS transistor Q1 is electrically connected to the discharge anode p+ of the battery pack 102 and the source thereof is grounded, the voltage difference between the gate and the source of the N-MOS transistor Q1 is greater than the turn-on voltage thereof, the N-MOS transistor Q1 is turned on, the drain of the N-MOS transistor Q1 is grounded and the level thereof jumps to a low level, and the KEY detection end KEY-IN of the tool board MCU detects that the level thereof is a low level. Therefore, the tool board MCU can determine whether the switch K1 is turned on by detecting the jump of the drain level of the N-MOS transistor Q1 in the switch detection circuit 101b.
It should be noted that, in the present embodiment, the internal power VCC of the tool board MCU can be obtained by performing voltage conversion through the battery pack 102. Alternatively, the positive and negative poles of the battery pack 102 may be connected to a power management chip circuit to convert the voltage of the battery pack 102 to a voltage adapted to the tool board MCU. Wherein, power management chip circuit is used for: when the battery pack 102 is discharged, the voltage of the battery pack 102 is converted into a voltage suitable for the tool board MCU to supply power to the tool board MCU, so that the tool board MCU can be prevented from being burnt out due to the fact that the voltage is too high.
Next, the operation principle of the charge-discharge activation circuit shown in fig. 2a will be described with reference to the peripheral control circuit shown in fig. 3.
As shown in fig. 3, when the switch K1 is closed, the trigger signal output terminal TRIG of the peripheral control circuit 101 outputs a trigger signal to the trigger signal receiving terminal TRIG of the discharge activating circuit 100a, and the trigger signal is a high voltage (total voltage m×u of the battery pack 102 in combination with the peripheral control circuit 101 shown in fig. 3 0 ). Therefore, in the charge-discharge activation circuit shown in fig. 2a, the diode D3 of the discharge activation circuit 100a is turned on, the capacitor C8 is charged with a large current instantaneously, and then the gate voltage of the N-MOS transistor Q3 is a divided voltage of the total voltage of the battery pack 102, and the source of the N-MOS transistor Q3 is grounded, so that the voltage difference between the gate and the source of the N-MOS transistor Q3 is greater than the turn-on voltage of the N-MOS transistor Q3, and the N-MOS transistor Q3 is turned on. When the N-MOS transistor Q3 is turned on, the gate of the P-MOS transistor Q4 is grounded through the drain and source of the N-MOS transistor Q3, and the source of the P-MOS transistor Q4 is electrically connected with the positive electrode Bn of the nth battery of the battery pack 102, so that the source voltage of the P-MOS transistor Q4 is the total voltage from the nth battery to the mth battery of the battery pack 102, namely the voltage (m-n+1) U of the m-n+1 battery in the battery pack 102 0 Therefore, the source voltage of the P-MOS Q4 is greater than the gate voltage thereof, and the voltage difference between the source voltage and the gate voltage is greater than the turn-on voltage of the P-MOS Q4, so that the P-MOS Q4 is turned on, i.e., the gate circuit 100c operates in the first gate mode, and the discharge activation circuit 100a is connected to the BMS module 103.
Correspondingly, when the P-MOS Q4 is turned on, the drain electrode thereof is divided by the voltage dividing resistor R16 and then outputs a first activation signal to the BMS module 103 through the activation signal output terminal TS1, so as to activate the BMS module 103 for discharge management. Alternatively, when the BMS module 103 receives the first activation signal, the BMS module 103 may be activated for discharge management.
Further, it is available to combine the peripheral control circuit 101 shown in fig. 3 and the discharge activation circuit 100a shown in fig. 2a that when the switch K1 is turned off, the P-MOS transistor Q4 is operated in the off state, the drain level thereof is low, and when the switch K1 is turned on, the P-MOS transistor Q4 is turned on, the drain voltage thereof is the positive voltage (m-n+1) of the nth battery 0 Is high. Thus, the first activation signal may be the nth sectionThe divided value of the positive electrode voltage of the battery may be a pulse signal formed by a rising edge of a low level transition to a high level or a low level transition to a high level.
On the other hand, for the PNP transistor Q2 in the discharging activation circuit 100a, when the trigger signal receiving terminal TRIG of the discharging activation circuit 100a receives the high voltage output by the peripheral control circuit 101, since the voltage values of the emitter and the base of the PNP transistor Q2 are both the high voltage of the trigger signal receiving terminal TRIG of the discharging activation circuit 100a, the PNP transistor Q2 works in the off state, and therefore, the voltage of the trigger signal receiving terminal TRIG of the discharging activation circuit 100a is pulled down to the voltage of the negative electrode B-of the mth battery, that is, the ground voltage 0, under the action of the pull-down resistor R11, the discharging activation circuit 100a can realize effective self-turn-off after activating the BMS module 103, which is helpful for reducing the static self-consumption thereof. And when the BMS module 103 is dormant, the static consumption of the charge-discharge activation circuit 100 may be controlled at the μa level. Alternatively, the pull-down resistor R11 may have a resistance of mΩ.
Further, the operation principle of the charge activation circuit 100b shown in fig. 2a will be described. As shown in fig. 2a, when the battery pack 102 is charged, the positive and negative poles of the battery pack 102 are connected to a dc power supply, and for the BMS module with the same charge and discharge port, the positive and negative poles of the battery pack 102 are ports p+ and P-, wherein the ports p+ and P-are electrically connected to the positive and negative poles b+ and B-of the battery pack 102 respectively; for the BMS module with different charge and discharge ports, the charge negative electrode and the discharge negative electrode of the battery pack 102 are ports P-, but the charge positive electrode and the discharge positive electrode are different in ports, and the charge positive electrode and the discharge positive electrode of the battery pack 102 are ports c+ and p+. Correspondingly, when the power supply terminal p+/P- (same port) or c+/P- (different port) of the charging activation circuit 100b has a dc signal, the capacitor C5 is charged instantaneously with a large current, the led of the optoisolator U1 is turned on and emits light, so that the internal phototransistor is turned on and outputs a high level with a level value similar to the positive voltage (m-n+1) U of the nth battery 0 . The source of the P-MOS transistor Q4 of the gating circuit 100c is connected to the collector of the phototransistor, so that the source voltage of the P-MOS transistor Q4 is approximately equal to the positive voltage (m-n+1) U of the nth battery 0 . P-MOS transistor Q4 is the positive voltage (m-n+1) U of the nth battery 0 Therefore, the source voltage of the P-MOS transistor Q4 is equal to the gate voltage thereof, so that the P-MOS transistor Q4 is not conductive, i.e. the gating circuit 100c receives the high level of the output of the phototransistor, the level of which is similar to the positive voltage (m-n+1) U of the nth battery cell 0 When the battery is operated in the second gating mode, the charging activation circuit 100b is connected to the BMS module 103, and the BMS module 103 can be activated to perform charging management.
Correspondingly, after the drain electrode of the P-MOS transistor Q4 is divided by the voltage dividing resistor R16, a second activation signal is output to the BMS module 103 through the activation signal output terminal TS1, so that the BMS module 103 can be activated to perform charging management.
Further, in conjunction with the charge activation circuit 100b shown in fig. 2a, when the power supply terminal p+/P- (same port) or c+/P- (different port) of the charge activation circuit 100b has no dc signal, the phototransistor is not turned on, so the second activation signal may be a divided voltage value of the voltage of the m-n+1 battery, or may be a pulse signal formed by a rising edge of a low level transition to a high level or a low level transition to a high level.
On the other hand, after the capacitor C5 is fully charged, the current flowing through the capacitor C5 is 0, the driving current passing through the input end of the optocoupler isolator U1 can be limited below mA, the optocoupler isolator U1 is not conductive, and the power consumption of the charge-discharge activation circuit can be further reduced.
It should be noted that, for the charge-discharge activation circuit provided in fig. 1a to 1c, the peripheral control circuit 101, the battery pack 102 and the BMS module 103 shown in fig. 1a to 1c, the charge MOS tube 100d and the discharge MOS tube 100e shown in fig. 1b, and the discharge MOS tube 100f and the charge MOS tube 100g shown in fig. 1c may be optional modules of the charge-discharge activation circuit 100, and the specific circuit structure thereof is not limited, so that the existing circuit structure may be selected to realize the corresponding functions. Of course, the peripheral control circuit 101 may alternatively have the circuit configuration shown in fig. 3.
It should be noted that, the descriptions of "first" and "second" herein are used to distinguish different messages, devices, modules, etc., and do not represent a sequence, and are not limited to the "first" and the "second" being different types.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present invention and is not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are to be included in the scope of the claims of the present invention.
Claims (6)
1. A charge-discharge activation circuit, comprising: a discharge activation circuit, a charge activation circuit, and a gate circuit; the discharge activating circuit is electrically connected with the gating circuit and is electrically connected with the trigger signal output end of the peripheral control circuit; the charging activation circuit is electrically connected with the gating circuit and is electrically connected with a charging anode of the battery pack; and the gating circuit is electrically connected with the BMS module of the battery pack;
wherein the discharge activation circuit includes: a PNP triode circuit and an N-MOS switch circuit;
the emitter of the PNP triode circuit is electrically connected with the trigger signal output end of the peripheral control circuit; the base electrode of the PNP triode circuit is grounded; the collector electrode of the PNP triode circuit is electrically connected with the grid electrode of the N-MOS switching circuit; a capacitor C8 is connected in series between the collector and the emitter of the PNP triode circuit;
the drain electrode of the N-MOS switch circuit is respectively and electrically connected with the gating circuit and the anode of the nth battery of the battery pack; the source electrode of the N-MOS switch circuit is grounded; wherein n is a positive integer, and n is more than or equal to 1 and less than or equal to the total number of the battery pack;
the PNP triode circuit comprises: PNP transistor and diode D3;
the emitter of the PNP triode is electrically connected with the cathode of the diode D3, and the anode of the diode D3 is electrically connected with the trigger signal output end of the peripheral control circuit;
the base electrode series resistor R11 of the PNP triode is connected with the ground, and the series point of the base electrode and the resistor R11 is electrically connected with the trigger signal output end of the peripheral control circuit;
the collector of the PNP triode is connected with two pull-down resistors R12 and R13 in series and then is connected with the ground, and the serial connection point of the two pull-down resistors R12 and R13 is electrically connected with the grid electrode of the N-MOS switching circuit;
the N-MOS switching circuit includes: an N-MOS tube Q3 and a voltage stabilizing tube ZD2;
the voltage stabilizing tube ZD2 is connected between the series connection point of the two pull-down resistors R12 and R13 and the ground in series, the negative electrode of the voltage stabilizing tube ZD2 is connected with the series connection point of the two pull-down resistors R12 and R13, and the positive electrode is grounded;
the drain electrode of the N-MOS tube Q3 is electrically connected with the gating circuit, and is electrically connected with the anode of the nth battery after being connected with a resistor R14 in series;
the source electrode of the N-MOS tube Q3 is grounded; a diode D6 is connected in series between the drain electrode and the source electrode, the anode of the diode D6 is connected with the source electrode, and the cathode is connected with the drain electrode;
the gating circuit includes: P-MOS transistor Q4; the grid electrode of the P-MOS tube Q4 is electrically connected with the drain electrode of the N-MOS switch circuit; the source electrode of the P-MOS tube Q4 is electrically connected with the anode of the nth battery; the drain electrode of the P-MOS tube Q4 is connected with two pull-down resistors R16 and R17 in series and then grounded, and the serial connection point of the two pull-down resistors R16 and R17 is electrically connected with the BMS module;
the charge activation circuit includes: an RC parallel circuit and an optocoupler isolator;
the first end of the RC parallel circuit is electrically connected with the charging anode of the battery pack; the anode of the light emitting diode in the optocoupler isolator is connected with the second end of the RC parallel circuit, the cathode of the light emitting diode is connected with the second end of the RC parallel circuit after being connected with the diode D4 in series, and the cathode of the diode D4 is electrically connected with the second end of the RC parallel circuit; an emitter of the photosensitive PNP triode in the opto-coupler isolator is electrically connected with a drain electrode of the P-MOS tube Q4, and a collector of the photosensitive PNP triode is electrically connected with a source electrode of the P-MOS tube Q4.
2. The charge-discharge activation circuit of claim 1, wherein the discharge activation circuit is configured to output a strobe signal to the strobe circuit under the triggering of a trigger signal from the trigger signal output terminal, so as to output a first activation signal to the BMS module through the strobe circuit to activate the BMS module for discharge management.
3. The charge-discharge activation circuit of claim 2, wherein the gating circuit is configured to operate in a first gating mode according to a gating signal from the discharge activation circuit to communicate the discharge activation circuit with the BMS module.
4. The charge-discharge activation circuit of claim 1, wherein the charge activation circuit is configured to output a strobe signal to the strobe circuit under the triggering of a dc signal provided by an external power source, so as to output a second activation signal to the BMS module through the strobe circuit, so as to activate the BMS module for charge management.
5. The charge-discharge activation circuit of claim 4, wherein the gating circuit is configured to operate in a second gating mode according to a gating signal from the charge activation circuit to communicate the charge activation circuit with the BMS module.
6. The charge-discharge activation circuit of claim 1, wherein the gating circuit further comprises: a filter capacitor C4; one end of the filter capacitor C4 is connected with the serial connection point of the two pull-down resistors R16 and R17, and the other end of the filter capacitor C4 is grounded.
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| CN106564393A (en) * | 2016-07-26 | 2017-04-19 | 华南理工大学 | High-power intelligent quick-charge electric source system for electric automobile and control method |
| CN206471888U (en) * | 2017-01-24 | 2017-09-05 | 临汾市沃特玛电池有限公司 | A kind of discharge and recharge active circuit |
| CN108206556A (en) * | 2016-12-16 | 2018-06-26 | 东莞市德尔能新能源股份有限公司 | BMS charging systems and its charging method |
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| CN203722290U (en) * | 2014-01-08 | 2014-07-16 | 上海长园维安电子线路保护有限公司 | Battery protection module with function automatically enabling the entry of low-power consumption state and wake-up function |
| CN106564393A (en) * | 2016-07-26 | 2017-04-19 | 华南理工大学 | High-power intelligent quick-charge electric source system for electric automobile and control method |
| CN108206556A (en) * | 2016-12-16 | 2018-06-26 | 东莞市德尔能新能源股份有限公司 | BMS charging systems and its charging method |
| CN206471888U (en) * | 2017-01-24 | 2017-09-05 | 临汾市沃特玛电池有限公司 | A kind of discharge and recharge active circuit |
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