CN110858757A - Current control and sampling method, device and computer readable storage medium - Google Patents
Current control and sampling method, device and computer readable storage medium Download PDFInfo
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- CN110858757A CN110858757A CN201810955054.1A CN201810955054A CN110858757A CN 110858757 A CN110858757 A CN 110858757A CN 201810955054 A CN201810955054 A CN 201810955054A CN 110858757 A CN110858757 A CN 110858757A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
- H02P23/14—Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P2205/00—Indexing scheme relating to controlling arrangements characterised by the control loops
- H02P2205/01—Current loop, i.e. comparison of the motor current with a current reference
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
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Abstract
The invention provides a current control and sampling method, a current control and sampling device and a computer readable storage medium. The current control and sampling method comprises the following steps: executing a current loop control program every two PWM periods to control the current, wherein the current loop control program is started to be executed at the starting time of the first PWM period and is finished before the finishing time of the second PWM period; sampling a first direct current bus sampling current and a second direct current bus sampling current in a second PWM period, taking the opposite value of the first direct current bus sampling current as a first phase current, taking the second direct current bus sampling current as a second phase current, and calculating the third phase current according to a reconstruction rule that the sum of the first phase current, the second phase current and the third phase current is zero. By adopting the technical scheme of the invention, the single-resistor blocking beat control is realized, the PWM frequency is improved under the condition of ensuring the normal operation of a current loop control program, and the single-resistor sampling processing method is optimized.
Description
Technical Field
The invention relates to the technical field of permanent magnet motors, in particular to a current control and sampling method, a current control and sampling device and a computer readable storage medium.
Background
Because of the consideration of cost and space, the permanent magnet motor of the automobile electronic water pump controller mostly adopts a single-resistor sampling mode, and additionally adopts a MCU (micro controller Unit) with lower dominant frequency. The conventional control usually adopts a way of one-to-one correspondence between a PWM (Pulse Width Modulation) period and a current loop control, as shown in fig. 1a and 1b, but if the dominant frequency is too low, the problem of overflow of the execution time of the current loop control program may be caused, and the execution time of the current loop control program is greater than the PWM period.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art or the related art.
To this end, an aspect of the present invention is to provide a current control and sampling method.
Another aspect of the present invention is to provide a current control and sampling apparatus.
Yet another aspect of the present invention is directed to a computer-readable storage medium.
In view of the above, according to an aspect of the present invention, a current control and sampling method is provided, including: executing a current loop control program every two PWM periods to control the current, wherein the current loop control program is started to be executed at the starting time of the first PWM period and is finished before the finishing time of the second PWM period; sampling a first direct current bus sampling current and a second direct current bus sampling current in a second PWM period, taking the opposite value of the first direct current bus sampling current as a first phase current, taking the second direct current bus sampling current as a second phase current, and calculating a third phase current according to a reconstruction rule that the sum of the first phase current, the second phase current and the third phase current is zero.
According to the current control and sampling method provided by the invention, the current loop control program is executed once every two PWM periods so as to control the current of the motor, the current loop control program is started to be executed at the starting moment of the first PWM period and is finished to be executed before the ending moment of the second PWM period, namely, the current loop control program is executed once corresponding to two PWM periods, so that the problem of overflow of the execution time of the current loop control program is solved. Furthermore, the first direct current bus sampling current and the second direct current bus sampling current are sampled in the second PWM period, and the third phase current is calculated according to the relation that the sum of the three phase currents is zero, so that the reconstruction of the three phase currents is realized, and the three phase currents are accurately obtained. By adopting the technical scheme of the invention, the single-resistor blocking beat control is realized, the PWM frequency is improved under the condition of ensuring the normal operation of a current loop control program, and the single-resistor sampling processing method is optimized.
The current control and sampling method according to the present invention may further have the following technical features:
in the above technical solution, preferably, the sampling of the first dc bus sampling current and the second dc bus sampling current in the second PWM period specifically includes: calculating a first sampling time and a second sampling time in a second PWM period; sampling a first direct current bus sampling current at a first sampling moment, and sampling a second direct current bus sampling current at a second sampling moment; the first sampling instant is obtained by the following formula: t isAD1trig＝2×TPWM-CompM(k+1)×TPWM/PrdReg-Tmin+TADstable，TAD1trigRepresenting a first sampling instant, TPWMRepresenting one PWM cycle, CompM(k +1) represents the second-period second pulse comparison value, PrdReg represents the peak of the falling sawtooth wave, TminIndicates a preset time period, TADstableRepresenting the sampling stabilization time; the second sampling instant is obtained by the following formula: t isAD2trig＝2×TPWM-CompM(k+1)×TPWM/PrdReg+TADstable，TAD2trigRepresenting the first sampling instant.
In the technical scheme, a first sampling moment and a second sampling moment are calculated, and the first sampling moment and the second sampling moment are both in a second PWM period. Further, sampling the first direct current bus sampling current and the second direct current bus sampling current at the first sampling time and the second sampling time respectively, and controlling the program through a current loopSampling after execution ensures the accuracy of current sampling. T isminAnd representing the preset time length, namely the minimum current sampling time length.
In any of the above technical solutions, preferably, before sampling the first dc bus sampling current and the second dc bus sampling current in the second PWM period, the method further includes: calculating a first period first pulse comparison value, a first period second pulse comparison value and a first period third pulse comparison value in a first PWM period, and a second period first pulse comparison value, a second period second pulse comparison value and a second period third pulse comparison value in a second PWM period, and comparing the first period first pulse comparison value, the first period second pulse comparison value, the first period third pulse comparison value, the second period first pulse comparison value, the second period second pulse comparison value and the second period third pulse comparison value with a falling sawtooth wave respectively to obtain a first pulse, a second pulse and a third pulse in the first PWM period and the second PWM period; calculating a difference value between the first period first pulse comparison value or the second period first pulse comparison value and the first period second pulse comparison value or the second period second pulse comparison value, recording as a first comparison value difference value, calculating a difference value between the first period second pulse comparison value or the second period second pulse comparison value and the first period third pulse comparison value or the second period third pulse comparison value, and recording as a second comparison value difference value; judging whether the first comparison value difference is greater than or equal to a preset threshold value or not and whether the second comparison value difference is greater than or equal to the preset threshold value or not; when the first comparison value difference value is larger than or equal to a preset threshold value and the second comparison value difference value is larger than or equal to the preset threshold value, the step of sampling the first direct current bus sampling current and the second direct current bus sampling current in a second PWM period is carried out; and when the difference value of the first comparison value is smaller than the preset threshold value and/or the difference value of the second comparison value is smaller than the preset threshold value, correcting the first period first pulse comparison value, the first period second pulse comparison value, the first period third pulse comparison value, the second period first pulse comparison value, the second period second pulse comparison value and the second period third pulse comparison value.
In the technical scheme, before sampling the first direct current bus sampling current and the second direct current bus sampling current in the second PWM period, whether PWM pulse phase shifting is needed or not is determined. Specifically, a first period first pulse comparison value, a first period second pulse comparison value and a first period third pulse comparison value in a first PWM period, and a second period first pulse comparison value, a second period second pulse comparison value and a second period third pulse comparison value in a second PWM period are calculated, and each comparison value is compared with a falling sawtooth wave to obtain a first pulse, a second pulse and a third pulse. The waveforms of the first pulse, the second pulse and the third pulse in the first PWM period are the same as those in the second PWM period, the comparison value of the first pulse in the first period is the same as that of the first pulse in the second period, the comparison value of the second pulse in the first period is the same as that of the second pulse in the second period, and the comparison value of the third pulse in the first period is the same as that of the third pulse in the second period. Further, a first comparison value difference and a second comparison value difference are calculated, wherein the first comparison value difference is a difference between a first period first pulse comparison value or a second period first pulse comparison value and a first period second pulse comparison value and a second period second pulse comparison value, and the second comparison value difference is a difference between the first period second pulse comparison value or the second period second pulse comparison value and a first period third pulse comparison value and a second period third pulse comparison value. Further, judging the relationship between the first comparison value difference value, the second comparison value difference value and a preset threshold, and when the first comparison value difference value is greater than or equal to the preset threshold and the second comparison value difference value is greater than or equal to the preset threshold, indicating that the falling edge time of each pulse in the second period has enough time interval, namely the sampling time is enough, directly performing current sampling; when the first comparison value difference is smaller than the preset threshold value and/or the second comparison value difference is smaller than the preset threshold value, it is indicated that the time interval of the falling edge time of each pulse in the second period is too short and smaller than the minimum sampling time, at least one of the first pulse, the second pulse and the third pulse needs to be sampled after phase shifting, and the phase shifting process is a process for correcting the comparison value of each pulse. Therefore, the edge time interval of the first pulse, the second pulse and the third pulse is far, observation is facilitated, and the problem that a non-observation area exists during single-resistor sampling is conveniently and effectively solved.
In any of the above technical solutions, preferably, the correcting the first period first pulse comparison value, the first period second pulse comparison value, the first period third pulse comparison value, the second period first pulse comparison value, the second period second pulse comparison value, and the second period third pulse comparison value specifically includes: when the first comparison difference is smaller than the preset threshold and the second comparison difference is smaller than the preset threshold, let CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k + 1)' denotes the modified second period first pulse comparison value, CompM(k +1) represents the second-period second pulse comparison value, Δ CompminRepresents a preset threshold; compH(k)’＝2×CompH(k)-CompM(k)+ΔCompmin，CompH(k) ' denotes a modified first period first pulse comparison value, CompH(k) Indicating a first pulse comparison value, Comp, of a first periodM(k) A second pulse comparison value representing a first period; compL(k+1)’＝CompM(k+1)+ΔCompmin，CompL(k + 1)' represents the modified second period third pulse comparison value; compL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin，CompL(k) ' denotes a modified first-period third-pulse comparison value, CompL(k) Representing the first period third pulse comparison value.
In the technical scheme, when the first comparison difference value is smaller than the preset threshold value and the second comparison difference value is smaller than the preset threshold value, the Comp is orderedH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompmin，CompL(k+1)’＝CompM(k+1)+ΔCompmin，CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin. Corresponding to the first pulse with a larger duty ratio in the second PWM periodThe duty ratio in one PWM period is correspondingly reduced, the duty ratio of the third pulse in the second PWM period is reduced, and the duty ratio in the first PWM period is correspondingly increased, so that the edge moments of the first pulse, the second pulse and the third pulse are far apart.
In any of the above technical solutions, preferably, the method further includes: when the first comparison difference value is smaller than the preset threshold value and the second comparison difference value is greater than or equal to the preset threshold value, the step S102 is performed; when the second comparison difference is smaller than the preset threshold and the first comparison difference is greater than or equal to the preset threshold, the step S112 is performed; step S102, determining (PrdReg-Comp)M(k) Whether it is less than a preset threshold, PrdReg represents the peak height of the falling sawtooth wave, when (PrdReg-Comp)M(k) When the threshold value is less than the preset threshold value, the step S104 is entered, otherwise, the step S108 is entered; step S104, Comp is processedH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Simultaneously adding (PrdReg-Comp)L(k))，CompH(k +1) denotes the second period first pulse comparison value, CompL(k +1) represents a second-period third pulse comparison value; order CompH(k+1)’＝0，CompH(k)’＝2×[CompH(k)+PrdReg-CompL(k)]Step S106 is entered; step S106, let CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompmin，CompM(k + 1)' denotes the modified second period second pulse comparison value, CompM(k) ' represents the corrected first period second pulse comparison value, and proceeds to step S110; step S108, let CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompminStep S110 is entered; step S110, judging whether the second comparison difference value is smaller than a preset threshold value, if so, entering step S112, otherwise, entering step S120; step S112, determine CompM(k) Whether it is less than the preset threshold value, when CompM(k) If the threshold is less than the preset threshold, the step S114 is entered, otherwise, the step S118 is entered(ii) a Step S114, CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Subtracting Comp at the same timeH(k) Let CompL(k+1)’＝PrdReg，CompL(k)’＝2×[CompL(k)-CompH(k)]-PrdReg, go to step S116; step S116, let CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminStep S120 is entered; step S118, let CompL(k+1)’＝CompM(k+1)+ΔCompmin；CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin(ii) a In step S120, the comparison value correction is completed.
In this embodiment, step S104, Comp is processedH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Simultaneously adding (PrdReg-Comp)L(k) Corresponding to the duty ratio of the first pulse, the second pulse and the third pulse in the first PWM period and the duty ratio of the first pulse, the second pulse and the third pulse in the second PWM period being simultaneously reduced, to make CompH(k+1)’＝0，CompH(k)’＝2×[CompH(k)+PrdReg-CompL(k)]Corresponding to the first pulse becoming 100% of the limit in the second PWM period, the duty cycle becomes correspondingly smaller in the first PWM period. Step S106, let CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompminThe duty ratio of the second pulse in two PWM periods is increased or decreased by the third pulse and Δ CompminThe size of the cells in between. Step S108, let CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompminIn other words, the duty ratio of the first pulse is increased in the second PWM period, and the duty ratio is decreased in the first PWM period. Step S114, CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Subtracting Comp at the same timeH(k) The duty ratio of the first pulse, the second pulse and the third pulse in the first PWM period and the duty ratio of the first pulse, the second pulse and the third pulse in the second PWM period are simultaneously increased to make CompL(k+1)’＝PrdReg，CompL(k)’＝2×[CompL(k)-CompH(k)]-PrdReg, corresponding to the third pulse having a duty cycle which becomes 0% of the limit in the second PWM period, and which should be larger in the first PWM period. Step S116, let CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminThe duty ratio of the second pulse in two PWM periods is increased or decreased by the first pulse and Δ CompminThe size of the cells in between. Step S118, let CompL(k+1)’＝CompM(k+1)+ΔCompmin；CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompminThe duty ratio of the third pulse in the second PWM period is reduced, and the duty ratio in the first PWM period is increased. Thereby allowing sufficient sampling time for current sampling.
It should be noted that the principle of all the pulse duty ratio changes is that the sum of the duty ratios of the changed pulses in two PWM periods is equal to the sum of the duty ratios of the two PWM periods before the change.
In any of the above solutions, preferably, in step S106, let CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompminThen, the method further comprises the following steps: when CompM(k) When' less than zero, let CompM(k)’＝0。
In this solution, CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompminThen, if the second pulse is made smaller in the second PWM period, then it is made larger in the first PWM period, there is aIt may exceed 100% and in this case it is cut off to 100%.
In any of the above solutions, preferably, in step S116, let CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminThen, the method further comprises the following steps: when CompM(k) ' when greater than PrdReg, let CompM(k)’＝PrdReg。
In this solution, CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminThen, if the second pulse becomes larger in the second PWM period, then it becomes smaller in the first PWM period, and may exceed 0%, and then it is turned off to 0%.
In any of the above technical solutions, preferably, the PWM period is counted in a falling sawtooth wave manner.
In the technical scheme, the PWM period counts in a descending sawtooth wave mode so as to ensure that a set of comparison values (if the triangular wave exists, the triangular wave has ascending and descending waves, and two sets of comparison values can appear when the triangular wave is compared with PWM pulse) appear in one PWM period, and the control program processing is simplified.
According to another aspect of the present invention, a current control and sampling apparatus is provided, which includes a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the steps of the current control and sampling method according to any of the above-mentioned technical solutions.
According to the current control and sampling device provided by the invention, when the processor executes the computer program, the steps of the current control and sampling method of any one of the technical schemes are realized, so that the computer equipment has all the beneficial effects of the current control and sampling method of any one of the technical schemes.
According to a further aspect of the present invention, a computer-readable storage medium is proposed, on which a computer program is stored, which computer program, when being executed by a processor, is adapted to carry out the steps of the current control and sampling method according to any of the previous claims.
The computer-readable storage medium provided by the present invention, when being executed by a processor, implements the steps of the current control and sampling method according to any of the above-mentioned technical solutions, and therefore the computer-readable storage medium includes all the advantageous effects of the current control and sampling method according to any of the above-mentioned technical solutions.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1a is a diagram showing the PWM period versus time for a current loop control implementation of the related art;
FIG. 1b is a graph showing the PWM period versus time for a current loop control implementation of the related art;
FIG. 2 shows a flow diagram of a current control and sampling method of one embodiment of the present invention;
FIG. 3 is a graph of PWM cycle time versus current loop control execution sequence for one embodiment of the present invention;
FIG. 4 shows a flow diagram of a current control and sampling method of another embodiment of the present invention;
FIG. 5 shows a single resistive sampling non-observation zone schematic of another embodiment of the present invention;
FIG. 6 is a symbolic-sense diagram illustrating a current control and sampling method according to one embodiment of the present invention;
FIG. 7 illustrates a PWM phase shift diagram for one aspect of an embodiment of the present invention;
FIG. 8 shows a schematic diagram of a current control and sampling apparatus of one embodiment of the present invention.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments of the present invention and features of the embodiments may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
An embodiment of the first aspect of the present invention provides a current control and sampling method, and fig. 2 illustrates a flow diagram of the current control and sampling method according to an embodiment of the present invention. Wherein, the method comprises the following steps:
and 204, sampling the first direct current bus sampling current and the second direct current bus sampling current in a second PWM period, taking the opposite value of the first direct current bus sampling current as a first phase current, taking the second direct current bus sampling current as a second phase current, and calculating a third phase current according to a reconstruction rule that the sum of the first phase current, the second phase current and the third phase current is zero.
According to the current control and sampling method provided by the invention, the current loop control program is executed once every two PWM periods so as to control the current of the motor, the current loop control program is started to be executed at the starting moment of the first PWM period and is finished to be executed before the ending moment of the second PWM period, namely, the current loop control program is executed once corresponding to two PWM periods, so that the problem of overflow of the execution time of the current loop control program is solved. Furthermore, the first direct current bus sampling current and the second direct current bus sampling current are sampled in the second PWM period, and the third phase current is calculated according to the relation that the sum of the three phase currents is zero, so that the reconstruction of the three phase currents is realized, and the three phase currents are accurately obtained. By adopting the technical scheme of the invention, the single-resistor blocking beat control is realized, the PWM frequency is improved under the condition of ensuring the normal operation of a current loop control program, and the single-resistor sampling processing method is optimized.
Preferably, the PWM periods are counted in a falling sawtooth fashion.
In this embodiment, as shown in fig. 3, a current loop control program is executed every two PWM periods to control the current of the motor, and the PWM periods are counted in a falling sawtooth wave manner to ensure that a set of comparison values (if a triangle wave exists, the triangle wave has rising and falling waves, and two sets of comparison values are generated when compared with a PWM pulse) appear in one PWM period, thereby simplifying the processing of the control program.
Fig. 4 shows a flow chart of a current control and sampling method according to another embodiment of the present invention. Wherein, the method comprises the following steps:
In the technical scheme, before sampling the first direct current bus sampling current and the second direct current bus sampling current in the second PWM period, whether PWM pulse phase shifting is needed or not is determined. Specifically, a first period first pulse comparison value, a first period second pulse comparison value and a first period third pulse comparison value in a first PWM period, and a second period first pulse comparison value, a second period second pulse comparison value and a second period third pulse comparison value in a second PWM period are calculated, and each comparison value is compared with a falling sawtooth wave to obtain a first pulse, a second pulse and a third pulse. The waveforms of the first pulse, the second pulse and the third pulse in the first PWM period are the same as those in the second PWM period, the comparison value of the first pulse in the first period is the same as that of the first pulse in the second period, the comparison value of the second pulse in the first period is the same as that of the second pulse in the second period, and the comparison value of the third pulse in the first period is the same as that of the third pulse in the second period. Further, a first comparison value difference and a second comparison value difference are calculated, wherein the first comparison value difference is a difference between a first period first pulse comparison value or a second period first pulse comparison value and a first period second pulse comparison value and a second period second pulse comparison value, and the second comparison value difference is a difference between the first period second pulse comparison value or the second period second pulse comparison value and a first period third pulse comparison value and a second period third pulse comparison value. Further, judging the relationship between the first comparison value difference value, the second comparison value difference value and a preset threshold, and when the first comparison value difference value is greater than or equal to the preset threshold and the second comparison value difference value is greater than or equal to the preset threshold, indicating that the falling edge time of each pulse in the second period has enough time interval, namely the sampling time is enough, directly performing current sampling; when the difference value of the first comparison value is smaller than the preset threshold value and/or the difference value of the second comparison value is smaller than the preset threshold value, it is indicated that the time interval of the falling edge time of each pulse in the second period is too short and smaller than the minimum sampling time, and a non-observation area (a non-observation area 1, a non-observation area 2, a non-observation area 3) shown in fig. 5 occurs, which affects resistance sampling, at least one of the first pulse, the second pulse, and the third pulse needs to be sampled after phase shifting, and the phase shifting process is a process of correcting each pulse comparison value. Therefore, the edge time interval of the first pulse, the second pulse and the third pulse is far, observation is facilitated, and the problem that a non-observation area exists during single-resistor sampling is conveniently and effectively solved.
Preferably, sampling the first dc bus sampling current and the second dc bus sampling current in the second PWM period specifically includes: calculating a first sampling time and a second sampling time in a second PWM period; sampling a first direct current bus sampling current at a first sampling moment, and sampling a second direct current bus sampling current at a second sampling moment; the first sampling instant is obtained by the following formula: t isAD1trig＝2×TPWM-CompM(k+1)×TPWM/PrdReg-Tmin+TADstable，TAD1trigRepresenting a first sampling instant, TPWMRepresenting one PWM cycle, CompM(k +1) represents the second-period second pulse comparison value, PrdReg represents the peak of the falling sawtooth wave, TminIndicates a preset time period, TADstableRepresenting the sampling stabilization time; the second sampling instant is obtained by the following formula: t isAD2trig＝2×TPWM-CompM(k+1)×TPWM/PrdReg+TADstable，TAD2trigRepresenting the first sampling instant.
In this embodiment, a first sampling instant and a second sampling instant are calculated, both within the second PWM period. Furthermore, the first direct current bus sampling current and the second direct current bus sampling current are respectively sampled at the first sampling moment and the second sampling moment, and the accuracy of current sampling is ensured by sampling after the current loop control program is executed. T isminAnd representing the preset time length, namely the minimum current sampling time length.
Fig. 6 shows a symbolic meaning diagram of a current control and sampling method according to an embodiment of the invention. Wherein the content of the first and second substances,
TPWMrepresenting a current PWM period, PWM (k) representing a first PWM period, and PWM (k +1) representing a second PWM period;
PrdReg represents the peak of the falling sawtooth wave;
PulseH(k) the first Pulse (highest phase Pulse) representing the first periodM(k) Second Pulse (intermediate phase Pulse) representing the first periodL(k) Third Pulse (lowest phase Pulse) representing the first periodH(k +1) denotes the first Pulse (highest phase Pulse) of the second cycle, PulseM(k +1) denotes a second Pulse (intermediate phase Pulse) of the second cycle, PulseL(k +1) represents the third pulse (lowest phase pulse) of the second cycle;
CompH(k) indicating a first pulse comparison value, Comp, of a first periodM(k) Indicating the comparison value of the second pulse, Comp, of the first periodL(k) Indicating the third pulse comparison value, Comp, of the first periodH(k +1) denotes the second period first pulse comparison value, CompM(k +1) denotes the second period second pulse comparison value, CompL(k +1) represents a second-period third pulse comparison value;
ΔCompHM(k) representing a first comparison difference, Δ Comp, of a first periodML(k) Representing the difference, Δ Comp, of the second comparison values of the first periodHM(k +1) represents the first comparison value difference, Δ Comp, of the second periodML(k +1) represents the second period second comparison value difference, Δ CompminRepresenting a preset threshold, wherein before phase shifting, a first period first comparison value difference value and a second period first comparison value difference value are used as first comparison value difference values, and a first period second comparison value difference value and a second period second comparison value difference value are used as second comparison value difference values;
Tminindicates a preset time period, TADstableRepresenting the sampling stabilization time;
TAD1tringrepresenting a first sampling instant, TAD1tring＝＝2×TPWM-CompM(k+1)×TPWM/PrdReg-Tmin+TADstable；
TAD2tringRepresenting the second sampling instant, TAD2tring＝2×TPWM-CompM(k+1)×TPWM/PrdReg+TADstableTherein CompM(k+1)×TPWMand/PrdReg, as shown in FIG. 6.
Preferably, in step 410, the first period first pulse comparison value, the first period second pulse comparison value, the first period third pulse comparison value, the second period first pulse comparison value, the second period second pulse comparison value, and the second period third pulse comparison value are corrected, which specifically includes the following conditions (1), (2), and (3):
(1) when the first comparison difference is smaller than the preset threshold and the second comparison difference is smaller than the preset threshold, let CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k + 1)' denotes the modified second period first pulse comparison value, CompM(k +1) represents the second pulse of the second cycleComparative value, Δ CompminRepresents a preset threshold; compH(k)’＝2×CompH(k)-CompM(k)+ΔCompmin，CompH(k) ' denotes a modified first period first pulse comparison value, CompH(k) Indicating a first pulse comparison value, Comp, of a first periodM(k) A second pulse comparison value representing a first period; compL(k+1)’＝CompM(k+1)+ΔCompmin，CompL(k + 1)' represents the modified second period third pulse comparison value; compL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin，CompL(k) ' denotes a modified first-period third-pulse comparison value, CompL(k) A third pulse comparison value representing a first period;
(2) when the first comparison difference value is smaller than the preset threshold value and the second comparison difference value is greater than or equal to the preset threshold value, the step S502 is entered;
(3) when the second comparison difference is smaller than the preset threshold and the first comparison difference is greater than or equal to the preset threshold, the step S512 is performed;
step S502, judge (PrdReg-Comp)M(k) Whether it is less than a preset threshold, PrdReg represents the peak height of the falling sawtooth wave, when (PrdReg-Comp)M(k) When the threshold value is less than the preset threshold value, the step S504 is entered, otherwise, the step S508 is entered;
step S504, CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Simultaneously adding (PrdReg-Comp)L(k))，CompH(k +1) denotes the second period first pulse comparison value, CompL(k +1) represents a second-period third pulse comparison value; order CompH(k+1)’＝0，CompH(k)’＝2×[CompH(k)+PrdReg-CompL(k)]Step S506 is entered;
step S506, let CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompminIf CompM(k) ' less than zero, let CompM(k)’＝0，CompM(k + 1)' denotes the modified second period second pulse comparison value, CompM(k) ' represents the corrected first period second pulse comparison value, and proceeds to step S510;
step S508, let CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompminStep S510 is entered;
step S510, judging whether the second comparison difference value is smaller than a preset threshold value, if so, entering step S512, otherwise, entering step S520;
step S512, determine CompM(k) Whether it is less than the preset threshold value, when CompM(k) If the value is smaller than the preset threshold value, the step S514 is executed, otherwise, the step S518 is executed;
step S514, CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Subtracting Comp at the same timeH(k) Let CompL(k+1)’＝PrdReg，CompL(k)’＝2×[CompL(k)-CompH(k)]-PrdReg, go to step S516;
step S516, let CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminIf CompM(k) ' greater than PrdReg, let CompM(k) ' PrdReg, proceed to step S520;
step S518, let CompL(k+1)’＝CompM(k+1)+ΔCompmin，CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin；
In step S520, the comparison value correction is completed.
In this embodiment, when the first comparison difference is smaller than the preset threshold and the second comparison difference is smaller than the preset threshold, let CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompmin，CompL(k+1)’＝CompM(k+1)+ΔCompmin，CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin. The duty ratio of the first pulse in the second PWM period is increased, the duty ratio of the first pulse in the first PWM period is correspondingly decreased, the duty ratio of the third pulse in the second PWM period is decreased, and the duty ratio of the third pulse in the first PWM period is correspondingly increased, so that the edge time intervals of the first pulse, the second pulse and the third pulse are far.
Step S504, CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Simultaneously adding (PrdReg-Comp)L(k) Corresponding to the duty ratio of the first pulse, the second pulse and the third pulse in the first PWM period and the duty ratio of the first pulse, the second pulse and the third pulse in the second PWM period being simultaneously reduced, to make CompH(k+1)’＝0，CompH(k)’＝2×[CompH(k)+PrdReg-CompL(k)]Corresponding to the first pulse becoming 100% of the limit in the second PWM period, the duty cycle becomes correspondingly smaller in the first PWM period. Step S506, let CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompminThe duty ratio of the second pulse in two PWM periods is increased or decreased by the third pulse and Δ CompminThe size of the cells in between. Step S508, let CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompminIn other words, the duty ratio of the first pulse is increased in the second PWM period, and the duty ratio is decreased in the first PWM period. Step S514, CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Subtracting Comp at the same timeH(k) The duty ratio of the first pulse, the second pulse and the third pulse in the first PWM period and the duty ratio of the first pulse, the second pulse and the third pulse in the second PWM period are simultaneously increased to make CompL(k+1)’＝PrdReg，CompL(k)’＝2×[CompL(k)-CompH(k)]-PrdReg, corresponding to the third pulse having a duty cycle which becomes 0% of the limit in the second PWM period, and which should be larger in the first PWM period. Step S516, let CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminThe duty ratio of the second pulse in two PWM periods is increased or decreased by the first pulse and Δ CompminThe size of the cells in between. Step S518, let CompL(k+1)’＝CompM(k+1)+ΔCompmin，CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompminIn the second PWM period, the duty ratio of the third pulse is decreased, and in the first PWM period, the duty ratio is increased, and as shown in fig. 7, the waveform is changed from (a) to (b). Thereby allowing sufficient sampling time for current sampling.
It should be noted that the principle of all the pulse duty ratio changes is that the sum of the duty ratios of the changed pulses in two PWM periods is equal to the sum of the duty ratios of the two PWM periods before the change.
In this embodiment, in step S506, CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompminThen, if the second pulse is smaller in the second PWM period, then it is larger in the first PWM period, which may exceed 100%, and then it is turned off to 100%. In step S516, CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminThen, if the second pulse becomes larger in the second PWM period, then it becomes smaller in the first PWM period, and may exceed 0%, and then it is turned off to 0%.
In a specific embodiment of the present application, a method for controlling a single electric blocking flap of an automotive electronic water pump is provided, which includes the following steps:
1. the current loop control program is executed once every two PWM periods, and the current loop control program synchronously starts to be executed at the starting moment of the first PWM period;
counting PWM in a descending sawtooth wave mode;
3. if the pulse edge interval of the PWM is too short and is less than the necessary sampling time, carrying out PWM phase-shifting treatment and then carrying out sampling;
4. and the three-phase current is sampled in the 2 nd PWM period and is obtained by reconstructing direct current on a bus single resistor.
The phase shift rule in the step 3 is carried out according to the following steps:
(1) determination of Δ CompHM、ΔCompMLAnd Δ CompminIf Δ CompHM<CompminAnd Δ CompML<CompminThen Comp will beH(k +1) Down, CompH(k) Rising, CompL(k +1) rise, CompL(k) Descending, then finishing phase shifting, and otherwise, continuing the step (2);
(2) determination of Δ CompHMAnd Δ CompminIf Δ CompHM<ΔCompminThen, the judgment is continued (PrdReg-Comp)M) And Δ CompminOtherwise, continuing the step (3); if (PrdReg-Comp)M)<ΔCompminShifting the comparison values in PWM (k +1) three phases simultaneously and then shifting each phase, otherwise, CompH(k +1) Down, CompH(k) Rising and then finishing phase shifting;
(3) determination of Δ CompMLAnd Δ CompminIf Δ CompML<ΔCompminIf yes, continue to judge CompMAnd Δ CompminIf Comp, otherwise the phase shift endsM<ΔCompminIf the comparison value in PWM (k +1) is shifted for three phases at the same time, then each phase is shifted, otherwise Comp is calculatedL(k +1) rise, CompL(k) Decreases and then the phase shift ends.
Wherein, Comp of PWM (k +1) in step (1)H(k +1) Down, CompH(k) The method comprises the following steps:
1) will CompH(k +1) reduction to Δ CompHM＝Compmin；
2) Will CompH(k) Raise, guarantee CompH(k)+CompH(k +1) is the same as before the move.
Comp of PWM (k +1) in step (1)L(k +1) rise, CompH(k) And (3) descending, comprising the following steps:
1) will CompL(k +1) Up to Δ CompML＝ΔCompmin；
2) Will CompL(k) Reduce and guarantee CompL(k)+CompL(k +1) is the same as before the move.
In the step (2), the comparison value in the PWM (k +1) is firstly translated by three phases at the same time and then each phase moves, and the method comprises the following steps:
1) will CompH(k+1)、CompM(k+1)、CompL(k +1) is simultaneously added with (PrdReg-Comp)L)；
2) Will CompH(k +1) to 0 and CompH(k) Raise, guarantee CompH(k)+CompH(k +1) is the same as before the move;
3) will CompM(k +1) movement is Δ CompminSimultaneous moving of CompM(k) Guarantee CompM(k+1)+CompM(k) As before the move.
In the step (3), the comparison value in the PWM (k +1) is firstly translated by three phases at the same time and then each phase moves, and the method is characterized by comprising the following steps:
1) will CompH(k+1)、CompM(k+1)、CompL(k +1) simultaneous subtraction of CompL(k+1)；
2) Will CompL(k +1) rises to PrdReg, CompL(k) Decrease, guarantee CompL(k+1)+CompL(k) Same as before the move;
3) will CompM(k) The shift is (PrdReg- Δ Comp)min) Simultaneous moving of CompM(k) Guarantee CompM(k+1)+CompM(k) As before the move.
Wherein, the sampling time in step 4 is arranged according to the following rules:
TAD1trig：2×TPWM-CompM×TPWM/PrdReg-Tmin+TADstable
TAD2trig：2×TPWM-CompM×TPWM/PrdReg+TADstable。
in another embodiment of the present application, a method for controlling a single electric blocking flap of an automotive electronic water pump is provided, which includes the following steps:
1. the current loop control routine is executed once every two PWM periods and is started synchronously at the start of the first PWM period, as shown in fig. 3.
The PWM count is in a falling sawtooth fashion, as shown in fig. 3.
3. The three-phase current is sampled only in a PWM (k +1) (second PWM period) period and is obtained by reconstructing direct current on a bus single resistor, and the sampling time is arranged according to the following rule:
TAD1trig：2×TPWM-CompM(k+1)×TPWM/PrdReg-Tmin+TADstable
TAD2trig：2×TPWM-CompM(k+1)×TPWM/PrdReg+TADstable。
4. if the pulse right edge interval of PWM (k +1) is enough, it is satisfied
ΔCompHM>＝ΔCompminAnd Δ CompML>＝ΔCompmin
Then the original value of the comparison value is maintained:
CompH(k)＝CompH(k+1)；
CompM(k)＝CompM(k+1)；
CompL(k)＝CompL(k+1)。
5. if the interval of the pulse right side edge of the PWM (k +1) is too short and is less than the necessary sampling time (the sampling time is insufficient), sampling is carried out after PWM phase-shifting processing is carried out, and the steps are as follows:
s1: determination of Δ CompHM、ΔCompMLAnd Δ CompminIf Δ CompHM<ΔCompminAnd Δ CompML<ΔCompminThen, the following processing is performed:
CompH(k+1)’＝CompM(k+1)-ΔCompmin；
CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompmin；
CompL(k+1)’＝CompM(k+1)+ΔCompmin；
CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin；
otherwise, continuing to step S2;
s2: determination of Δ CompHMAnd Δ CompminIf Δ CompHM<ΔCompminAdvancing to S3, otherwise advancing to step S8;
s3: judgment (PrdReg-Comp)M) And Δ CompminSize of between, if (PrdReg-Comp)M)<ΔCompminStep S4 is entered, otherwise step S7 is entered;
s4: will CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Simultaneously adding (PrdReg-Comp)L) Proceeding to step S5;
S5：CompH(k+1)’＝0，CompH(k)’＝2×[CompH(k)+PrdReg-CompL(k)]proceeding to step S6;
S6：CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompmin(ii) a If CompM(k)’<0, then CompM(k) ' -0; proceeding to step S8;
S7：CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompminproceeding to step S8;
s8: judgment ofΔCompMLAnd Δ CompminIf Δ CompML<ΔCompminAdvancing to S9, otherwise advancing to step S14;
s9: judgment CompMAnd Δ CompminIf Comp, ofM<ΔCompminStep S10 is entered, otherwise step S13 is entered;
s10: will CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Subtracting Comp at the same timeH(k) Proceeding to step S11;
S11：CompL(k+1)’＝PrdReg，CompL(k)’＝2×[CompL(k)-CompH(k)]-PrdReg, go to step S12;
S12：CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompmin(ii) a If CompM(k)’>PrdReg, CompM(k) ' PrdReg, proceed to step S14;
S13：CompL(k+1)’＝CompM(k+1)+ΔCompmin，CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompminproceeding to step S14, the waveform variation diagram of this step is shown in fig. 7;
s14: the phase shift processing is ended.
All the above symbols have meanings referring to fig. 6, and the upper right-hand band' indicates values after the phase shift processing.
In a second aspect of the present invention, a current control and sampling device is provided, and fig. 8 shows a schematic diagram of a current control and sampling device 80 according to an embodiment of the present invention. Wherein the device 80 comprises:
a memory 802, a processor 804 and a computer program stored in the memory 802 and operable on the processor 804, wherein the processor 804 implements the steps of the current control and sampling method according to any of the above-mentioned embodiments when executing the computer program.
In the current control and sampling device 80 provided by the present invention, when the processor 804 executes the computer program, the steps of the current control and sampling method according to any of the above technical solutions are implemented, so that the computer apparatus includes all the beneficial effects of the current control and sampling method according to any of the above technical solutions.
In an embodiment of the third aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and the computer program, when being executed by a processor, implements the steps of the current control and sampling method according to any one of the above technical solutions.
The computer-readable storage medium provided by the present invention, when being executed by a processor, implements the steps of the current control and sampling method according to any of the above-mentioned technical solutions, and therefore the computer-readable storage medium includes all the advantageous effects of the current control and sampling method according to any of the above-mentioned technical solutions.
In the description herein, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance unless explicitly stated or limited otherwise; the terms "connected," "mounted," "secured," and the like are to be construed broadly and include, for example, fixed connections, removable connections, or integral connections; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the description herein, the description of the terms "one embodiment," "some embodiments," "specific embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A current control and sampling method, comprising:
executing a current loop control program every two PWM periods to control current, wherein the current loop control program is started at the starting time of the first PWM period and is finished before the finishing time of the second PWM period;
sampling a first direct current bus sampling current and a second direct current bus sampling current in the second PWM period, taking the opposite value of the first direct current bus sampling current as a first phase current, taking the second direct current bus sampling current as a second phase current, and calculating the third phase current according to a reconstruction rule that the sum of the first phase current, the second phase current and the third phase current is zero.
2. The current control and sampling method according to claim 1, wherein sampling the first dc bus sampled current and the second dc bus sampled current in the second PWM period specifically comprises:
calculating a first sampling time and a second sampling time in the second PWM period;
starting to sample the first direct current bus sampling current at the first sampling moment, and starting to sample the second direct current bus sampling current at the second sampling moment;
the first sampling instant is obtained by the following formula:
TAD1trig＝2×TPWM-CompM(k+1)×TPWM/PrdReg-Tmin+TADstable，TAD1trigrepresenting said first sampling instant, TPWMRepresenting one said PWM period, CompM(k +1) represents the second-period second pulse comparison value, PrdReg denotes the peak of the falling sawtooth wave, TminIndicates a preset time period, TADstableRepresenting the sampling stabilization time;
the second sampling instant is obtained by the following formula:
TAD2trig＝2×TPWM-CompM(k+1)×TPWM/PrdReg+TADstable，TAD2trigrepresenting the first sampling instant.
3. The current control and sampling method according to claim 1 or 2, wherein before sampling the first dc bus sample current and the second dc bus sample current in the second PWM period, further comprising:
calculating a first period first pulse comparison value, a first period second pulse comparison value and a first period third pulse comparison value in the first PWM period, and a second period first pulse comparison value, a second period second pulse comparison value and a second period third pulse comparison value in the second PWM period, and comparing the first period first pulse comparison value, the first period second pulse comparison value, the first period third pulse comparison value, the second period first pulse comparison value, the second period second pulse comparison value and the second period third pulse comparison value with a falling sawtooth wave respectively to obtain a first pulse, a second pulse and a third pulse in the first PWM period and the second PWM period;
calculating a difference value between the first period first pulse comparison value or the second period first pulse comparison value and the first period second pulse comparison value or the second period second pulse comparison value, recording as a first comparison value difference value, calculating a difference value between the first period second pulse comparison value or the second period second pulse comparison value and the first period third pulse comparison value or the second period third pulse comparison value, and recording as a second comparison value difference value;
judging whether the first comparison value difference value is greater than or equal to a preset threshold value or not and whether the second comparison value difference value is greater than or equal to the preset threshold value or not;
when the first comparison value difference value is larger than or equal to the preset threshold value and the second comparison value difference value is larger than or equal to the preset threshold value, the step of sampling a first direct current bus sampling current and a second direct current bus sampling current in the second PWM period is carried out;
and when the first comparison value difference is smaller than the preset threshold value and/or the second comparison value difference is smaller than the preset threshold value, correcting the first period first pulse comparison value, the first period second pulse comparison value, the first period third pulse comparison value, the second period first pulse comparison value, the second period second pulse comparison value and the second period third pulse comparison value.
4. The method of claim 3, wherein the modifying the first periodic first pulse comparison value, the first periodic second pulse comparison value, the first periodic third pulse comparison value, the second periodic first pulse comparison value, the second periodic second pulse comparison value, and the second periodic third pulse comparison value comprises:
when the first comparison difference value is smaller than the preset threshold value and the second comparison difference value is smaller than the preset threshold value, ordering
CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k + 1)' denotes the modified second period first pulse comparison value, CompM(k +1) represents the second period second pulse comparison value, Δ CompminRepresenting the preset threshold;
CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompmin，CompH(k) ' denotes a modified first period first pulse comparison value, CompH(k) Representing said first period first pulse comparison value, CompM(k) A second pulse comparison value representing the first period;
CompL(k+1)’＝CompM(k+1)+ΔCompmin，CompL(k+1) ' represents a modified second period third pulse comparison value;
CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin，CompL(k) ' denotes a modified first-period third-pulse comparison value, CompL(k) Representing the first period third pulse comparison value.
5. The current control and sampling method of claim 4, further comprising:
when the first comparison difference value is smaller than the preset threshold value and the second comparison difference value is greater than or equal to the preset threshold value, the method goes to step S102; when the second comparison difference value is smaller than the preset threshold value and the first comparison difference value is greater than or equal to the preset threshold value, the method goes to step S112;
step S102, determining (PrdReg-Comp)M(k) Whether it is less than the preset threshold, PrdReg represents the peak height of the falling sawtooth wave, when (PrdReg-Comp)M(k) When the threshold value is less than the preset threshold value, the step S104 is entered, otherwise, the step S108 is entered;
step S104, Comp is processedH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Simultaneously adding (PrdReg-Comp)L(k))，CompH(k +1) represents the second period first pulse comparison value, CompL(k +1) represents the second period third pulse comparison value; order CompH(k+1)’＝0，CompH(k)’＝2×[CompH(k)+PrdReg-CompL(k)]Step S106 is entered;
step S106, let CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompmin，CompM(k + 1)' denotes the modified second period second pulse comparison value, CompM(k) ' represents the corrected first period second pulse comparison value, and proceeds to step S110;
step S108, let CompH(k+1)’＝CompM(k+1)-ΔCompmin，CompH(k)’＝2×CompH(k)-CompM(k)+ΔCompminStep S110 is entered;
step S110, determining whether the second comparison difference is smaller than the preset threshold, and if the second comparison difference is smaller than the preset threshold, entering step S112, otherwise, entering step S120;
step S112, determine CompM(k) Whether it is less than the preset threshold value, when CompM(k) If the value is smaller than the preset threshold value, the step S114 is executed, otherwise, the step S118 is executed;
step S114, CompH(k+1)、CompM(k+1)、CompL(k+1)、CompH(k)、CompM(k)、CompL(k) Subtracting Comp at the same timeH(k) Let CompL(k+1)’＝PrdReg，CompL(k)’＝2×[CompL(k)-CompH(k)]-PrdReg, go to step S116;
step S116, let CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminStep S120 is entered;
step S118, let CompL(k+1)’＝CompM(k+1)+ΔCompmin；CompL(k)’＝2×CompL(k)-CompM(k)-ΔCompmin；
In step S120, the comparison value correction is completed.
6. The current control and sampling method of claim 5, wherein in step S106, let CompM(k+1)’＝ΔCompmin，CompM(k)’＝2×[CompM(k)+PrdReg-CompL(k)]-ΔCompminThen, the method further comprises the following steps:
when CompM(k) When' less than zero, let CompM(k)’＝0。
7. The current control and sampling method of claim 5, wherein in step S116, let CompM(k+1)’＝(PrdReg-ΔCompmin)，CompM(k)’＝2×[CompM(k)-CompH(k)]-PrdReg+ΔCompminThen, the method further comprises the following steps:
when CompM(k) ' when greater than PrdReg, let CompM(k)’＝PrdReg。
8. Current control and sampling method according to claim 1 or 2,
and the PWM period is counted in a descending sawtooth wave mode.
9. A current control and sampling device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the current control and sampling method according to any one of claims 1 to 8 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the current control and sampling method according to any one of claims 1 to 8.
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