CN110855864B - CMOS imaging system based on staggered splicing application - Google Patents

CMOS imaging system based on staggered splicing application Download PDF

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CN110855864B
CN110855864B CN201911126411.4A CN201911126411A CN110855864B CN 110855864 B CN110855864 B CN 110855864B CN 201911126411 A CN201911126411 A CN 201911126411A CN 110855864 B CN110855864 B CN 110855864B
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pin
detector
cmos
imaging
pins
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CN110855864A (en
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余达
刘金国
韩诚山
薛旭成
姜肖楠
张艳鹏
许亮
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/52—Elements optimising image sensor operation, e.g. for electromagnetic interference [EMI] protection or temperature control by heat transfer or cooling elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

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  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A CMOS imaging system based on staggered splicing application relates to the technical field of CMOS imaging, and solves the problems that in the existing imaging with large width, the length direction of a focal plane circuit board is limited due to the fact that the detector is spliced, and a filter capacitor is not arranged in the middle of the detector, so that the filter capacitor is too far away from a pin; each imaging group comprises a 422 communication control module, a time sequence driving control module, a data integration and sending module, a data transmission interface and an imaging focal plane group; the imaging group comprises a data transmission interface module, an imaging focal plane module, a data integration and sending module, a time sequence driving module and a 422 communication control module; the imaging system ensures that the large-format CMOS imaging is stable and reliable; the occupied space of the imaging circuit board is reduced, and the filtering effect is improved, so that the imaging performance is improved. The effective heat dissipation area of the detector is increased, and the temperature change is reduced, so that the stability of imaging parameters such as dark current and the like is improved.

Description

CMOS imaging system based on staggered splicing application
Technical Field
The invention relates to the technical field of CMOS imaging, in particular to a CMOS imaging system for staggered splicing application of aerospace application.
Background
In large-width imaging applications, because the resolution of a single-chip detector is limited, the width is increased by adopting a staggered splicing mode, and two rows of detectors are connected end to end. For detectors with low resolution, in order to avoid image splicing leaks of each detector in the process of side-sway imaging, detectors in the upper row and the lower row are generally required to be overlapped by a certain number of pixels, so that the length direction of a focal plane circuit board is limited, and the length of the focal plane circuit board is close to or slightly longer than that of the detectors. For the application of the CMOS detector, as a plurality of functions are integrated in a single chip, if no filter capacitor is arranged in the middle of the detector, the problem that the filter capacitor is too far away from a pin exists for power supply and bias pins in the middle of the front side and the rear side of the detector.
Disclosure of Invention
The invention provides a CMOS imaging system based on staggered splicing application, aiming at solving the problems that in the existing imaging with large width, the length direction of a focal plane circuit board is limited due to the fact that the detector is spliced, and the filter capacitor is too far away from a pin due to the fact that the filter capacitor is not arranged in the middle of the detector.
The CMOS imaging system based on the staggered splicing application comprises a camera controller and n imaging groups; each imaging group comprises a 422 communication control module, a time sequence driving control module, a data integration and sending module, a data transmission interface module and an imaging focal plane module; the 422 communication control module receives the command sent by the camera controller and returns corresponding information; the time sequence driving control module generates a time sequence and a driving signal which meet the voltage and current requirements; the data integration and transmission module conditions the multi-channel serial data and outputs data meeting a data transmission interface protocol; the data transmission interface module outputs a signal specified by a data transmission interface protocol; the imaging focal plane module is used for performing photoelectric conversion and simultaneously generating voltage and bias signals required by the detector;
the ground coverage width SW of the CMOS imaging system and the effective pixel number n of the single-chip CMOS detectorvalid_pixThe relationship of (1) is:
SW＝[nvalid_pix×nchip-noverlap_pix×(nchip-1)]×GSD
in the formula, nchipIs the total number of CMOS detectors, noverlap_pixIs the number of inter-chip overlapping pixels, n, of a CMOS detectorvalid_pixThe number of effective pixels of the single-chip CMOS detector is shown, and the GSD is the resolution of the ground pixels;
length f of focal plane of CMOS detectorcontrol＝2(nvalid_pix-noverlap_pix)×apix-lboard_gap；
In the formula, apixIs the pixel size of a CMOS detectorboard_gapIs the gap between the focal planes of the CMOS detector.
The invention has the beneficial effects that: the CMOS imaging system based on staggered splicing application ensures that the CMOS imaging of a large breadth is stable and reliable; the concrete advantages are that:
1. the occupied space of the imaging circuit board is reduced, and the filtering effect is improved, so that the imaging performance is improved.
2. The effective heat dissipation area of the detector is increased, and the temperature change is reduced, so that the stability of imaging parameters such as dark current and the like is improved.
Drawings
FIG. 1 is a block diagram of a CMOS imaging system based on staggered tiling according to the present invention;
FIG. 2 is a schematic diagram of the distribution of a CMOS detector for staggered tiling application in a CMOS imaging system based on staggered tiling application according to the present invention;
FIG. 3 is a schematic spectrum distribution diagram of a CMOS detector in a CMOS imaging system based on staggered tiling application according to the present invention;
FIG. 4 is a schematic diagram of the pin distribution of a CMOS detector in a CMOS imaging system based on staggered tiling application according to the present invention;
FIG. 5 is a schematic diagram of a CMOS detector pin distribution structure in a CMOS imaging system based on staggered tiling application according to the present invention;
fig. 6 is a schematic diagram of a package of a CMOS detector in a CMOS imaging system based on staggered tiling according to the present invention.
Detailed Description
Detailed description of the preferred embodimentthe present embodiment is described with reference to fig. 1 to 6, a CMOS imaging system based on staggered tiling application,
the imaging synchronous control system of the multi-channel CMOS comprises a camera controller and n imaging groups; each imaging group comprises a 422 communication control module, a time sequence driving control module, a data integration and sending module, a data transmission interface module and an imaging focal plane module. The 422 communication control module receives a 422 command sent by the camera controller and returns corresponding information; the time sequence driving control module generates a time sequence and a driving signal which meet the voltage and current requirements; the data integration and transmission module conditions the multi-channel serial data and outputs data meeting a data transmission interface protocol; the data transmission interface module outputs a signal specified by a data transmission interface protocol; the imaging focal plane module mainly performs photoelectric conversion and simultaneously generates voltage and bias signals required by the detector. Fig. 2 shows a CMOS detector layout for staggered tiling applications with the highest resolution p-spectrum relatively close together.
The ground coverage width SW of the imaging system and the effective pixel number n of the single-chip CMOS detectorvalid_pixThe relationship is:
SW＝[nvalid_pix×nchip-noverlap_pix×(nchip-1)]×GSD
in the formula nchipIs the total number of CMOS detectors, noverlap_pixIs the number of inter-chip overlapping pixels, n, of a CMOS detectorvalid_pixThe effective pixel number of the single-chip CMOS detector, and the GSD is the ground pixel resolution.
Length f of the focal plane of the CMOS detectorcontrol＝2(nvalid_pix-noverlap_pix)×apix-lboard_gapIn the formula apixIs the pixel size of a CMOS detectorboard_gapThe gap between the focal planes of the CMOS detector is required to be not less than 1 mm.
Referring to fig. 3, the present embodiment is described, and the spectral distribution of the CMOS detector is as follows: the panchromatic band (p-spectrum) with the smaller pixel size is on one side of the detector, not in the middle; the multispectral spectral segment (b-spectrum) is in the rest of the CMOS detector.
In the present embodiment, the pins of the CMOS detector are distributed in the following manner, with reference to fig. 4 and 5: on the pin of detector was arranged, the centre was not placed the pin, and the benefit of pin arranging like this lies in: a region without pins in the middle of the detector for placing a heat-conducting fin on the circuit boardThe corresponding position is used for placing a filter capacitor of a power supply. A four-layer spatial three-dimensional structure is formed in the middle pin-free distribution area of the detector: the first layer is a detector, and the second layer is a radiating fin tightly attached to the detector; the third layer is a filter capacitor tightly adhered to the circuit board and welded, and the fourth layer is the circuit board. The width l of the region where the pins of the heat-conducting sheet are not distributed is requiredblank_pinNot less than 5mm, i.e./blank p_inNot less than 5 mm; the power supply and bias pins of the detector are placed at the upper and lower ends of the detector, but not at the left and right sides.
The present embodiment is described with reference to fig. 6, and the package form of the CMOS detector includes a pin distribution region, a wafer and various capacitors for filtering, and the wafer is connected to the capacitors and pins of the pin distribution region through connection lines. All the capacitance values are less than 4.7uF bias filter capacitance, a single ceramic chip capacitance is adopted and placed in the package of the detector, and the pin is not led out. The power supplies with the same function of b spectrum must be combined into 1, and top and bottom cannot be distributed on the upper side, the lower side or the left side and the right side of the detector respectively; the same number of pins of the analog power supply, the digital power supply, the analog-digital power supply and the ground is combined, the number of the lead-out pins is not more than 2, a ceramic chip capacitor with the capacitance value of 0.01uF to 0.1uF is added between each power supply and the ground pin on the wafer, and a ceramic chip capacitor with the capacitance value of 1 to 4.7uF is added on each power supply.
In this embodiment, the number of pins n of the CMOS detectorchip_pinRepresented by the formula:
nchip_pin＝ngnd_pin+npower_pin+nbias_pin+ndata_out_pin+ncontrol_pin+ncharge_transfer_pin+nspi_test_clock_pin
in the formula, ngnd_pinThe number of the ground pins of the detector is required to be not more than 2 respectively in an analog ground, a digital ground, an analog-to-digital conversion ground and a pixel ground; n ispower_pinThe number of pins of the power supply of the detector is required to be not more than 2 for the same analog power supply, digital power supply and analog-digital power supply; n isbias_pinThe number of the offset pins of the detector is that the pin with the capacity larger than 4.7uF is led out and the pin with the capacity smaller than 4.7uFNot leading out, setting the number of pins to be 0; i.e. nbias p_inThe value of (d) is equal to the number of pins with the bias capacitance larger than 4.7 uF; n isdata_out_pinNumber of pins, n, for data output by the detectorcontrol_pinControlling the number of pins, n, for the input of the detectorcharge_transfer_pinNumber of input charge transfer pins, n, for the detectorspi_test_clock_pinThe number of the pins is the spi interface, the input clock and the test pin number of the detector.
In this embodiment, the imaging focal plane group is a CMOS image sensor of long-photostudio core corporation; the data transmission interface adopts TLK2711 of TI company; the 422 communication control module, the time sequence driving control module and the data integration and transmission module adopt Virtex 5FPGA of Xilinx company.

Claims (4)

1. The CMOS imaging system based on the staggered splicing application comprises a camera controller and n imaging groups; each imaging group comprises a 422 communication control module, a time sequence driving control module, a data integration and sending module, a data transmission interface module and an imaging focal plane module; the 422 communication control module receives a command sent by the camera controller and returns corresponding information; the time sequence driving control module generates a time sequence driving signal meeting the voltage and current requirements; the data integration and transmission module processes the multi-channel serial data and outputs data meeting a data transmission interface protocol; the data transmission interface module outputs a signal specified by a data transmission interface protocol; the imaging focal plane module is used for performing photoelectric conversion and simultaneously generating voltage and bias signals required by a CMOS detector of the imaging focal plane module; the method is characterized in that:
the ground coverage width SW of the CMOS imaging system and the effective pixel number n of the single-chip CMOS detectorvalid_pixThe relationship of (1) is:
SW＝[nvalid_pix×nchip-noverlap_pix×(nchip-1)]×GSD
in the formula, nchipIs the total number of CMOS detectors, noverlap_pixIs the number of inter-chip overlapping pixels, n, of a CMOS detectorvalid_pixThe number of effective pixels of the single-chip CMOS detector is shown, and the GSD is the resolution of the ground pixels;
length f of focal plane of CMOS detectorcontrol＝2(nvalid_pix-noverlap_pix)×apix-lboard_gap；
In the formula, apixIs the pixel size of a CMOS detectorboard_gapIs the gap between the focal planes of the CMOS detector;
the CMOS detector has the following pin distribution modes: on the pin arrangement of the CMOS detector, a heat conducting fin is arranged in a region without a pin in the middle of the CMOS detector, and a filter capacitor of a power supply is arranged at a corresponding position on a circuit board; a four-layer spatial three-dimensional structure is formed in the middle non-pin distribution area of the CMOS detector: the first layer is a CMOS detector, and the second layer is a radiating fin tightly attached to the CMOS detector; the third layer is a filter capacitor welded close to the circuit board, and the fourth layer is the circuit board; the width of the region where the pins of the heat-conducting sheet are not distributed is required to be lblank_pinSaid lblank_pinNot less than 5 mm; and a power supply and a bias pin are arranged at the upper end and the lower end of the CMOS detector.
2. The CMOS imaging system based on the staggered tiling application of claim 1, wherein: the spectral distribution of the CMOS detector is set as follows: the panchromatic spectrum is on one side of the detector and the multispectral spectrum is on the rest of the CMOS detector.
3. The CMOS imaging system based on the staggered tiling application of claim 1, wherein: packaging the CMOS detector; the device comprises a pin distribution area, a wafer and a plurality of filter capacitors; the wafer is connected with the plurality of filter capacitors and the pins of the pin distribution area through connecting wires;
setting a capacitance value smaller than 4.7uF, and adopting a single ceramic chip capacitor without leading out a pin;
combining the power supply sources with the same functions of the multispectral spectral bands into one power supply source;
and a ceramic chip capacitor with the capacitance value of 0.01-0.1 uF is added between each power supply pin and each ground pin on the wafer, and a ceramic chip capacitor with the capacitance value of 1-4.7uF is added to each power supply.
4. The CMOS imaging system based on the staggered tiling application of claim 1, wherein: the number n of pins of the CMOS detectorchip_pinRepresented by the formula:
nchip_pin＝ngnd_pin+npower_pin+nbias_pin+ndata_out_pin+ncontrol_pin+ncharge_transfer_pin+nspi_test_clock_pin
in the formula, ngnd_pinThe number of the ground pins of the detector is required to be less than or equal to 2 respectively in an analog ground, a digital ground, an analog-to-digital conversion ground and a pixel ground; n ispower_pinThe number of pins of the power supply of the detector is required to be less than or equal to 2, wherein the number of pins of the same analog power supply, digital power supply and analog-digital power supply is less than or equal to 2;
nbias_pinis the offset pin number of the detector, the offset pin number n of the detectorbias_pinThe value of (d) is equal to the number of pins with the bias capacitance larger than 4.7 uF; n isdata_out_pinNumber of pins, n, for data output by the detectorcontrol_pinControlling the number of pins, n, for the input of the detectorcharge_transfer_pinNumber of input charge transfer pins, n, for the detectorspi_test_clock_pinThe number of the pins is the spi interface, the input clock and the test pin number of the detector.
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CN111510647B (en) * 2020-04-27 2021-08-31 中国科学院长春光学精密机械与物理研究所 Uniform charge transfer control method for multi-spectral-segment TDICMOS

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