CN110854203B - Thin film transistor, array substrate, display panel and display device - Google Patents
Thin film transistor, array substrate, display panel and display device Download PDFInfo
- Publication number
- CN110854203B CN110854203B CN201911146984.3A CN201911146984A CN110854203B CN 110854203 B CN110854203 B CN 110854203B CN 201911146984 A CN201911146984 A CN 201911146984A CN 110854203 B CN110854203 B CN 110854203B
- Authority
- CN
- China
- Prior art keywords
- substrate
- active layer
- thin film
- film transistor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 115
- 239000010409 thin film Substances 0.000 title claims abstract description 43
- 239000000463 material Substances 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 31
- 238000005452 bending Methods 0.000 abstract description 25
- 239000010410 layer Substances 0.000 description 147
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000002161 passivation Methods 0.000 description 7
- 238000000059 patterning Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000007738 vacuum evaporation Methods 0.000 description 4
- 239000000956 alloy Substances 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000595 mu-metal Inorganic materials 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Abstract
The invention relates to the technical field of display and discloses a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor includes a substrate, and an active layer and a source-drain electrode layer sequentially disposed on the substrate, wherein the active layer includes a first portion and a second portion connected to a source electrode and a drain electrode in the source-drain electrode layer, respectively, and a third portion connected between the first portion and the second portion, the first portion and the second portion having a height difference in a direction perpendicular to the substrate. Specifically, when the flexible display panel is bent, the bending radius direction is perpendicular to the surface of the substrate. In the thin film transistor provided by the embodiment of the invention, the third part (channel region) of the active layer extends along the extending direction which is approximately perpendicular to the substrate, the mechanical stress received in the bending process of the substrate is small, the deformation is not easy to occur, the problems of TFT threshold voltage drift, device failure and the like are not easy to cause, and therefore, the performance and the service life of the flexible display panel can be improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a thin film transistor, an array substrate, a display panel, and a display device.
Background
The general manufacturing method of flexible organic electroluminescent (OLED) displays is: preparing a flexible substrate on a carrier substrate, and then preparing a buffer layer, a Thin Film Transistor (TFT) and an organic light emitting diode on the flexible substrate; and after the preparation of the flexible display substrate is finished, the flexible display substrate is peeled off from the bearing substrate by using laser. Specifically, the flexible OLED display product can often buckle in the use, and TFT can continuously receive mechanical stress effect in the buckling process, along with the increase of buckling times, very easily lead to threshold voltage (Vth) drift of TFT, device inefficacy to make flexible display show unusual, even unable normal work.
Disclosure of Invention
The invention discloses a thin film transistor, an array substrate, a display panel and a display device, and aims to improve the structure of a TFT device in a flexible display panel, and improve the performance and service life of the TFT.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the thin film transistor comprises a substrate, and an active layer and a source-drain electrode layer which are sequentially arranged on the substrate, wherein the active layer comprises a first part and a second part which are respectively connected with a source electrode and a drain electrode in the source-drain electrode layer, and a third part which is connected between the first part and the second part, and the first part and the second part have a height difference in a direction perpendicular to the substrate.
Specifically, when the flexible display panel is bent, the bending radius direction is perpendicular to the surface of the substrate. In the Thin Film Transistor (TFT) provided in the embodiment of the present invention, the first portion and the second portion of the active layer are connected to the source electrode and the drain electrode respectively, and the third portion is connected between the first portion and the second portion, i.e., the third portion is configured as a channel region, and the first portion and the second portion are provided with a height difference in a direction perpendicular to the substrate, so that the third portion (channel region) will extend in an extending direction approximately perpendicular to the substrate, and the extending direction tends to be consistent with a direction of a bending radius, and further, in a bending process of the substrate, a mechanical stress received by the third portion (channel region) of the active layer is small, and deformation is not easy to occur, so that problems such as TFT threshold voltage (Vth) drift, device failure and the like are not easy to be caused. In summary, when the TFT according to the embodiment of the present invention is applied to a flexible display panel, the mechanical stress applied to the channel region of the active layer is small during the bending process of the substrate, and the TFT has stable performance and long service life, so that the performance and service life of the flexible display panel can be greatly improved, and the flexible display panel can have a smaller radius of curvature.
Optionally, the thin film transistor further includes a support disposed between the substrate and the active layer, including a bottom surface close to the substrate, a top surface away from the substrate, and a side surface disposed between the bottom surface and the top surface;
the first part of the active layer is positioned on the top surface of the support body, the second part is positioned between the plane of the top surface and the plane of the bottom surface, and the third part extends along the side surface of the support body;
the source electrode and the drain electrode in the source electrode layer are respectively arranged on the first part and the second part of the active layer and are respectively connected with the first part and the second part.
Optionally, the support body is in an inverted cone shape.
Optionally, an included angle between a plane where the bottom surface of the support body is located and the side surface is 45-90 degrees.
Optionally, the active layer includes two active layer patterns independent of each other, each of the active layer patterns includes a first portion, a second portion, and a third portion that are sequentially connected, and the two active layer patterns are symmetrically disposed with respect to the support body;
the source electrode layer comprises two source electrode patterns and two drain electrode patterns, the two source electrode patterns are respectively arranged on first parts of the two active layer patterns, and the two drain electrode patterns are respectively arranged on second parts of the two active layer patterns.
Optionally, the thin film transistor further includes a gate layer disposed between the support and the active layer, and the gate layer surrounds the support.
Optionally, the support is a resin material.
Optionally, the thin film transistor further includes a gate electrode disposed between the substrate and the active layer;
the gate has a raised structure facing away from the substrate, the raised structure being configured as the support.
Optionally, the substrate is a flexible substrate.
An array substrate comprising a thin film transistor according to any one of the above; the substrate of the thin film transistor is configured as a substrate of the array substrate.
A display panel comprises the array substrate and an OLED light-emitting structure arranged on the array substrate.
A display device comprises the display panel.
Drawings
Fig. 1 is a schematic cross-sectional structure of a thin film transistor according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure of a thin film transistor according to another embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of an array substrate in a bent state according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure of a support body in a thin film transistor according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a support in a thin film transistor according to an embodiment of the present invention;
fig. 6 is a schematic diagram of the active layer channel projection length L 'in a state that a part of the active layer channel projection length L' is folded along with the substrate.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, an embodiment of the present invention provides a thin film transistor including a substrate 1, and an active layer 2 and a source-drain electrode layer sequentially disposed on the substrate 1, wherein the active layer 2 includes a first portion 21 and a second portion 22 connected to a source electrode 31 and a drain electrode 32 in the source-drain electrode layer, respectively, and a third portion 23 connected between the first portion 21 and the second portion 22, the first portion 21 and the second portion 22 having a height difference in a direction perpendicular to the substrate 1.
Specifically, as shown in fig. 3, when the flexible display panel is bent, the bending radius direction (the extending direction of the solid line in fig. 3) is perpendicular to the surface of the substrate 1. As shown in fig. 1, in the Thin Film Transistor (TFT) provided in the embodiment of the present invention, the first portion 21 and the second portion 22 of the active layer 2 are respectively connected to the source 31 and the drain 32, the third portion 23 is connected between the first portion 21 and the second portion 22, that is, the third portion 23 is configured as a channel region, and the first portion 21 and the second portion 22 are provided with a height difference in a direction perpendicular to the substrate 1, so that the third portion (channel region) 23 extends along an extending direction close to the perpendicular to the substrate 1, and the extending direction tends to be consistent with a direction of a bending radius, so that during a bending process of the substrate 1, a mechanical stress received by the third portion (channel region) 23 of the active layer 2 is small, deformation is not easy to occur, and thus problems such as TFT threshold voltage (Vth) drift, device failure and the like are not easy to be caused. In summary, when the TFT according to the embodiment of the present invention is applied to a flexible display panel, the channel region of the active layer 2 receives little mechanical stress during the bending process of the substrate 1, and the TFT has stable performance and long service life, so that the performance and service life of the flexible display panel can be greatly improved, and the flexible display panel can have a smaller radius of curvature.
In a specific embodiment, as shown in fig. 1, fig. 2 and fig. 4, the thin film transistor provided in the embodiment of the present invention may further include a support 4, specifically, the support 4 is disposed between the substrate 1 and the active layer 2, and includes a bottom surface 42 close to the substrate 1, a top surface 41 far from the substrate 1, and a side surface 43 disposed between the bottom surface 42 and the top surface 41.
Specifically, as shown in fig. 1, 2 and 4, the first portion 21 of the active layer 2 is located on the top surface 41 of the support 4, the second portion 22 is located between the plane of the top surface 41 and the plane of the bottom surface 42, and the third portion 23 extends along the side surface 43 of the support 4; in this way, the first portion 21 and the second portion 22 of the active layer 2 have a height difference in the direction perpendicular to the substrate 1, and the extending direction of the third portion 23 and the direction of the bending radius tend to be consistent, so that the mechanical stress suffered by the third portion (channel region) 23 in the bending process of the substrate 1 is small, deformation is not easy to occur, and the problems of TFT threshold voltage (Vth) drift, device failure and the like are not easy to cause.
Specifically, the first portion 21 and the second portion 22 of the active layer 2 are configured as ohmic contact regions, and the source electrode 31 and the drain electrode 32 in the source-drain electrode layer are respectively disposed on the first portion 21 and the second portion 22 and are respectively connected to the first portion 21 and the second portion 22. Specifically, as shown in fig. 1 and 2, the source electrode 31 is disposed on the first portion 21, the drain electrode 32 is disposed on the second portion 22, and in actual disposition, the drain electrode 32 may be disposed on the first portion 21, and the source electrode 31 may be disposed on the second portion 22.
In a specific embodiment, as shown in fig. 1, 2 and 4, the support body 4 is in an inverted cone shape, that is, the area of the top surface 41 of the support body 4 is larger than the area of the bottom surface 42, and the support body 4 is gradually narrowed and thinned from the top surface 41 to the bottom surface 42, so that a shielding area 40 is formed below the top surface 41 of the support body 4.
Specifically, because the vacuum evaporation plating is poor, the support body 4 is arranged to be in an inverted cone shape, when the conductive layers of the source electrode 31 and the drain electrode 32 are manufactured by adopting the vacuum evaporation plating process, under the shielding of the inverted cone structure, the metal electrode material is not deposited in the shielding region 40, so that the source electrode 31 and the drain electrode 32 can be directly formed on the top surface 41 and the side of the inverted cone structure respectively, the composition process can be simplified, and a mask plate can be saved when the composition process is adopted to form patterns according to the process requirements. In addition, when the active layer 2 is processed by a Plasma (Plasma) process, the third portion 23 of the active layer 2 is not conductive under the shielding of the inverted cone structure, so that the first portion 21 and the second portion 22 which are not shielded can be directly conductive to become an ohmic contact area, and the processing process of the active layer 2 is simplified.
For example, the longitudinal section of the support body 4 (section perpendicular to the substrate 1) may be in the form of an inverted isosceles trapezoid.
Alternatively, the base angle (the angle between the plane of the bottom surface 42 and the side surface 43, which is the acute angle between the two surfaces, including 90 °) β of the support body 4 is 45 ° to 90 °, and specifically β is optionally 80 °.
Specifically, the support body 4 is not limited to an inverted cone, and may be a cube, a cylinder, a step shape, or other shapes having a certain height, or that is, the longitudinal section of the support body is not limited to an inverted trapezoid, and may be a square, an upright trapezoid, a step shape, or the like.
The deformation of the active layer channel in the embodiment of the invention is explained by the schematic diagrams in fig. 5 and fig. 6, and the numerical analysis shows that the active layer channel in the TFT provided by the embodiment of the invention is not easy to deform along with the substrate, so that the TFT has better performance and longer service life.
Specifically, in fig. 5, the structure of the support body in the embodiment of the present invention is illustrated, L is a side edge of the support body, β is a bottom angle of the support body, and since the active layer channel extends along the side edge of the support body, L is approximately the length of the active layer channel, and β is approximately the inclination angle of the active layer channel; the projection length of the active layer channel on the substrate is L' =lcos beta in the substrate unbent state; since only the portion of the active layer channel extending along the substrate plane is bent during bending of the substrate, the portion corresponding to the projection length L' of the active layer channel is bent and deformed along with the substrate.
The fan shape in fig. 6 is a schematic diagram of the dimension of the projected length L ' of the active layer channel along with the bending process of the substrate, as shown in fig. 6, a section of bending arc in the figure represents a section of the projected length L ' of the active layer channel in a bending state, r is a bending radius, Δh is a distance between a chord and an arc, and can represent the bending degree of L '. Specifically, according to the geometric formula, L ' =2α×r, Δh=r-rcos α, it can be known from the two formulas that L ' is proportional to Δh, that is, the larger the projection length L ' of the active layer channel is, the larger Δh is, and the larger the bending deformation of the active layer channel is.
As is clear from the formula L '=lcos β, β is inversely proportional to L', and further, β is inversely proportional to Δh, and thus, when the length L of the active layer channel is determined, β is larger and Δh is smaller. Therefore, in the embodiment of the invention, the base angle beta of the support body is selected to be 80 degrees, so that the support body can have an inverted cone shape, and the deformation of the active layer channel when the substrate 1 is bent can be reduced as much as possible, thereby effectively improving the performance and the service life of the TFT.
Specifically, β may be set to 90 °, and in this case, the projection length L' of the active layer channel on the substrate is approximately zero (when the thickness of the active layer is ignored), the deformation of the active layer channel when the substrate is bent is approximately zero, and the performance and lifetime improvement effect of the TFT are best.
In a specific embodiment, as shown in fig. 2, the active layer 2 includes two active layer patterns (201 and 202) independent of each other, each of the active layer patterns includes a first portion 21, a second portion 22, and a third portion 23 connected in sequence, and the two active layer patterns are symmetrically disposed with respect to the support 4.
Specifically, the source-drain electrode layer includes two source patterns (311 and 312) and two drain patterns (321 and 322), which are respectively disposed on the first portions 21 of the two active layer patterns, and which are respectively disposed on the second portions 22 of the two active layer patterns.
As shown in fig. 2, two active layer patterns are provided, namely a first active layer pattern 201 and a second active layer pattern 202, respectively, two source patterns are provided, namely a first source pattern 311 and a second source pattern 312, respectively, and two drain patterns are provided, namely a first drain pattern 321 and a second drain pattern 322, respectively; the first source pattern 311 and the first drain pattern 321 are conducted through the first active layer pattern 201, the second source pattern 312 and the second drain pattern 322 are conducted through the second active layer pattern 202, and the extending directions of the channel regions (the third portion 23) of the first active layer pattern 201 and the second active layer pattern 202 are consistent with the direction of the bending radius, so that the mechanical stress received in the bending process of the substrate 1 is very small, and the problems of TFT threshold voltage (Vth) drift, device failure and the like are not easy to cause; specifically, fig. 3 is a schematic structural diagram of the thin film transistor 100 provided in the embodiment of the present invention in a state of bending along with the substrate, as can be seen from fig. 3, the extending directions of the channel regions of the two active layer patterns (the extending directions of the two dotted lines in fig. 3) are all consistent with the direction of the bending radius (the extending direction of the solid line in fig. 3), so that the mechanical stress applied to the two channel regions is very small in the bending process of the substrate 1.
Specifically, as shown in fig. 2, the two source patterns (311 and 312) may be connected together, and the two drain patterns (321 and 322) are connected to the same pixel electrode 9, that is, the source-drain electrode layer in the embodiment of the present invention is used to realize the conduction of the same signal, where the thin film transistor provided in the embodiment of the present invention is equivalent to a TFT functional structure, and the TFT functional structure realizes the conduction between the two source and drain electrodes through two channel regions at the same time, so that the performance of the TFT may be effectively improved; alternatively, the two source patterns (311 and 312) are not electrically connected, and the two drain patterns (321 and 322) are respectively connected to the two different pixel electrodes 9, where the source-drain electrode layer in the embodiment of the present invention may be used to realize the conduction of two signals, and the thin film transistor provided in the embodiment of the present invention may be equivalent to two TFT functional structures.
Specifically, the two active layer patterns, the two source electrode patterns and the two drain electrode patterns in the embodiment of the invention can be respectively and symmetrically arranged relative to the support body or asymmetrically arranged, and can be specifically determined according to actual requirements.
In a specific embodiment, as shown in fig. 1, the support 4 may be a separate structure, and may be specifically manufactured by patterning using a resin material.
Specifically, the thin film transistor provided in the embodiment of the present invention may further include a gate layer 51 disposed between the support 4 and the active layer 2, and specifically, the gate layer 51 surrounds the support 4.
Further, the thin film transistor provided in the embodiment of the present invention further includes a gate insulating layer 6 disposed between the gate layer 51 and the active layer 2, where the gate insulating layer 6 surrounds the support 4 and completely covers the gate layer 51.
In another specific embodiment, as shown in fig. 2, the thin film transistor provided in the embodiment of the present invention includes a gate electrode 52 disposed between the substrate 1 and the active layer 2; specifically, the gate 52 has a protruding structure facing away from the substrate 1, and the protruding structure is configured as the support 4, in other words, the support 4 may not be a separate structure, but a part of the gate 52 pattern, so that the manufacturing process of the support 4 may be omitted and a mask may be saved. Further, the thin film transistor provided by the embodiment of the invention further includes a gate insulating layer 6 disposed between the gate electrode 52 and the active layer 2, where the gate insulating layer 6 surrounds the support 4 and completely covers the gate electrode 52.
Optionally, the gate adopts an Al/ITO laminated structure, and in particular, the ITO material layer is located on a side of the Al material layer facing away from the substrate, and the Al/ITO laminated structure is easily etched to form an inverted cone structure due to the etching selectivity.
Of course, the gate is not limited to the above materials, and the convex structure of the gate is not limited to the inverted cone shape; specifically, the gate electrode may be formed of one or more metal materials such as Mo, al, and cμ, and may have one or more layers, for example, the gate electrode may be formed of a metal Mo material and patterned to form a convex structure (support body) having a square longitudinal section.
Specifically, the above embodiment of the present invention is described taking an overlapping TFT as an example, that is, the gate electrode and the source-drain electrode in the TFT are respectively disposed on two sides of the active layer, but the embodiment of the present invention is not limited to the above structure, and in practical design, a coplanar TFT may also be used, that is, the gate electrode and the source-drain electrode in the TFT are both disposed on the same side of the active layer (on the side facing away from the substrate).
In a specific embodiment, the substrate is a flexible substrate, i.e., the substrate is flexible, and the material of the flexible substrate includes Polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and the like.
Specifically, in the embodiment of the present invention, the active layer material may include a-Si, IGZO, ITZO, znNO, etc.; the source electrode layer, the drain electrode layer and the gate electrode layer can be made of metal materials such as Cr, ti, mo, W, al, cu, alloy materials or other conductive materials.
Specifically, as shown in fig. 1 and 2, in the manufacturing process, the flexible substrate 1 may be first manufactured on the carrier substrate 10, then functional layers are manufactured on the flexible substrate 1, and after each functional layer is manufactured, the flexible substrate 1 and the carrier substrate 10 are peeled off by using a laser.
Specifically, as shown in fig. 1 and fig. 2, the thin film transistor provided in the embodiment of the present invention may further include structures such as a buffer layer 7 and a passivation layer 8, which are not described herein in detail.
The embodiment of the invention also provides an array substrate, as shown in fig. 3, where the array substrate includes the thin film transistor 100 described in any one of the above; specifically, the substrate 1 of the thin film transistor 100 is configured as a substrate of the array substrate.
Specifically, based on the array substrate provided by the embodiment of the present invention, the present embodiment further provides a method for preparing an array substrate, where the method specifically may include the following steps:
step 101, cleaning a carrier substrate
Firstly, the bearing substrate is cleaned. The bearing substrate can be glass, silicon wafer, stainless steel sheet, plastic and the like; specifically, a glass substrate may be used in this embodiment.
Step 102, manufacturing a flexible substrate
Preparing a flexible substrate through a spin coating or pasting process, wherein the material of the flexible substrate can comprise Polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and the like; the thickness of the flexible substrate may be 1-300 μm, in particular 200 μm in this embodiment.
Step 103, manufacturing a buffer layer
Depositing a buffer layer by Chemical Vapor Deposition (CVD) technique, wherein the buffer layer can be SiO x 、SiN x 、SiON x 、AlO x And one or more insulating materials, the buffer layer can be one or more layers of structures, and the thickness is 1nm-800nm. Specifically, the buffer layer in this embodiment may be made of SiO x The thickness is optionally 300nm.
Step 104, manufacturing a metal gate
And preparing a grid electrode conducting layer on the buffer layer, wherein the grid electrode conducting layer can be made of Cr, ti, mo, W, al, C mu metal materials, alloy materials or other conducting materials. The gate conductive layer may be one or more layers having a thickness of 1nm to 2000nm. The gate material in this embodiment may be selected to be an Al/ITO stack, and the thickness may be selected to be 300nm. After the gate conductive layer is deposited, a gate pattern can be formed by a patterning process, and the gate pattern can include inverted cone-shaped protrusions as a support. Of course, an inverted cone-shaped support body can be formed by a patterning process before the gate conductive layer is deposited, then the gate conductive layer is deposited, and a gate pattern surrounding the inverted cone-shaped support body can be formed by the patterning process according to the process requirement.
Step 105, manufacturing a gate insulating layer
Depositing a gate insulating layer by Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD), wherein the gate insulating layer can be SiO x 、SiN x 、SiON x 、AlO x The gate insulating layer can be one or more layers of structures and the thickness can be 1nm-800nm. Specifically, the gate insulating layer in this embodiment may be SiO x The thickness is optionally 300nm.
Step 106, manufacturing an active layer
Depositing an active layer material by adopting a magnetron sputtering technology, and forming an active layer on the grid inverted cone structure by a patterning process, wherein the active layer material can comprise: IGZO, ITZO, HIZO, ATZIO, ATZO, ZTO, GTO, IGTO, znO, the active layer may be one or more layers, and the thickness may be 1nm-500nm, and this embodiment may be 50nm. After depositing active layer material, patterning process is adopted to form active layer pattern according to process requirement, and He and N can be used 2 O and the like are subjected to a Plasma treatment process, and the conductive of the non-shielded parts (the first part and the second part of the active layer) can be directly realized under the shielding of the inverted cone structure.
Step 107, manufacturing source and drain
The source-drain electrode conductive layer is manufactured by adopting a vacuum evaporation process, and the source-drain electrode conductive layer can be manufactured by adopting a Cr, ti, mo, W, al, C mu metal material, an alloy material or other conductive materials. The source/drain electrode conductive layer may have one or more layers, and the thickness may be 1nm to 2000nm, and this embodiment may be 400nm. Because vacuum evaporation has poor plating surrounding property, the source electrode and the drain electrode can be directly formed on the first part and the second part of the active layer under the shielding of the inverted cone structure.
Step 108, manufacturing passivation layer
Depositing a passivation layer by Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD), wherein the passivation layer may be SiO x 、SiN x 、SiON x 、AlO x The passivation layer is made of one or more insulating materials, and the passivation layer can be of one or more layers and has a thickness of 1nm-800nm; and then forming a connection via hole between the pixel electrode and the source/drain electrode through a patterning process. The passivation layer in this embodiment may be SiO x The thickness is optionally 300nm.
Step 109, manufacturing a pixel electrode
Depositing a pixel electrode by adopting a magnetron sputtering technology, wherein the pixel electrode material comprises the following components: ITO, IZO, ag, mg, al, etc., the above pixel electrode may have a one-layer or multi-layer structure, and the thickness may be 1nm to 2000nm; the thickness of this embodiment is optionally 40nm.
Specifically, the preparation of the array substrate is completed by forming the complete TFT array through the steps, and if the display function is to be further realized, the planarization layer, the pixel defining layer, the evaporation of the light Emitting Layer (EL), the fabrication of the encapsulation layer, and the like can be selectively fabricated as required.
Specifically, an embodiment of the present invention provides a display panel, where the display panel includes the above array substrate, and further, the display panel includes an OLED light emitting structure disposed on the array substrate.
Specifically, the display panel provided by the embodiment of the invention is a flexible display panel. The TFT in the flexible display panel has small mechanical stress on the active layer channel region in the bending process of the substrate, and has stable performance and long service life, thereby greatly improving the performance and service life of the whole flexible display panel and enabling the flexible display panel to have smaller curvature radius.
In addition, the embodiment of the invention also provides a display device which comprises the display panel.
The display device provided by the embodiment of the invention can be a mobile phone, a flat panel, a display, a television, a billboard, a lighting device and the like.
It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (11)
1. A thin film transistor is characterized by comprising a substrate, and an active layer and a source drain electrode layer which are sequentially arranged on the substrate; the thin film transistor further includes a support disposed between the substrate and the active layer;
the active layer includes a first portion and a second portion connected to a source electrode and a drain electrode in the source-drain electrode layer, respectively, and a third portion connected between the first portion and the second portion, the first portion and the second portion having a height difference in a direction perpendicular to the substrate;
the active layer comprises two active layer patterns which are mutually independent, each active layer pattern comprises a first part, a second part and a third part which are sequentially connected, and the two active layer patterns are symmetrically arranged relative to the supporting body;
the source electrode layer comprises two source electrode patterns and two drain electrode patterns, the two source electrode patterns are respectively arranged on first parts of the two active layer patterns, and the two drain electrode patterns are respectively arranged on second parts of the two active layer patterns.
2. The thin film transistor according to claim 1, wherein the support includes a bottom surface close to the substrate, a top surface away from the substrate, and a side surface provided between the bottom surface and the top surface;
the first part of the active layer is positioned on the top surface of the support body, the second part is positioned between the plane of the top surface and the plane of the bottom surface, and the third part extends along the side surface of the support body;
the source electrode and the drain electrode in the source electrode layer are respectively arranged on the first part and the second part of the active layer and are respectively connected with the first part and the second part.
3. The thin film transistor according to claim 2, wherein the support body has an inverted cone shape.
4. The thin film transistor according to claim 3, wherein an angle between a plane in which the bottom surface of the support body is located and the side surface is 45 ° to 90 °.
5. The thin film transistor of claim 1, further comprising a gate layer disposed between the support and the active layer, the gate layer surrounding the support.
6. The thin film transistor according to claim 5, wherein the support is a resin material.
7. The thin film transistor of claim 1, further comprising a gate electrode disposed between the substrate and the active layer;
the gate has a raised structure facing away from the substrate, the raised structure being configured as the support.
8. The thin film transistor according to any one of claims 1 to 7, wherein the substrate is a flexible substrate.
9. An array substrate comprising the thin film transistor of any one of claims 1-8; the substrate of the thin film transistor is configured as a substrate of the array substrate.
10. A display panel comprising the array substrate of claim 9, and an OLED light emitting structure disposed on the array substrate.
11. A display device comprising the display panel according to claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911146984.3A CN110854203B (en) | 2019-11-21 | 2019-11-21 | Thin film transistor, array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911146984.3A CN110854203B (en) | 2019-11-21 | 2019-11-21 | Thin film transistor, array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110854203A CN110854203A (en) | 2020-02-28 |
| CN110854203B true CN110854203B (en) | 2023-10-03 |
Family
ID=69603069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911146984.3A Active CN110854203B (en) | 2019-11-21 | 2019-11-21 | Thin film transistor, array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110854203B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633101A (en) * | 2016-04-01 | 2016-06-01 | 京东方科技集团股份有限公司 | TFT array substrate and manufacture method thereof, and display device |
| CN108054140A (en) * | 2017-12-06 | 2018-05-18 | 深圳市华星光电技术有限公司 | FFS mode array substrate and its manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103178119B (en) * | 2013-03-25 | 2015-07-29 | 京东方科技集团股份有限公司 | Array base palte, array base palte preparation method and display unit |
| CN107482064B (en) * | 2017-08-28 | 2019-10-25 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor and its manufacturing method and array substrate |
-
2019
- 2019-11-21 CN CN201911146984.3A patent/CN110854203B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633101A (en) * | 2016-04-01 | 2016-06-01 | 京东方科技集团股份有限公司 | TFT array substrate and manufacture method thereof, and display device |
| CN108054140A (en) * | 2017-12-06 | 2018-05-18 | 深圳市华星光电技术有限公司 | FFS mode array substrate and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110854203A (en) | 2020-02-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20210234129A1 (en) | Flexible organic light emitting diode display panel | |
| CN108183126B (en) | Elastic display panel manufacturing method, elastic display panel and display thereof | |
| CN106816473B (en) | Thin film transistor, preparation method thereof, array substrate and display device | |
| US20100044708A1 (en) | Thin film transistor, pixel structure and fabrication methods thereof | |
| TWI697115B (en) | Organic light-emitting display device and method of manufacturing the same | |
| US20220375966A1 (en) | Array substrate and manufacturing method therefor, and display panel | |
| US10788907B2 (en) | Touch display substrate, fabrication method and touch display device | |
| US11296235B2 (en) | Thin film transistor having a wire grid on a channel region and manufacturing method thereof, array substrate and manufacturing method thereof, and display panel | |
| EP2657969A2 (en) | Array substrate and method of fabricating the same | |
| US11939657B2 (en) | Hybrid mask stick and mask frame assembly employing the same | |
| KR20160071578A (en) | Mask frame assembly, manufacturing method of the same and manufacturing method of organic light emitting display device there used | |
| CN110061034B (en) | Preparation method of OLED display panel and OLED display panel | |
| CN113689798B (en) | bendable display | |
| CN109378326A (en) | Display panel and preparation method thereof | |
| KR20160049165A (en) | Mask frame assembly, manufacturing method of the same and manufacturing method of organic light emitting display device there used | |
| US20230066211A1 (en) | Display device | |
| US10361261B2 (en) | Manufacturing method of TFT substrate, TFT substrate, and OLED display panel | |
| CN110854203B (en) | Thin film transistor, array substrate, display panel and display device | |
| US20230329056A1 (en) | Organic light emitting display device | |
| CN110518023B (en) | Array substrate and preparation method thereof | |
| CN105304653A (en) | Pixel structure, array substrate, liquid crystal panel, and pixel structure manufacturing method | |
| CN113745249B (en) | Display panel, preparation method thereof and mobile terminal | |
| CN212230409U (en) | OLED display structure | |
| JP6378769B2 (en) | Optical device | |
| CN106030821B (en) | Top-gate thin-film transistors, array substrate and its manufacturing method and TFT device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |