CN110854202A - Fin type transistor and manufacturing method thereof - Google Patents
Fin type transistor and manufacturing method thereof Download PDFInfo
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- CN110854202A CN110854202A CN201911174067.6A CN201911174067A CN110854202A CN 110854202 A CN110854202 A CN 110854202A CN 201911174067 A CN201911174067 A CN 201911174067A CN 110854202 A CN110854202 A CN 110854202A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 98
- 239000002184 metal Substances 0.000 claims abstract description 98
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 69
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 69
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 239000001301 oxygen Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 128
- 239000011229 interlayer Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 51
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 24
- 229910008484 TiSi Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000007796 conventional method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a fin type transistor, comprising: the shallow trenches between the fin bodies are filled with field oxygen; a cell structure of the fin transistor is formed on the fin top structure, the cell structure comprising: a gate structure, a source region and a drain region; grooves are formed in the fin body top structures on two sides of the grid structure and filled with embedded epitaxial layers, and the source region and the drain region are formed in the corresponding embedded epitaxial layers; and the metal silicide is formed on the whole outer side surface of the embedded epitaxial layer so as to increase the contact area of the source region or the drain region corresponding to the metal silicide, and the metal silicide on the surfaces of the source region and the drain region is respectively contacted with the contact holes corresponding to the tops of the source region and the drain region. The invention also discloses a manufacturing method of the fin type transistor. The invention can reduce the contact resistance of the source and drain contact hole of the device and thereby improve the performance of the device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a fin transistor. The invention also relates to a manufacturing method of the fin type transistor.
Background
Fig. 1 is a schematic diagram of a conventional fin transistor; the conventional fin transistor includes:
a fin 102, wherein the fin 102 is formed by etching the semiconductor material of the semiconductor substrate 101.
Typically, the semiconductor substrate 101 is a silicon substrate.
The shallow trenches between the fins 102 are filled with field oxide 103, and the top surface of the field oxide 103 is lower than the top surface of the fins 102.
The portion of the fin 102 protruding above the field oxide 103 is a fin top structure. In fig. 1, the surface 104 is a top surface of the field oxide 103, and the fin top structure is a structure of the fin 102 located above the surface 104.
A cell structure of a fin transistor is formed on the fin top structure, the cell structure comprising: a gate structure, a source region and a drain region.
The grid structure comprises a grid dielectric layer and a metal grid which are sequentially overlapped, wherein the grid dielectric layer comprises a high dielectric constant layer.
The grid electrode structure covers the side face of the fin body top structure or the grid electrode structure covers the side face and the top surface of the fin body top structure.
Grooves are formed in the fin body top structures on two sides of the grid structure, an embedded epitaxial layer 105 is filled in the grooves, and the source region and the drain region are formed in the corresponding embedded epitaxial layer 105. The groove has a sigma-shaped structure.
The fin transistors are N-type fin transistors, and the embedded epitaxial layer 105 is a SiP epitaxial layer. Can also be: the fin transistors are P-type fin transistors, and the embedded epitaxial layer 105 is a SiGe epitaxial layer.
An interlayer film 201 covers the surface of the embedded epitaxial layer 105, the field oxide 103 and the gate structure.
A contact hole 203 is formed in the interlayer film 201 so as to pass through the interlayer film 201. The contact hole 203 is made of a metal such as tungsten filled in the opening 202.
A source electrode, a drain electrode, and a gate electrode composed of a front metal layer are formed on the surface of the interlayer film 201.
The source region is in contact with and connected to the source electrode through the top corresponding contact hole 203, the drain region is in contact with and connected to the drain electrode through the top corresponding contact hole 203, and the top of the polysilicon gate is connected to the gate electrode through the corresponding contact hole 203.
A metal silicide 106 is formed on the surface of the embedded epitaxial layer 105 at the bottom of the contact hole 203 corresponding to the source region and the drain region.
In the conventional method for manufacturing a fin transistor, the metal silicide 106 is formed in a middle-of-line process (MEOL), wherein MEOL corresponds to a forming process of the interlayer film 201 and a forming process of the contact hole 203, in the conventional method, after the opening 202 of the contact hole 203 is formed, metal deposition and annealing silicidation of the metal silicide 106 are performed, and finally, a metal such as tungsten is filled in the opening 202 of the contact hole 203 to form the contact hole, so that the area of the metal silicide 106 of the source and drain contact holes in the conventional method is limited by the size of the contact hole 203, which may adversely affect the source and drain contact resistance of the device. With the development of a semiconductor process, the size of a device is continuously reduced in an equal proportion, and when the process node of the fin transistor is reduced to be below 14nm, the conventional method is not beneficial to the reduction of the source-drain contact resistance of the device, so that the improvement of the electrical performance of the device is influenced.
Disclosure of Invention
The invention aims to provide a fin type transistor, which can reduce the contact resistance of a source drain contact hole of a device and improve the performance of the device. Therefore, the invention also provides a manufacturing method of the fin type transistor.
To solve the above technical problem, the present invention provides a fin transistor including:
the fin body is formed by etching the semiconductor material of the semiconductor substrate.
And field oxygen is filled in the shallow trench between the fin bodies, and the top surface of the field oxygen is lower than that of the fin bodies.
The part of the fin body protruding above the field oxygen is a fin body top structure.
A cell structure of a fin transistor is formed on the fin top structure, the cell structure comprising: a gate structure, a source region and a drain region.
The grid electrode structure covers the side face of the fin body top structure or the grid electrode structure covers the side face and the top surface of the fin body top structure.
Grooves are formed in the fin body top structures on two sides of the grid electrode structure, an embedded epitaxial layer is filled in the grooves, and the source region and the drain region are formed in the corresponding embedded epitaxial layer.
And the metal silicide is formed on the whole outer side surface of the embedded epitaxial layer so as to increase the contact area of the source region or the drain region corresponding to the metal silicide, and the whole outer side surface of the embedded epitaxial layer comprises a side surface and a top surface.
The interlayer film covers the surface of the metal silicide and the surface of the gate structure.
A contact hole is formed in the interlayer film so as to penetrate through the interlayer film.
And a source electrode, a drain electrode and a grid electrode which are composed of a front metal layer are formed on the surface of the interlayer film.
The metal silicide on the surface of the source region is contacted with the contact hole corresponding to the top and connected to the source electrode, the metal silicide on the surface of the drain region is contacted with the contact hole corresponding to the top and connected to the drain electrode, and the top of the polysilicon gate is connected to the gate electrode through the corresponding contact hole.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the fin transistors are N-type fin transistors, and the embedded epitaxial layer is a SiP epitaxial layer.
In a further improvement, the fin transistors are P-type fin transistors, and the embedded epitaxial layer is a SiGe epitaxial layer.
In a further refinement, the metal silicide comprises TiSi.
In a further development, the recess has a sigma-shaped configuration.
In a further improvement, the process node of the fin transistor is below 14 nm.
The gate structure comprises a gate dielectric layer and a metal gate which are sequentially overlapped, wherein the gate dielectric layer comprises a high dielectric constant layer.
In order to solve the above technical problem, the method for manufacturing a fin transistor according to the present invention includes the steps of:
step one, providing a semiconductor substrate, and etching the semiconductor material of the semiconductor substrate to form a fin body.
Filling field oxygen in the shallow trenches among the fin bodies, wherein the top surfaces of the field oxygen are lower than the top surfaces of the fin bodies; the part of the fin body protruding above the field oxygen is a fin body top structure.
And step three, forming a pseudo gate structure corresponding to the unit structure of the fin transistor on the fin body top structure.
And fourthly, performing self-aligned etching on the fin body top structures on two sides of the pseudo gate structure to form a groove.
And step five, filling the embedded epitaxial layer in the groove.
And sixthly, performing self-aligned source-drain injection to form a source region and a drain region in the embedded epitaxial layer at two sides of the pseudo gate structure.
Seventhly, forming metal silicide in a self-alignment mode on the whole outer side surface of the embedded epitaxial layer where the source region and the drain region are formed so as to increase the contact area of the source region or the drain region corresponding to the metal silicide, wherein the whole outer side surface of the embedded epitaxial layer comprises a side surface and a top surface.
And step eight, forming a zero layer interlayer film, wherein the zero layer interlayer film covers the surface of the metal silicide, and the top surface of the zero layer interlayer film is level to the top surface of the dummy gate structure.
And ninthly, removing the pseudo gate structure, and forming a gate structure in the removal region of the pseudo gate structure, wherein the gate structure comprises a gate dielectric layer and a metal gate which are sequentially overlapped, and the gate dielectric layer comprises a high dielectric constant layer.
Tenth, forming a first interlayer film, wherein the first interlayer film covers the surfaces of the zero-layer interlayer film and the gate structure, and the zero-layer interlayer film and the first interlayer film are overlapped to form an integral interlayer film.
Step eleven, forming a contact hole penetrating through the interlayer film.
And step twelve, finishing a back-end process, wherein the back-end process comprises the step of forming a source electrode, a drain electrode and a grid electrode which are composed of a front metal layer on the surface of the interlayer film.
The metal silicide on the surface of the source region is contacted with the contact hole corresponding to the top and connected to the source electrode, the metal silicide on the surface of the drain region is contacted with the contact hole corresponding to the top and connected to the drain electrode, and the top of the polysilicon gate is connected to the gate electrode through the corresponding contact hole.
In a further improvement, the semiconductor substrate is a silicon substrate.
The further improvement is that the fin type transistor is an N type fin type transistor, and the embedded epitaxial layer is a SiP epitaxial layer; or the fin type transistor is a P-type fin type transistor, and the embedded epitaxial layer is a SiGe epitaxial layer.
In a further refinement, the metal silicide comprises TiSi.
In a further development, the recess has a sigma-shaped configuration.
The further improvement is that the front metal layer comprises a plurality of layers, interlayer films of corresponding layers are isolated among the front metal layers, and the source electrode, the drain electrode and the grid electrode are formed by the front metal layer at the topmost layer.
In a further improvement, the process node of the fin transistor is below 14 nm.
In the fin type transistor, the metal silicide corresponding to the bottoms of the source and drain contact holes, namely the contact holes at the tops of the source region and the drain region, covers the outer side surface of the whole embedded epitaxial layer, so that the coverage area of the metal silicide is maximized, and the corresponding resistance is the ratio of the resistivity to the area under the condition that the resistivity of the metal silicide is not changed, so that the larger the area is, the smaller the corresponding resistance is, and the contact resistance of the source and drain contact holes of the device can be reduced after the coverage area of the metal silicide is maximized, so that the on-resistance of the device can be reduced, and the performance of the device can be improved.
In the prior art, the metal silicide of the source-drain contact hole is formed in a middle-stage process (MEOL),
the middle process corresponds to the forming process of an interlayer film and the forming process of a contact hole, the existing method is to carry out metal deposition and annealing silicification on metal silicide after an opening of the contact hole is formed, and finally, metal such as tungsten is filled in the opening of the contact hole to form the contact hole, so that the area of the metal silicide of the source drain contact hole is limited by the size of the contact hole in the existing method; the fin type transistor manufacturing method breaks through the conventional thinking limit of the metal silicide for forming the source and drain contact holes in the existing method, the forming process of the metal silicide is directly placed in the front-end process (FEOL) before MEOL, and the metal silicide of the source and drain contact holes is directly formed mainly after the formation of the embedded epitaxial layer and the source and drain injection in the embedded epitaxial layer, so that the metal silicide of the source and drain contact holes can be formed on the whole outer side surface of the embedded epitaxial layer in a self-aligning mode, the contact resistance of the source and drain contact holes of the device can be reduced after the coverage area of the metal silicide is maximized, and the on-resistance of the device can be reduced, and the performance of the device can be improved.
The invention can be suitable for the device with a process node below 14nm, such as 14HF device process, wherein the 14HF device comprises a fin body process and an HKMG process, HK represents a high dielectric constant layer, and MG represents a metal gate. In addition, the metal silicide of the source and drain contact holes can realize better performance by adopting TiSi, the TiSi is combined with the ion implantation of amorphous treatment (PAI) and the source and drain implantation process with high dosage, the low source and drain contact resistivity can be obtained, the process temperature is low, the resistivity and the process temperature can be well adapted to the process requirements of fin transistors, and the performance of devices can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic diagram of a conventional fin transistor;
fig. 2 is a schematic structural diagram of a fin transistor according to an embodiment of the invention.
Detailed Description
Fig. 2 is a schematic structural diagram of a fin transistor according to an embodiment of the present invention; the fin transistor of the embodiment of the invention comprises:
and the fin body 2 is formed by etching the semiconductor material of the semiconductor substrate 1.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate.
The shallow trenches between the fins 2 are filled with field oxygen 3, and the top surfaces of the field oxygen 3 are lower than the top surfaces of the fins 2.
The part of the fin body 2 protruding above the field oxide 3 is a fin body top structure. In fig. 2, the surface 4 is the top surface of the field oxide 3, and the fin top structure is the structure of the fin 2 located above the surface 4.
A cell structure of a fin transistor is formed on the fin top structure, the cell structure comprising: a gate structure, a source region and a drain region.
The process node of the fin transistor is below 14 nm.
The grid structure comprises a grid dielectric layer and a metal grid which are sequentially overlapped, wherein the grid dielectric layer comprises a high dielectric constant layer.
The grid electrode structure covers the side face of the fin body top structure or the grid electrode structure covers the side face and the top surface of the fin body top structure.
Grooves are formed in the fin body top structures on two sides of the grid structure, an embedded epitaxial layer 5 is filled in the grooves, and the source region and the drain region are formed in the corresponding embedded epitaxial layer 5. The groove has a sigma-shaped structure.
In the embodiment of the invention, the fin type transistor is an N type fin type transistor, and the embedded epitaxial layer 5 is a SiP epitaxial layer. In other embodiments can also be: the fin type transistor is a P type fin type transistor, and the embedded epitaxial layer 5 is a SiGe epitaxial layer.
The metal silicide 6 is formed on the whole outer side surface of the embedded epitaxial layer 5 to increase the contact area of the source region or the drain region corresponding to the metal silicide 6, and the whole outer side surface of the embedded epitaxial layer 5 comprises a side surface and a top surface. Preferably, the metal silicide 6 is TiSi.
The interlayer film covers the surface of the metal silicide 6 and the surface of the gate structure.
A contact hole is formed in the interlayer film so as to penetrate through the interlayer film.
And a source electrode, a drain electrode and a grid electrode which are composed of a front metal layer are formed on the surface of the interlayer film.
The metal silicide 6 on the surface of the source region is contacted with the corresponding contact hole on the top and connected to the source electrode, the metal silicide 6 on the surface of the drain region is contacted with the corresponding contact hole on the top and connected to the drain electrode, and the top of the polysilicon gate is connected to the gate electrode through the corresponding contact hole.
In the fin transistor, the metal silicide 6 corresponding to the bottoms of the source and drain contact holes, namely the contact holes at the tops of the source region and the drain region, covers the outer side surface of the whole embedded epitaxial layer 5, so that the coverage area of the metal silicide 6 can be maximized, and the corresponding resistance is the ratio of the resistivity to the area under the condition that the resistivity of the metal silicide 6 is not changed, so that the larger the area is, the smaller the corresponding resistance is, but after the coverage area of the metal silicide 6 is maximized, the contact resistance of the source and drain contact holes of the device can be reduced, so that the on-resistance of the device can be reduced, and the performance of the device can be improved.
The manufacturing method of the fin type transistor comprises the following steps:
step one, providing a semiconductor substrate 1, and etching the semiconductor material of the semiconductor substrate 1 to form a fin body 2.
The semiconductor substrate 1 is a silicon substrate.
Filling field oxygen 3 in the shallow trenches among the fin bodies 2, wherein the top surfaces of the field oxygen 3 are lower than the top surfaces of the fin bodies 2; the part of the fin body 2 protruding above the field oxide 3 is a fin body top structure.
And step three, forming a pseudo gate structure corresponding to the unit structure of the fin transistor on the fin body top structure.
The process node of the fin transistor is below 14 nm.
The pseudo gate structure comprises a gate dielectric layer and a polysilicon gate which are sequentially overlapped.
And fourthly, performing self-aligned etching on the fin body top structures on two sides of the pseudo gate structure to form a groove.
The groove has a sigma-shaped structure.
And step five, filling the embedded epitaxial layer 5 in the groove.
In the method of the embodiment of the invention, the fin type transistor is an N type fin type transistor, and the embedded epitaxial layer 5 is a SiP epitaxial layer. In other embodiments the method can also be: the fin type transistor is a P type fin type transistor, and the embedded epitaxial layer 5 is a SiGe epitaxial layer.
And sixthly, performing self-aligned source-drain injection to form a source region and a drain region in the embedded epitaxial layer 5 at two sides of the pseudo gate structure.
Seventhly, forming a metal silicide 6 on the whole outer side surface of the embedded epitaxial layer 5 with the source region and the drain region in a self-alignment mode to increase the contact area of the source region or the drain region corresponding to the metal silicide 6, wherein the whole outer side surface of the embedded epitaxial layer 5 comprises a side surface and a top surface.
Preferably, the metal silicide 6 comprises TiSi.
And step eight, forming a zero-layer interlayer film, wherein the zero-layer interlayer film covers the surface of the metal silicide 6, and the top surface of the zero-layer interlayer film is flush with the top surface of the dummy gate structure.
And ninthly, removing the pseudo gate structure, and forming a gate structure in the removal region of the pseudo gate structure, wherein the gate structure comprises a gate dielectric layer and a metal gate which are sequentially overlapped, and the gate dielectric layer comprises a high dielectric constant layer.
Tenth, forming a first interlayer film, wherein the first interlayer film covers the surfaces of the zero-layer interlayer film and the gate structure, and the zero-layer interlayer film and the first interlayer film are overlapped to form an integral interlayer film.
Step eleven, forming a contact hole penetrating through the interlayer film.
And step twelve, finishing a back-end process, wherein the back-end process comprises the step of forming a source electrode, a drain electrode and a grid electrode which are composed of a front metal layer on the surface of the interlayer film.
The metal silicide 6 on the surface of the source region is contacted with the corresponding contact hole on the top and connected to the source electrode, the metal silicide 6 on the surface of the drain region is contacted with the corresponding contact hole on the top and connected to the drain electrode, and the top of the polysilicon gate is connected to the gate electrode through the corresponding contact hole.
The front metal layers comprise a plurality of layers, interlayer films of corresponding layers are isolated among the front metal layers, and the source electrode, the drain electrode and the grid electrode are formed by the front metal layer on the topmost layer.
In the existing method, metal silicide 6 of a source-drain contact hole is formed in MEOL, wherein MEOL corresponds to the forming process of an interlayer film and the forming process of a contact hole, in the existing method, after the opening of the contact hole is formed, metal deposition and annealing silicification of the metal silicide 6 are carried out, and finally, metal such as tungsten is filled in the opening of the contact hole to form the contact hole, so that the area of the metal silicide 6 of the source-drain contact hole in the existing method is limited by the size of the contact hole; the fin transistor manufacturing method breaks through the conventional thought limit of the metal silicide 6 for forming the source and drain contact holes in the existing method, the forming process of the metal silicide 6 is directly placed in the front-end process (FEOL) before MEOL, the metal silicide 6 of the source and drain contact holes is directly formed mainly after the embedded epitaxial layer 5 is formed and after source and drain injection is carried out in the embedded epitaxial layer 5, and therefore the metal silicide 6 of the source and drain contact holes can be formed in a self-aligning mode on the whole outer side surface of the embedded epitaxial layer 5, the contact resistance of the source and drain contact holes of the device can be reduced after the coverage area of the metal silicide 6 is maximized, the on-resistance of the device can be reduced, and the performance of the device can be improved.
Embodiments of the invention can accommodate devices using process nodes below 14nm, such as 14HF devices including fin 2 processing and HKMG processing, where HK denotes a high dielectric constant layer and MG denotes a metal gate. In addition, the metal silicide 6 of the source and drain contact hole in the embodiment of the invention can realize better performance by adopting TiSi, the TiSi can obtain low source and drain contact resistivity and low process temperature by combining amorphous treatment ion implantation and high-dose source and drain implantation processes, and the resistivity and the process temperature can be well adapted to the process requirements of fin transistors, so that the performance of devices can be improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A fin-type transistor, comprising:
the fin body is formed by etching a semiconductor material of the semiconductor substrate;
the shallow trenches between the fin bodies are filled with field oxygen, and the top surfaces of the field oxygen are lower than the top surfaces of the fin bodies;
the part of the fin body protruding above the field oxygen is a fin body top structure;
a cell structure of a fin transistor is formed on the fin top structure, the cell structure comprising: a gate structure, a source region and a drain region;
the grid electrode structure covers the side face of the fin body top structure or the grid electrode structure covers the side face and the top surface of the fin body top structure;
grooves are formed in the fin body top structures on two sides of the grid structure, an embedded epitaxial layer is filled in the grooves, and the source region and the drain region are formed in the corresponding embedded epitaxial layer;
the metal silicide is formed on the whole outer side surface of the embedded epitaxial layer so as to increase the contact area of the source region or the drain region corresponding to the metal silicide, and the whole outer side surface of the embedded epitaxial layer comprises a side surface and a top surface;
the interlayer film covers the surface of the metal silicide and the surface of the grid structure;
forming a contact hole in the interlayer film through the interlayer film;
a source electrode, a drain electrode and a grid electrode which are composed of a front metal layer are formed on the surface of the interlayer film;
the metal silicide on the surface of the source region is contacted with the contact hole corresponding to the top and connected to the source electrode, the metal silicide on the surface of the drain region is contacted with the contact hole corresponding to the top and connected to the drain electrode, and the top of the polysilicon gate is connected to the gate electrode through the corresponding contact hole.
2. The fin-transistor of claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The fin-transistor of claim 2, wherein: the fin type transistor is an N type fin type transistor, and the embedded epitaxial layer is a SiP epitaxial layer.
4. The fin-transistor of claim 2, wherein: the fin type transistor is a P type fin type transistor, and the embedded epitaxial layer is a SiGe epitaxial layer.
5. The fin-transistor of claim 1, wherein: the metal silicide includes TiSi.
6. The fin-transistor of claim 1, wherein: the groove has a sigma-shaped structure.
7. The fin-transistor of claim 1, wherein: the process node of the fin transistor is below 14 nm.
8. The fin-transistor of claim 7, wherein: the grid structure comprises a grid dielectric layer and a metal grid which are sequentially overlapped, wherein the grid dielectric layer comprises a high dielectric constant layer.
9. A method for manufacturing a fin transistor comprises the following steps:
step one, providing a semiconductor substrate, and etching a semiconductor material of the semiconductor substrate to form a fin body;
filling field oxygen in the shallow trenches among the fin bodies, wherein the top surfaces of the field oxygen are lower than the top surfaces of the fin bodies; the part of the fin body protruding above the field oxygen is a fin body top structure;
forming a pseudo gate structure corresponding to a unit structure of the fin transistor on the fin body top structure;
fourthly, performing self-aligned etching on the fin body top structures on two sides of the pseudo gate structure to form a groove;
filling an embedded epitaxial layer in the groove;
sixthly, performing self-aligned source-drain injection to form a source region and a drain region in the embedded epitaxial layer on two sides of the pseudo gate structure;
seventhly, forming metal silicide in a self-alignment mode on the whole outer side surface of the embedded epitaxial layer where the source region and the drain region are formed so as to increase the contact area of the source region or the drain region corresponding to the metal silicide, wherein the whole outer side surface of the embedded epitaxial layer comprises a side surface and a top surface;
step eight, forming a zero-layer interlayer film, wherein the zero-layer interlayer film covers the surface of the metal silicide, and the top surface of the zero-layer interlayer film is flush with the top surface of the dummy gate structure;
removing the pseudo gate structure, and forming a gate structure in a removal region of the pseudo gate structure, wherein the gate structure comprises a gate dielectric layer and a metal gate which are sequentially overlapped, and the gate dielectric layer comprises a high dielectric constant layer;
tenth, forming a first interlayer film, wherein the first interlayer film covers the surfaces of the zero-layer interlayer film and the gate structure, and the zero-layer interlayer film and the first interlayer film are overlapped to form an integral interlayer film;
step eleven, forming a contact hole penetrating through the interlayer film;
twelfth, a back-end process is completed, wherein the back-end process comprises the step of forming a source electrode, a drain electrode and a grid electrode which are composed of a front metal layer on the surface of the interlayer film;
the metal silicide on the surface of the source region is contacted with the contact hole corresponding to the top and connected to the source electrode, the metal silicide on the surface of the drain region is contacted with the contact hole corresponding to the top and connected to the drain electrode, and the top of the polysilicon gate is connected to the gate electrode through the corresponding contact hole.
10. The method of manufacturing a fin-type transistor of claim 9, wherein: the semiconductor substrate is a silicon substrate.
11. The method of manufacturing a fin-type transistor of claim 10, wherein: the fin type transistor is an N type fin type transistor, and the embedded epitaxial layer is a SiP epitaxial layer; or the fin type transistor is a P-type fin type transistor, and the embedded epitaxial layer is a SiGe epitaxial layer.
12. The method of manufacturing a fin-type transistor of claim 9, wherein: the metal silicide includes TiSi.
13. The method of manufacturing a fin-type transistor of claim 9, wherein: the groove has a sigma-shaped structure.
14. The method of manufacturing a fin-type transistor of claim 9, wherein: the front metal layers comprise a plurality of layers, interlayer films of corresponding layers are isolated among the front metal layers, and the source electrode, the drain electrode and the grid electrode are formed by the front metal layer on the topmost layer.
15. The method of manufacturing a fin-type transistor of claim 9, wherein: the process node of the fin transistor is below 14 nm.
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| CN105826374A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | P type FinFET (Fin Field Effect Transistor) and formation method thereof |
| CN107464756A (en) * | 2016-06-03 | 2017-12-12 | 台湾积体电路制造股份有限公司 | Method for reducing the contact resistance in semiconductor fabrication process |
| CN109585553A (en) * | 2017-09-28 | 2019-04-05 | 台湾积体电路制造股份有限公司 | Fin field effect transistor device structure |
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| CN105826374A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | P type FinFET (Fin Field Effect Transistor) and formation method thereof |
| CN107464756A (en) * | 2016-06-03 | 2017-12-12 | 台湾积体电路制造股份有限公司 | Method for reducing the contact resistance in semiconductor fabrication process |
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