CN110851374A

CN110851374A - Pre-comparison system and pre-comparison method

Info

Publication number: CN110851374A
Application number: CN201810947713.7A
Authority: CN
Inventors: 赖乙婷; 江志和
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2018-08-20
Filing date: 2018-08-20
Publication date: 2020-02-28
Anticipated expiration: 2038-08-20
Also published as: CN110851374B

Abstract

A pre-alignment method comprises the following steps: receiving an initial address; gradually increasing a current address according to the initial address; adding an offset value to the current address to obtain a comparison address; comparing the comparison address with at least one defective address to generate a hit parameter; generating a redundant address related to the comparison address; and setting a Y-direction address as the current address or the redundant address according to the hit parameter, wherein the Y-direction address is related to the access of the memory array.

Description

Pre-comparison system and pre-comparison method

Technical Field

The invention relates to a pre-comparison system and a pre-comparison method. In particular, to a pre-compare system and a pre-compare method applied to a NAND flash memory.

Background

In recent years, NAND flash memories have been widely used due to the spread of mass data and nonvolatile data. In addition, the mass data makes NAND flash memory suitable for memory cards, Universal Serial Bus (USB) flash drives, and storage devices in mobile devices. To increase the advantages, flash memory cells are manufactured to be as small as possible by complicated device manufacturing processes, and chip yield is difficult to maintain without redundancy mechanisms and Error Correction Codes (ECC).

As technology and technology advance, processors are required to run more complex computations, which means that the processors require memory capacity and data throughput may increase dramatically. To meet this trend, a Double Data Rate (DDR) input/output interface is a popular choice for achieving high data transmission speed. However, for the address replacement method, it is almost impossible to access the memory data in a short access data time including internal data transfer time and row repair time (column repair time).

For the foregoing reasons, how to reduce the transmission time of the NAND memory has become one of the problems to be solved in the art.

Disclosure of Invention

An embodiment of the present invention provides a pre-alignment system, including: a memory array; an input/output circuit for receiving an initial address; an address counter coupled to the input/output circuit for gradually increasing a current address according to the initial address; an adder coupled to the address counter for adding an offset value to the current address to obtain a comparison address; a mapping table for storing at least one defect address; a mapping circuit, coupled to the mapping table and the adder, for comparing the comparison address with the at least one defect address stored in the mapping table to generate a hit parameter and a redundant address associated with the comparison address; a first register coupled to the mapping circuit for storing the hit parameter; a second register coupled to the mapping circuit for storing the redundant address; and a multiplexer, coupled to the first and second registers, for setting a Y-direction address as the current address or the redundant address according to the hit parameter stored in the first register, the Y-direction address being associated with access to the memory array.

Another embodiment of the present invention provides a pre-alignment method, including: receiving an initial address; gradually increasing a current address according to the initial address; adding an offset value to the current address to obtain a comparison address; comparing the comparison address with at least one defective address to generate a hit parameter; generating a redundant address related to the comparison address; and setting a Y-direction address as the current address or the redundant address according to the hit parameter, wherein the Y-direction address is related to access to a memory array.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:

drawings

Fig. 1 is a schematic diagram of a redundancy structure of a NAND flash memory according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram illustrating a pre-alignment method according to an embodiment of the disclosure.

Fig. 3 is a schematic diagram of a pre-alignment system according to an embodiment of the disclosure.

Fig. 4A-4B are flowcharts illustrating a Y-direction repair analysis method according to an embodiment of the disclosure.

FIG. 5 is a schematic diagram of an operation timing sequence applicable to the pre-alignment system of FIG. 3.

Fig. 6 is a schematic diagram of a pre-alignment system according to an embodiment of the present disclosure.

FIG. 7 is a diagram illustrating an operation timing sequence of the pre-alignment system of FIG. 6.

[ notation ] to show

100: redundancy structure of NAND flash memory

RA: redundant array

NA: normal array

NB: normal block

And NS: spare block

C1, C1': line of

And RS: redundant blocks

RB: redundant blocks

210-260: step (ii) of

300: pre-alignment system

PGB: page buffer area

RPR: redundant buffer

NCH: normal high speed memory

RCH: redundant high speed memory

XC: x-direction control signal

29: column control circuit

23: repair analysis circuit

FY: corresponding result

15: mapping circuit

16: mapping table

17: first buffer

HT, HT': hit parameter

RY and RY': redundant addresses

19: second buffer

PM: pre-alignment selection signal

11. 21: multi-way selector

25: address counter

YI: initial address

CA: current address

MA: comparing addresses

XA: x-direction address

SX: address signal

SY: address signal

YA: y-direction address

YC: y-direction control signal

IND, OTD: data signal

27: row control circuit

10: input/output circuit

401-415: step (ii) of

wt: waiting time

t1-t 4: time interval

TL: time axis accessor

CDFF, CIO: period of frequency

DTIO: data input/output

MEL: memory load signal

F1-F8: transistor with a metal gate electrode

65a to 65 d: mapping circuit

66a to 66 d: mapping table

67a to 67 d: hit flag register

69a to 69 d: redundant address buffer

600: pre-alignment system

74: row control circuit

51. 61, 7l, 81: function multiplexer

70: address multiplexer

75: address counter

53. 63, 73, 83: adder

MA0-MA 3: comparing addresses

i 1: time interval

CLC: period of frequency

Detailed Description

The technical terms in the specification refer to the common terms in the technical field, and if the specification explains or defines a part of the terms, the explanation of the part of the terms is subject to the explanation or definition in the specification. Various embodiments of the present disclosure may have one or more technical features. In the present invention, the present invention provides a method for implementing a mobile communication system, which is capable of providing a mobile communication system with a plurality of mobile communication devices.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a redundancy structure 100 of a NAND flash memory according to an embodiment of the present invention. The redundancy structure 100 of the NAND flash memory includes a normal array (normal array) NA and a redundant array (redundancy array) RA. The normal array NA may be used to store normal data and the redundant array RA may be used to store redundant data. The normal array NA includes one or more normal blocks NB and one or more spare blocks NS, and the redundant array RA includes one or more redundant blocks RB and one or more spare redundant blocks RS. In one embodiment, the redundancy function is composed of a normal block NB, a spare block NS, a redundancy block RB, and a spare redundancy block RS. The redundancy functions include X-direction redundancy and Y-direction redundancy. The X-direction redundancy is composed of a spare block NS and a spare redundancy block RS, and the spare block NS and the spare redundancy block RS can be used to replace the bad blocks in the normal block NB and the redundancy block RB, respectively. In addition, the redundant array RA is used as a Y-direction redundancy, and includes spare columns (columns) that can be used to replace bad columns (badcolumns) in the normal array NA.

For example, column C1 is a Y-direction spare column of the redundancy array RA, and column C1 may be used in place of column C1 ' when column C1 ' includes a defect (i.e., column C1 ' is defective).

It should be noted that the pre-compare system and the pre-compare method of the embodiment of the invention are not limited to the redundancy structure 100 of the NAND flash memory. The pre-comparison system and the pre-comparison method of the embodiment of the invention can be applied to other circuits, improve the data access time and track the transmission speed of an interface (such as a DDR interface). The pre-alignment system and the pre-alignment method are further described below. For ease of understanding, the following embodiments take redundancy structure 100 of a NAND flash memory as an example.

Referring to fig. 2 to 3, fig. 2 is a schematic diagram illustrating a pre-comparison method according to an embodiment of the disclosure. Fig. 3 is a schematic diagram of a pre-alignment system 300 according to an embodiment of the disclosure. In one embodiment, the pre-compare system 300 comprises a memory array 10, an input/output circuit 10, an address counter 25, an adder 13, a mapping circuit (mapping circuit)15, a mapping table 16, a first register 17, a second register 19, and a multiplexer 21. In one embodiment, the memory array 10 includes a normal array NA, a redundant array RA, a page buffer PGB, a normal high speed NCH, a redundant buffer RPR, and a redundant high speed RCH. In one embodiment, the first register 17 and the second register 19 may be implemented by D flip-flops (DFFs), respectively. In one embodiment, the mapping table 16 may be any circuit element capable of storing data. For example, the mapping table 16 may be implemented by a Content Addressable Memory (CAM) circuit. Wherein mapping circuit 15 has access to mapping table 16.

It should be noted that the embodiments of the present invention are not limited to the implementation of the first register 17 and the second register 19 by using D flip-flops. Other embodiments of the present invention may employ other types of registers having the same function. For example, register 17 or 19 may be a latch, a capacitor, a memory cell, or any other circuit element capable of storing data. For convenience of description, the embodiment takes D flip-flops as the first register 17 and the second register 19 for illustration.

In step 210, the input/output circuit 10 receives an initial address. In one embodiment, the input/output circuit 10 receives a request instruction and calculates the initial address YI to be accessed according to the request instruction. For example, when a request instruction needs to access data of "addr [5 ]" to "addr [9 ]" in the normal array NA, the input-output circuit 10 obtains the initial address YI as "addr [5 ]". In the following, the first to fourth addresses represent the access sequence of the requested instruction. For example, for a request instruction to access "addr [5 ]" to "addr [40 ]", the first address is "addr [5 ]", the second address is "addr [6 ]", the third address is "addr [7 ]", and so on.

In step 220, the address counter 25 gradually increases the current address CA according to the initial address YI. In one embodiment, the address counter 25 sets the initial value of the current address CA to the initial address YI, and increments the current address CA by 1 every cycle. For example, in a first cycle, the current address CA equals the first address, in a second cycle, the current address CA equals the second address, in a third cycle, the current address CA equals the third address, and so on. The address counter 25 provides the current address CA to the adder 13 and the multiplexer 21.

In step 230, adder 13 adds offset value OV to current address CA to generate match address MA. In one embodiment, the offset value OV is 1. That is, in a sequential memory access operation, the compare address MA may represent the next address to be accessed. For example, adder 13 may add 1 to current address CA (current address CA equals first address "addr [5 ]") to generate match address MA (equals second address "addr [6 ]"). The invention is not so limited. The offset value OV may be set to different integer values, as will be described in other embodiments.

In one embodiment, the pre-alignment system 300 further comprises a function multiplexer 11 for providing the offset value OV. In FIG. 3, the functional multiplexer 11 receives two

integers

1 and 0 as inputs and receives the pre-compare selection signal PM as a selection signal. In an embodiment of the present invention, when the pre-comparison function is enabled, the pre-comparison selection signal PM is set to a logic high level, otherwise, the pre-comparison selection signal PM is set to a logic low level.

In step 240, the mapping circuit 15 compares the comparison address MA with at least one defect address in the mapping table 16 to generate a hit parameter HT.

In step 250, mapping circuit 15 generates redundancy address RY associated with match address MA.

In one embodiment, the comparing system 300 further comprises a repair analyzing circuit 23 for determining a defect status in the memory array 20, thereby generating the mapping table 16. Therefore, the mapping table 16 records at least one defect address. The defective address represents an address of a defective memory cell in the memory array 20.

Referring to fig. 4A to 4B, fig. 4A to 4B are flowcharts illustrating a Y-direction repair analysis method according to an embodiment of the disclosure. In one embodiment, the Y-direction repair analysis method can find and repair defective rows (defectcolumns) in the memory array 20. It should be noted that the present invention is not limited to the Y-direction repair analysis method. The Y-direction repair analysis method is used herein to provide an example for finding and repairing defects of the NAND flash memory.

In step 401, the mapping circuit 15 performs a global defect scan (global defect screen) to find a defective row. For example, rows (e.g., rows C1 and C1' in FIG. 1) refer to, for example, a plurality of memory cells in an array (e.g., normal array NA and redundant array RA in FIG. 3), sets of sense circuits disposed in a page buffer system (e.g., page buffer PGB and redundant buffer RPR in FIG. 3), and high speed memory in a high speed system (e.g., high speed memory NCH and redundant high speed memory RCH in FIG. 3). The plurality of rows constitute one memory macro. The sensing circuit can be used to identify data in the memory cell. The data read by the sensing circuit can be sent to the high speed memory. The high speed memory temporarily stores the read data until the input/output circuit 10 reads the data. Global defect scanning can confirm the defect status by scanning the flash memory cells, the sensing circuits and the high-speed circuits in each row.

In step 402, the repair analysis circuit 23 determines whether the currently detected region (area) contains a defect. If the current detection area contains defects, go to step 403, otherwise, go to step 405. In step 403, the mapping circuit 15 determines whether the Y-direction redundancy is over (overflow). If the mapping circuit 15 determines that there is a Y-direction redundancy overflow, it indicates that there is no residual redundancy repairable global defect in the Y-direction (e.g., the Y-direction redundancy space is exhausted), so if step 403 is true, step 415 is entered. If the mapping circuit 15 determines that the Y-direction redundancy does not overflow, step 404 is entered.

In step 415, the repair analysis circuit 23 discards the NAND flash memory because the NAND flash memory contains too many defects. Conversely, if the Y-direction redundancy does not overflow, the repair analysis circuit 23 repairs the global defect through the Y-direction redundancy in step 404. In step 405, the repair analysis circuit 23 determines whether the current detected pattern (pattern) is the last circuit pattern, if the repair analysis circuit 23 determines that the current detected pattern is the last circuit pattern, step 407 is performed, otherwise, step 406 is performed. In step 406, the repair analysis circuit 23 detects the next circuit pattern.

In step 407, the repair analysis circuit 23 performs a local defect scan (local defect scan). This represents the repair analysis circuit 23 finding the defect of the current detection block. In step 408, if any defect is detected in the current detection block, step 409 is entered, otherwise, step 411 is entered. In step 409, the repair analysis circuit 23 determines whether the Y-direction redundancy is an overflow (overflow) value. If in step 409 mapping circuit 15 determines that a Y-direction redundancy overflow value indicates that there is no Y-direction redundancy available to repair the local defect (e.g., the Y-direction redundancy space is exhausted), then step 415 is entered. If in step 409 the repair analysis circuit 23 determines that the Y-direction redundancy does not overflow, then step 410 is entered. In step 410, the repair analysis circuit 23 repairs the local defect using the remaining redundancy in the Y direction. In step 411, the repair analysis circuit 23 determines whether the current detected pattern is the last circuit pattern, if the repair analysis circuit 23 determines that the current detected pattern is the last circuit pattern, step 412 is entered, otherwise, step 413 is entered. In step 413, the repair analysis circuit 23 detects the next circuit pattern. In step 412, the mapping circuit 15 determines whether the current detected block is the last block. If the mapping circuit 15 determines that the current detection block is not the last block, step 414 is performed to determine the next block, and if not, the Y-direction repair analysis method is ended.

In the Y-direction repair analysis method of the present embodiment, both global defects and local defects can be scanned. When a defect is found, the repair analysis circuit 23 first determines whether the Y-direction redundancy is sufficient to repair the defect. If the Y-direction redundancy is sufficient to repair the defect, the row address where the defect is located is written into the mapping table 16 and mapped to the redundant address RY for performing the repair function, so as to replace the row position having the defect with the redundant address RY. In addition, other embodiments of the present disclosure may apply known algorithms to repair NAND flash memory.

The repair analyzing circuit 23 transfers the corresponding result FY to the mapping table 16. The mapping circuit 15 compares the comparison address MA with at least one defect address in the mapping table 16 to generate a hit parameter ht (hit parameter). If at least one of the defective addresses is identical to the matching address MA, the hit parameter HT is set to a logic high level, otherwise, the hit parameter HT is set to a logic low level. In addition, mapping circuit 15 finds redundant address RY associated with compare address MA.

The mapping circuit 15 transmits the hit parameter HT to the first register 17 and transmits the redundant address RY to the second register 19. The first register 17 temporarily stores the hit parameter HT. In one embodiment, the second register 19 stores the redundant address RY (e.g. address r [0] "in the redundant array RA) corresponding to the comparison address MA temporarily, when the comparison address MA is recorded as an error location in the mapping table 16, i.e. the comparison address MA is marked as a defective address in the mapping table 16, the redundant address RY is used to replace the comparison address MA. In one embodiment, the first register 17 and the second register 19 may be D flip-flops. The register hit HT 'output by the first register 17 is the delay of the hit HT, and the redundant address RY' output by the second register 19 is the delay of the redundant address RY.

In step 260, the multiplexer 21 sets the Y-direction address YA as the redundancy address RY 'or the current address CA according to the hit parameter HT', and transmits the output address (Y-direction address YA) to the column control circuit 27. When the hit parameter HT ' is logically high, the Y-direction address YA is set as the redundant address RY ', and when the hit parameter HT ' is logically low, the Y-direction address YA is set as the current address CA.

In one embodiment, when the hit parameter HT' (as the determination signal) is set to a logic low level, the multiplexer 21 transmits the current address CA to the column control circuit 27, and the column control circuit 27 triggers the normal columns in the normal array NA by the Y-direction control signal YC to output the data corresponding to the Y-direction address YA. On the other hand, when the hit parameter HT 'is at a logic high level, the multiplexer 21 sends the redundancy address RY' to the column control circuit 27 for outputting the repair data of the redundancy array RA in FIG. 3. The signals SX and SY are address signals that are available for accessing the memory during the repair analysis (i.e., the signals SX and SY are not available for accessing the memory during normal operation). In one embodiment, the Y-direction repair unit may be a word (word) or a byte (byte) or even a bit (bit).

In some embodiments, the row control circuit 29 can also be used to trigger the memory array to output the correct data in the X direction corresponding to the output address by the X direction control signal XC. The pre-alignment system and the pre-alignment method can also be realized by replacing the defective row data (defect row data) with the redundant row data (redundancy row data) in the X direction.

In one embodiment, when the Y-direction address YA is set as the redundancy address RY', the data (e.g., correct data) corresponding to the Y-direction address YA is written into the redundancy buffer RPR, and the data is outputted from the redundancy cache RCH. Once the redundant address is accessed, the redundant high speed memory RCH can take data from the data signal IND of the input-output circuit 10 and send the output data to the input-output circuit 10 by the data signal OTD.

In one embodiment, when the Y-direction address YA is set as the current address CA (address for accessing the normal array NA), the data (e.g., correct data) corresponding to the Y-direction address YA is written into a page buffer PGB, and the data is outputted from the normal cache NCH. When the normal high-speed memory NCH is accessed, the normal high-speed memory NCH may receive data from the input-output circuit 10 by the data signal IND and output the data to the input-output circuit 10 by the data signal OTD.

Referring to fig. 3 and 5, fig. 5 is a schematic diagram of an operation timing sequence of the pre-alignment system 300 applied to fig. 3. In one embodiment, the time axis TL sequentially includes a waiting time, a time interval t1, a time interval t2, a time interval t3, a time interval t4, and the like. The period of each time interval t1-t4 is the same as the frequency period CIO of the input-output circuit 10 and the period CDFF of the D flip-flop. The period CDFF of the D flip-flop is used to control the timing of the receiving and transmitting data of the first register 17 and the second register 19. Thus, the first register 17 and the second register 19 can operate synchronously. In one embodiment, the pre-alignment system 300 may employ DDR interface to output two bytes (e.g., high byte and low byte) in one cycle, as in data input/output DTIO

FIG. 5 shows a timing diagram of the operation of the pre-alignment method assuming that the alignment address MA needs to be repaired. In one embodiment, the address counter 25 sends the current address CA to the adder 13. Since the pre-compare select signal PM is still logic low during the waiting time wt, the adder 3 directly bypasses (bypass) the current address CA to become the Y-direction address YA. Since it is assumed that the first address is not recorded in the mapping table 16, the hit parameter HT is logic low, since the mapping circuit 15 determines that the matching address MA is not identical to any defect address recorded in the mapping table 16. Therefore, in the time interval t1, the hit parameter HT' is logic low (since the hit parameter HT was logic low in the previous time interval wt), and the Y-direction address YA will be the same as the current address CA. On the other hand, the pre-alignment selection signal PM transitions to a logic high level at the beginning of the time interval t 1. Therefore, adder 13 adds 1 to current address CA to generate compare address MA, and provides compare address MA to mapping circuit 15. Then, at a first time interval t1, the mapping circuit 15 compares the comparison address MA with at least one defect address in the mapping table 16. In this assumption, the match address MA matches at least one defective address in the mapping table 16, such that the hit parameter HT stored in the first register 17 changes to a logic high level, and the redundant address RY is temporarily stored in the second register 19. In the next clock cycle, the hit parameter HT 'and the redundant address RY' are transmitted to the multiplexer 21 at the same time as the beginning of the second time interval t 2. Then, in the second time interval t2, the data stored in the redundant address RY' is outputted (this can be represented by the Y-direction address YA in the second time interval t 2).

Thus, when the current address CA (original address) points to the wrong column, the Y-direction address YA is switched to the corresponding redundant address RY'; otherwise, the Y-direction address YA corresponds to the current address CA. Since, in this example, as assumed, the third address and the fourth address are not recorded in the mapping table 16, the pre-alignment system 300 can set the set Y-direction address YA as the current address CA in the third time interval t3 and the fourth time interval t 4.

Referring to fig. 6, fig. 6 is a schematic diagram of a pre-alignment system 600 according to an embodiment of the present disclosure. In one embodiment, if the pre-alignment time is longer than the output cycle time, the pre-alignment system 600 (including the

functional multiplexers

51, 61, 71, 81, the address counter 75, the address multiplexer 70, the row control circuit 74 and the

adders

53, 63, 73, 83) in FIG. 6 can replace the pre-alignment system 300 (including the functional multiplexer 11, the address counter 25, the multiplexer 21, the row control circuit 27 and the adder 13) in FIG. 3. The

functional multiplexers

51, 61, 71 and 81 provide different offset values to the

adders

53, 63, 73 and 83. For example, based on the pre-alignment selection signal PM, the functional multiplexer 51 sets the offset value to 0 or 4, the functional multiplexer 61 sets the offset value to 1 or 5, the functional multiplexer 71 sets the offset value to 2 or 6, and the functional multiplexer 81 sets the offset value to 3 or 7.

FIG. 6 is different from FIG. 3 in that the pre-matching system 600 in FIG. 6 divides the mapping table 16 into four partial mapping tables 66 a-66 d. The number of mapping tables 16 may be adjusted as needed. The pre-alignment system 600 includes four mapping circuits 65 a-65 d for accessing corresponding mapping tables 66 a-66 d. Taking FIG. 6 as an example, the mapping table 16 of FIG. 3 is divided into four partial mapping tables 66 a-66 d. On the other hand, the defective addresses are sorted and stored in different sub-mapping tables 66a to 66d according to the corresponding defective addresses. In this case, the defect address is a multiple of 4 (which can also be expressed as 4n, where n is an integer) and is stored in the mapping table 65 a; the defect address is 4n +1, which is stored in the mapping table 65 b; the defect address is 4n +2, which is stored in the mapping table 65 c; and the defect address is 4n +3, which is stored in the mapping table 65 d.

In one embodiment, each mapping circuit 65 a-65 d corresponds to two registers, namely, the hit flag registers 67 a-67 d and the redundant address registers 69 a-69 d. For example, mapping circuit 65a is coupled to hit flag register 67a and redundant address register 69 a. The hit flag registers 67 a-67 d function and operate in the same manner as the first register 17 shown in FIG. 3, and the redundant address registers 69 a-69 d function and operate in the same manner as the second register 19 shown in FIG. 3. The registers 67a to 67d are connected in series, and the registers 69a to 69d are connected in series. For example, the data output of register 69b (i.e., the Q port of the D flip-flop) is coupled to the data input of register 69a (i.e., the D port of the D flip-flop), and so on. When the memory load (memory load) signal MEL is at a logic high level, the hit flag registers 67a 67d and the redundant address registers 69a 69d are connected to the corresponding mapping circuits 65a 65d through the transistors F1F 8. Transistors F1-F8 are coupled between buffers 69 a-69 d and mapping circuits 65 a-65 d, respectively. Transistors F1-F8 are controlled by memory load signal MEL.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating an operation timing sequence of the pre-alignment system of fig. 6, wherein it is assumed that the second address needs to be repaired. In one embodiment, the pre-alignment system 600 of FIG. 6 uses a DDR architecture. However, the invention is not limited to use with DDR architectures, for example, other embodiments of the invention may employ Single Data Rate (SDR).

During the waiting time wt, the pre-compare selection signal PM is set to a logic low level. Accordingly, the comparison addresses MA0-MA3 represent the first 4 addresses, and the current address CA is the initial address (which is the first address). The mapping circuits 65a to 65d simultaneously compare the comparison addresses MA0 to MA3 with the defect addresses in the mapping tables 66a to 66 d. The comparison time can be extended to 4 times the CLC cycles with parallel processing by the mapping circuits 65 a-65 d.

In the last cycle of the waiting time wt, the memory load signal MEL has a high level for half cycle to transmit the redundant address and the hit flag to the redundant address registers 69 a-69 d and the hit flag registers 67 a-67 d. Since it is assumed that only the second address is defective, when the memory load signal MEL is high, only the hit flag register 67b is logic high, and the other

hit flag registers

67a, 67c and 67d are logic low. In addition, a redundant address related to the second address is also buffered in the redundant address buffer 69 b.

After the first four redundant addresses and the hit flags in the mapping circuits 65 a-65 d are respectively transmitted to the redundant address registers 69 a-69 d and the hit flag registers 67 a-67 d, the pre-compare selection signal PM is pulled high in the fifth clock cycle CLC when the memory loading signal MEL is pulled high. First time interval i1 includes fifth through eighth frequency cycles CLC. In one embodiment, each time interval (e.g., time interval i1) includes four clock cycles CLC. In time interval i1, when the pre-compare selection signal PM is high, 4, 5, 6 and 7 are added to the current address CA (the current address CA is still the initial address (the first address) in the fifth clock cycle) to generate the compare addresses MA0-MA 3. Accordingly, the mapping circuits 65a to 65d obtain the next 4 addresses (i.e., the fifth to eighth addresses) for performing the pre-compare function.

In one embodiment, the following events are performed for each clock cycle CLC beginning with the fifth clock cycle CLC: the data stored in the redundant address register 69b is moved to the redundant address register 69a (e.g., the data stored in the redundant address register 69b overwrites the data stored in the original redundant address register 69 a), the data stored in the redundant address register 69c is moved to the redundant address register 69b, and the data stored in the redundant address register 69d is moved to the redundant address register 69 c.

The hit flag HT received from the hit flag register 67a during the fifth cycle is logic low because the first address does not need to be repaired. Because, the address multiplexer 70 transfers the current address CA to the row control circuit 74 to output data regarding the first address. In the sixth clock cycle CLC, since the second address contains defects, in the fifth clock cycle CLC, the hit flag of the second address that has been transferred from the hit flag register 67b to the hit flag register 67a is sent from the hit flag register 67a as the hit parameter HT (i.e., the hit parameter HT is overwritten by the hit flag in the hit flag register 67 b), and the corresponding redundant address of the second address that has been transferred from the redundant address register 69b to the redundant address register 69a is sent from the redundant address register 69a as the redundant address RY (i.e., the redundant address RY is overwritten by the redundant address in the redundant address register 69 b). The hit flags stored in the hit flag registers 67b 67d are shifted to the right hit flag registers 67a 67c, respectively, and the redundant addresses stored in the redundant address registers 69b 69d are shifted to the right redundant address registers 69a 69c, respectively. Since the third address and the fourth address are not recorded in the mapping tables 66c and 66d in this example, the pre-alignment system 600 outputs the current address CA in the third time interval t3 and the fourth time interval t 4.

It should be noted that the present disclosure is not limited to the use of four mapping tables. Other possible embodiments of the present disclosure may use any number of mapping tables. Therefore, the pre-alignment system can simultaneously check whether there is a defective address by comparing the tables 66 a-66 d with a plurality of parts, thereby reducing the calculation time. In addition, since each of the partial comparison tables 66a to 66d has a smaller data size than the original comparison table, the mapping circuits 65a to 65d can complete the comparison process more quickly.

Based on the above description and the detailed description of the embodiments, the pre-compare system and the pre-compare method can find out whether the next read address needs to be repaired. In the case of sequential access, the next read address can be easily prealigned out because the subsequent addresses increase linearly. In addition, the next read address is transferred to the mapping table (which contains all the defective addresses) to determine whether the next read address has a defect. If the next read address matches one of the defect addresses recorded in the mapping table, the mapping circuit obtains the row or column redundant address corresponding to the next read address in advance, and directly outputs the data of the relevant redundant row or column address in the next period. Therefore, the data access time of the NAND flash memory can be shortened, and the transmission speed of a DDR or SDR interface is effectively supported.

In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims

1. A pre-alignment system, comprising:

a memory array;

an input/output circuit for receiving an initial address;

an address counter coupled to the input/output circuit for gradually increasing a current address according to the initial address;

an adder coupled to the address counter for adding an offset value to the current address to obtain a comparison address;

a mapping table for storing at least one defect address;

a mapping circuit, coupled to the mapping table and the adder, for comparing the comparison address with the at least one defect address stored in the mapping table to generate a hit parameter and a redundant address associated with the comparison address;

a first register coupled to the mapping circuit for storing the hit parameter;

a second register coupled to the mapping circuit for storing the redundant address; and

a multiplexer coupled to the first and second registers for setting a Y-direction address as the current address or the redundant address according to the hit parameter stored in the first register, the Y-direction address being associated with access to the memory array.

2. The pre-alignment system of claim 1, further comprising:

a column control circuit coupled to the multiplexer for receiving the Y-direction address and triggering the memory array to output data associated with the Y-direction address;

a repair analysis circuit for checking a defect state in the memory array to generate the mapping table; and

a function multiplexer, coupled to the adder, for setting the offset value to a first integer or a second integer in response to a pre-compare select signal, wherein the pre-compare select signal is logic high if a pre-compare function is enabled.

3. The pre-alignment system of claim 1,

the mapping circuit is used for: setting the hit parameter to logic high if the compared address matches the at least one defective address stored in the mapping table; if the match address does not match any of the at least one defective address stored in the mapping table, setting the hit parameter to logic low;

the multiplexer is used for: when the hit parameter is logic high, setting the Y-direction address as the redundant address; and setting the Y-direction address as the current address when the hit parameter is logic low.

4. The pre-alignment system of claim 1,

the memory array comprises a redundant buffer area and a redundant high-speed memory, when the Y-direction address is set as the redundant address, data related to the Y-direction address is written into the redundant buffer area and is output by the redundant high-speed memory; and

the memory array comprises a page buffer area and a normal high-speed memory, and when the Y-direction address is set as the current address, data related to the Y-direction address is written into the page buffer area and output by the normal high-speed memory.

5. The pre-alignment system of claim 1, further comprising:

a lower adder for adding a lower offset value to the current address to generate a lower comparison address, wherein the lower offset value is different from the offset value;

a lower mapping table for storing at least one lower defect address;

a lower mapping circuit for comparing the lower comparison address with the at least one lower defect address stored in the lower mapping table to generate a lower hit parameter and a lower redundant address associated with the lower comparison address;

a lower level first buffer for storing the lower level hit parameter, wherein a data output terminal of the lower level first buffer is coupled to a data input terminal of the first buffer;

a lower level second register for storing the lower level redundant address, wherein a data output terminal of the lower level second register is coupled to a data input terminal of the second register;

a first transistor coupled between the first buffer and the mapping circuit; and

a second transistor coupled between the second register and the mapping circuit;

wherein the first and second transistors are controlled by a memory load signal.

6. A pre-comparison method of a pre-comparison system, the pre-comparison system comprising a memory array, the pre-comparison method comprising:

receiving an initial address;

gradually increasing a current address according to the initial address;

adding an offset value to the current address to obtain a comparison address;

comparing the comparison address with at least one defective address to generate a hit parameter;

generating a redundant address related to the comparison address; and

setting a Y-direction address as the current address or the redundant address according to the hit parameter, wherein the Y-direction address is related to the access of the memory array.

7. The method of claim 6, further comprising:

triggering the memory array to output data associated with the Y-direction address;

checking a defect state in the memory array to generate a mapping table, wherein the mapping table is used for storing the at least one defect address; and

the offset value is set to be a first integer or a second integer in response to a pre-compare select signal, wherein the pre-compare select signal is logic high if a pre-compare function is enabled.

8. The method of pre-alignment of claim 6, wherein,

generating the hit parameter includes: setting the hit parameter to logic high if the compared address matches the at least one defective address; if the compared address does not match any of the at least one defective address, setting the hit parameter to logic low; and

setting the Y-direction address includes: when the hit parameter is logic high, setting the Y-direction address as the redundant address; and setting the Y-direction address as the current address when the hit parameter is logic low.

9. The method of pre-alignment of claim 6, wherein,

10. The method of claim 6, further comprising:

adding a next offset value to the current address to generate a next comparison address, wherein the next offset value is different from the offset value;

comparing the lower comparison address with at least one lower defect address stored in a lower mapping table to generate a lower hit parameter;

generating a lower redundant address related to the lower comparison address;

overwriting the hit parameter with the next hit parameter; and

the redundant address is overwritten with the lower redundant address.