TWI676175B - Pre-match system and pre-match method - Google Patents

Abstract

A pre-comparison method includes: receiving an initial address; gradually increasing a current address according to the initial address; adding a deviation value to the current address to obtain a comparison address; comparing the comparison address And at least one defective address to generate a hit parameter; generate a redundant address related to the comparison address; and set a Y-direction address as the current address or the redundant address according to the hit parameter The Y-direction address is related to access to the memory array.

Description

Pre-comparison system and pre-comparison method

This case is about a pre-comparison system and pre-comparison method. In particular, it relates to a pre-comparison system and pre-comparison method applied to NAND flash memory.

In recent years, due to the popularity of huge amounts of data and non-volatile data, NAND flash memory has been widely used. In addition, the huge amount of data makes NAND flash memory suitable for memory cards, universal serial bus (USB) flash drives, and storage devices in mobile devices. In order to expand the advantages, when manufacturing flash memory cells, they are made as small as possible through complex equipment production processes. Without redundant mechanisms and Error Correction Codes (ECCs), it will be difficult to maintain wafer yield.

With the advancement of technology and technology, processors are required to be able to run more complex calculations, which means that processors need memory capacity and data throughput may increase dramatically. To keep up with this trend, the Double Data Rate (DDR) input / output interface is a popular choice to achieve high data transmission speeds. However, for the address replacement method, it is almost impossible to access the data within a short access time. The short access time includes the internal data transmission time and the column repair time.

Based on the foregoing reasons, how to reduce the transmission time of NAND memory has become one of the urgent problems to be solved in the industry.

An embodiment of the present invention provides a pre-comparison system, which includes: a memory array; an input-output circuit for receiving an initial address; a bit counter coupled to the input-output circuit for using the initial bit The address is gradually increased by a current address; an adder is coupled to the address counter to add an offset value to the current address to obtain a comparative address; a mapping table is used to store at least one defect An address; a mapping circuit coupled to the mapping table and the adder, for comparing the comparison address with the at least one defect address stored in the mapping table to generate a hit parameter and generating a correlation parameter A redundant address of the comparison address; a first register coupled to the mapping circuit to store the hit parameter; a second register coupled to the mapping circuit to store the redundancy An address; and a multiplexer coupled to the first and second registers to set a Y-direction address to the current address or the current address according to the hit parameter stored in the first register The redundant address, the Y-direction address is related to The array of memory access.

Another embodiment of the present invention provides a pre-comparison method, which includes: receiving an initial address; gradually increasing a current address according to the initial address; adding a deviation value to the current address to obtain a comparison position Compare the comparison address with at least one defective address to generate a hit parameter; generate a redundant address related to the comparison address; and set a Y-direction address as the current according to the hit parameter Address or the redundant address, the Y-direction address is related to access to a memory array.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

Redundant structure of 100‧‧‧NAND flash memory

RA‧‧‧Redundant Array

NA‧‧‧Normal array

NB‧‧‧Normal block

NS‧‧‧spare block

Line C1, C1’‧‧‧‧

RS‧‧‧Redundant block

RB‧‧‧Redundant block

210 ~ 260‧‧‧step

300‧‧‧ pre-comparison system

PGB‧‧‧Page Buffer

RPR‧‧‧Redundant buffer

NCH‧‧‧Normal cache memory

RCH‧‧‧Redundant cache memory

XC‧‧‧X direction control signal

29‧‧‧column control circuit

23‧‧‧ Repair analysis circuit

FY‧‧‧ corresponding result

15‧‧‧ mapping circuit

16‧‧‧ mapping table

17‧‧‧The first register

HT, HT’‧‧‧ hit parameters

RY, RY’‧‧‧ redundant address

19‧‧‧Second register

PM‧‧‧ Pre-comparison selection signal

11, 21‧‧‧ Multiplexer

25‧‧‧Address Counter

YI‧‧‧ initial address

CA‧‧‧ Current address

MA‧‧‧ Compare Address

XA‧‧‧X direction address

SX‧‧‧ address signal

SY‧‧‧ address signal

YA‧‧‧Y direction address

YC‧‧‧Y direction control signal

IND, OTD‧‧‧ Data Signal

27‧‧‧line control circuit

10‧‧‧I / O circuit

401-415‧‧‧step

wt‧‧‧waiting time

t1 ~ t4‧‧‧Time interval

TL‧‧‧Timeline

CDFF, CIO‧‧‧clock cycle

DTIO‧‧‧Data output / input

MEL‧‧‧Memory Load Signal

F1 ~ F8‧‧‧Transistors

65a ~ 65d‧‧‧Map circuit

66a ~ 66d‧‧‧ Mapping Table

67a ~ 67d‧‧‧hit flag register

69a ~ 69d‧‧‧ redundant address register

600‧‧‧ pre-comparison system

74‧‧‧line control circuit

51, 61, 71, 81‧‧‧ Function Multiplexer

70‧‧‧Address Multiplexer

75‧‧‧ address counter

53, 63, 73, 83‧‧‧ Adders

MA0-MA3‧‧‧Comparison address

i1‧‧‧ time interval

CLC‧‧‧Clock cycle

FIG. 1 is a schematic diagram of a redundant structure of a NAND flash memory according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a pre-comparison method according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a pre-comparison system according to an embodiment of the present invention.

4A to 4B are flowcharts of a method for repairing the Y direction according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of the operation timing of the pre-comparison system applicable to FIG. 3.

FIG. 6 is a schematic diagram of a pre-comparison system according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of the operation timing of the pre-comparison system of FIG. 6.

The technical terms in this specification refer to the customary terms in the technical field. If some terms are described or defined in this specification, the interpretation of these terms is subject to the description or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those with ordinary knowledge in the technical field may selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.

Please refer to FIG. 1. FIG. 1 is a drawing according to an embodiment of the present case. Schematic diagram of a redundant structure 100 of a NAND flash memory. The redundant structure 100 of the NAND flash memory includes a normal array NA and a redundancy array RA. The normal array NA can be used to store normal data, and the redundant array RA can be used to store redundant data. The normal array NA includes one or more normal blocks NB and one or more spare blocks NS, and the redundant array RA includes one or more redundant blocks RB and one or more spare redundant blocks RS. In one embodiment, the redundancy function is composed of a normal block NB, a spare block NS, a redundant block RB, and a spare redundant block RS. Redundancy functions include X-direction redundancy and Y-direction redundancy. The X-direction redundancy is composed of the spare block NS and the spare redundant block RS, and the spare block NS and the spare redundant block RS can be used to replace the damage in the normal block NB and the redundant block RB, respectively Block. In addition, the redundant array RA is used as the Y-direction redundancy. The redundant array RA includes some spare columns that can be used to replace bad columns in the normal array NA.

For example, the row C1 is a spare row in the Y direction of the redundant array RA, and when the row C1 'contains defects (that is, the row C1' is damaged), the row C1 can be used instead of the row C1 '.

It should be noted that the pre-comparison system and the pre-comparison method in the embodiments of the present invention are not limited to the redundant structure 100 of the NAND flash memory. The pre-comparison system and the pre-comparison method of the embodiments of the present invention can be applied to other circuits to improve the data access time so as to be in line with the transmission speed of an interface (such as a DDR interface). The pre-comparison system and the pre-comparison method are further described below. In order to make the description easier to understand, the following embodiments take the redundant structure 100 of the NAND flash memory as an example for illustration.

Please refer to Figs. 2 to 3, and Fig. 2 is a drawing according to an embodiment of the present case. Schematic of the pre-comparison method. FIG. 3 is a schematic diagram of a pre-comparison system 300 according to an embodiment of the present invention. In one embodiment, the pre-comparison system 300 includes a memory array 20, an input-output circuit 10, a bit address counter 25, an adder 13, a mapping circuit 15, a mapping table 16, and The first register 17, a second register 19, and a multiplexer 21. In one embodiment, the memory array 20 includes a normal array NA, a redundant array RA, a page buffer PGB, a normal cache NCH, a redundant buffer RPR, and a redundant cache RCH. In an embodiment, the first register 17 and the second register 19 may be implemented by D flip-flop (DFF), respectively. In one embodiment, the mapping table 16 may be any circuit element capable of storing data. For example, the mapping table 16 may be implemented by a content addressable memory (CAM) circuit. The mapping circuit 15 can access the mapping table 16.

It should be noted that the embodiment of the present invention is not limited to adopting a D-type flip-flop to realize the first register 17 and the second register 19. Other embodiments of the present invention may use other types of registers with the same function. For example, the register 17 or 19 may be a latch, a capacitor, a memory unit, or any other circuit element that can store data. In order to facilitate the description, the embodiment of the present invention uses the D-type flip-flop as the first register 17 and the second register 19 as an example for description.

In step 210, the input-output circuit 10 receives an initial address. In an embodiment, the input-output circuit 10 receives a request instruction and calculates an initial address YI to be accessed according to the request instruction. For example, when the request instruction needs to access the data of “addr [5]” to “addr [9]” in the normal array NA, the input-output circuit 10 obtains the initial address YI as “addr [5]”. Underneath, the first to fourth addresses represent the request instruction Access order. For example, for a request instruction to access "addr [5]" to "addr [40]", the first address is "addr [5]", the second address is "addr [6]", and the third address "Addr [7]" and so on.

In step 220, the address counter 25 gradually increases the current address CA according to the initial address YI. In one embodiment, the address counter 25 sets the initial value of the current address CA to the initial address YI, and increases the current address CA by 1 every cycle. For example, in the first cycle, the current address CA is equal to the first address, in the second cycle, the current address CA is equal to the second address, and in the third cycle, the current address CA is equal to the third address. So on and so forth. The address counter 25 sends the current address CA to the adder 13 and the multiplexer 21.

In step 230, the adder 13 adds the offset value OV to the current address CA to generate a comparison address MA. In one embodiment, the deviation value OV is one. That is, in a sequential memory access operation, the comparison address MA may represent the next address to be accessed. For example, the adder 13 may add 1 to the current address CA (the current address CA is equal to the first address "addr [5]") to generate a comparison address MA (equal to the second address "addr [6]") . The invention is not limited to this. The deviation value OV can be set to a different integer value, which will be described in other embodiments.

In one embodiment, the pre-comparison system 300 further includes a functional multiplexer 11 to provide a deviation value OV. In FIG. 3, the functional multiplexer 11 receives two integers 1 and 0 as inputs, and receives the pre-comparison selection signal PM as a selection signal. In an embodiment of the present case, when the pre-comparison function is enabled, the pre-comparison selection signal PM is set to a logic high level, otherwise the pre-comparison selection signal PM is set to a logic low level.

At step 240, the mapping circuit 15 compares the address MA with the mapping table 16 At least one of the defect addresses is compared to generate a hit parameter HT.

In step 250, the mapping circuit 15 generates a redundant address RY related to the comparison address MA.

In one embodiment, the pre-comparison system 300 further includes a repair analysis circuit 23 for confirming a defect state in the memory array 20 to generate a mapping table 16. Therefore, the mapping table 16 records at least one defect address. The defective address represents the address of a defective memory cell in the memory array 20.

Please refer to FIGS. 4A to 4B. FIGS. 4A to 4B are flowcharts of the Y-direction repair analysis method according to an embodiment of the present invention. In one embodiment, the Y-direction repair analysis method can find and repair the defect columns in the memory array 20. It should be noted that the present invention is not limited to using the Y-direction repair analysis method. The Y-direction repair analysis method is used here to provide an example to find and repair defects in NAND flash memory.

In step 401, the mapping circuit 15 performs a global defect screen to find defective rows. For example, a row (for example, rows C1 and C1 'in FIG. 1) relates to, for example, a plurality of memory cells located in an array (for example, a normal array NA and a redundant array RA in FIG. 3), setting Several sets of sensing circuits in a page buffer system (for example, page buffer PGB and redundant buffer RPR in Figure 3), and a cache system (for example, cache memory NCH and redundancy in Figure 3) Cache memory (RCH). Multiple rows form a memory macro. The sensing circuit can be used to identify data in the memory unit. The data read by the sensing circuit can be sent to the cache memory. The cache memory can temporarily store the read data until the input / output circuit 10 reads the data. all Domain defect scanning can confirm the defect status by scanning the flash memory cells, sensing circuits and cache circuits in each row.

In step 402, the repair analysis circuit 23 confirms whether the current detection area contains a defect. If the current detection area contains a defect, proceed to step 403; otherwise, proceed to step 405. In step 403, the mapping circuit 15 confirms whether the redundancy in the Y direction overflows. If the mapping circuit 15 confirms the Y-direction redundancy overflow value, it means that there is no remaining redundancy in the Y-direction to repair the global defect (for example, the Y-direction redundant space has been used up). Therefore, if step 403 is YES, proceed to step 415 . If the mapping circuit 15 confirms that there is no overflow value in the Y-direction redundancy, it proceeds to step 404.

In step 415, since the NAND flash memory contains too many defects, the repair analysis circuit 23 discards the NAND flash memory. Conversely, if there is no overflow in the Y-direction redundancy, the repair analysis circuit 23 uses the Y-direction redundancy to repair the global defect in step 404. In step 405, the repair analysis circuit 23 determines whether the current detection pattern is the last circuit pattern. If the repair analysis circuit 23 determines that the current detection pattern is the last circuit pattern, the process proceeds to step 407; otherwise, the process proceeds to step 406. In step 406, the repair analysis circuit 23 detects the next circuit pattern.

In step 407, the repair and analysis circuit 23 performs a local defect screen. This represents the repair analysis circuit 23 to find the defect of the current detection block. In step 408, if any defect is detected in the current detection block, the process proceeds to step 409; otherwise, the process proceeds to step 411. In step 409, the repair analysis circuit 23 confirms whether the redundancy in the Y direction overflows. If in step 409, the mapping circuit 15 confirms the redundancy in the Y direction, it means that no redundancy in the Y direction can be used to repair the local defect (for example, For example, the redundant space in the Y direction has been used up), and therefore, step 415 is performed. If in step 409, the repair and analysis circuit 23 confirms that there is no overflow in the Y-direction redundancy, it proceeds to step 410. In step 410, the repair and analysis circuit 23 uses the remaining redundancy in the Y direction to repair local defects. In step 411, the repair analysis circuit 23 determines whether the current detection pattern is the last circuit pattern. If the repair analysis circuit 23 determines that the current detection pattern is the last circuit pattern, the process proceeds to step 412, otherwise, the process proceeds to step 413. In step 413, the repair analysis circuit 23 detects the next circuit pattern. In step 412, the mapping circuit 15 determines whether the current detection block is the last block. If the mapping circuit 15 determines that the current detection block is not the last block, it proceeds to step 414 to determine the next block, and if not, ends the Y-direction repair analysis method.

In the Y-direction repair analysis method of the embodiment of this case, both global defects and local defects can be scanned out. When a defect is found, the repair analysis circuit 23 first confirms whether the redundancy in the Y direction is sufficient to repair the defect. If the redundancy in the Y direction is sufficient to repair the defect, the row address where the defect lies is written into the mapping table 16 and is mapped to the redundant address RY to perform the repair function, and the redundant address RY replaces the defective row position . In addition, other embodiments of this case can also use known algorithms to repair NAND flash memory.

The repair analysis circuit 23 transmits the corresponding result FY to the mapping table 16. The mapping circuit 15 compares the comparison address MA with at least one defective address in the mapping table 16 to generate a hit parameter HT (hit parameter). If at least one defect address is the same as the comparison address MA, the hit parameter HT is set to a logic high level; otherwise, the hit parameter HT is set to a logic low level. In addition, the mapping circuit 15 finds the redundant address RY related to the comparison address MA.

The mapping circuit 15 transmits the hit parameter HT to the first register 17, and transmits the redundant address RY to the second register 19. The first register 17 temporarily stores the hit parameter HT. In an embodiment, the second register 19 temporarily stores the redundant address RY corresponding to the comparison address MA (for example, it is represented as "addressr [0]" in the redundant array RA). When the comparison address is When MA is recorded as an error position in the mapping table 16, that is, the comparison address MA is marked as a defective address in the mapping table 16, and the redundant address RY is used instead of the comparison address MA. In one embodiment, the first register 17 and the second register 19 may be D-type flip-flops. The temporary hit parameter HT ′ output by the first register 17 is the delay of the hit parameter HT, and the redundant address RY ′ output by the second register 19 is the delay of the redundant address RY. .

In step 260, the multiplexer 21 sets the Y-direction address YA as the redundant address RY 'or the current address CA according to the hit parameter HT', and transmits the output address (Y-direction address YA) to the line control circuit. 27. When the hit parameter HT 'is a logic high level, the Y direction address YA is set as the redundant address RY', and when the hit parameter HT 'is a logic low level, the Y direction address YA is set as the current address CA .

In an embodiment, when the hit parameter HT '(as a judgment signal) is set to a logic low level, the multiplexer 21 transmits the current address CA to the line control circuit 27, and the line control circuit 27 is triggered by the Y direction control signal YC The normal lines in the normal array NA output data corresponding to the Y-direction address YA. On the other hand, when the hit parameter HT 'is at a logic high level, the multiplexer 21 transmits the redundant address RY' to the row control circuit 27 to output the repair data of the redundant array RA in the third figure. The signals SX and SY are address signals. When performing repair analysis, the signals SX and SY can be used to access memory (that is, (During operation, the signals SX and SY are not used to access the memory.) In an embodiment of the present case, the Y-direction repair unit may be a word, a byte, or even a bit.

In some embodiments, the row control circuit 29 can also be used to trigger the memory array to output the correct data in the X direction corresponding to the output address by controlling the signal XC in the X direction. The pre-comparison system and the pre-comparison method can also be implemented by replacing the row defect data with redundant row data in the X direction due to the X direction.

In an embodiment, when the Y-direction address YA is set as the redundant address RY ', the data (eg, correct data) corresponding to the Y-direction address YA is written into the redundant buffer RPR, and the data is made redundant. Cache memory RCH output. Once the redundant address is accessed, the redundant cache memory RCH can obtain data from the data signal IND of the input-output circuit 10 and send the output data to the input-output circuit 10 by the data signal OTD.

In an embodiment, when the Y-direction address YA is set to the current address CA (the address used to access the normal array NA), data (eg, correct data) corresponding to the Y-direction address YA is written The page buffer (page buffer) is PGB, and the data is output from the normal cache memory NCH. When the normal cache memory NCH is accessed, the normal cache memory NCH can receive data from the input-output circuit 10 through the data signal IND, and output data to the input-output circuit 10 through the data signal OTD.

Please refer to FIGS. 3 and 5. FIG. 5 is a schematic diagram of the operation timing of the pre-comparison system 300 that can be applied to FIG. 3. In an embodiment, the time axis TL sequentially includes a waiting time, a time interval t1, a time interval t2, a time interval t3, and a time interval t4. Wait. The period of each time interval t1-t4 is the same as the clock period CIO of the input-output circuit 10, and the same as the period CDFF of the D-type flip-flop. The period CDFF of the D-type flip-flop is used to control the timing of receiving and transmitting data from the first register 17 and the second register 19. Therefore, the first register 17 and the second register 19 can operate synchronously. In one embodiment, the pre-comparison system 300 may use a DDR interface to output two bytes (such as a high byte and a low byte) in one cycle, as shown by the data output / input DTIO.

FIG. 5 shows the operation timing diagram of the pre-comparison method assuming that the comparison address MA needs to be repaired. In one embodiment, the address counter 25 transmits the current address CA to the adder 13. Because the pre-comparison selection signal PM is still at a logic low level during the waiting time wt, the adder 13 directly bypasses the current address CA to become the Y-direction address YA. Since it is assumed that the first address is not recorded in the mapping table 16, the hit parameter HT is a logic low level, because the mapping circuit 15 determines that the comparison address MA is not the same as any defective address recorded in the mapping table 16. Therefore, in the time interval t1, the hit parameter HT 'is a logic low level (because the hit parameter HT is a logic low level in the previous time interval wt), and the Y-direction address YA will be the same as the current address CA. On the other hand, the pre-comparison selection signal PM transitions to a logic high level at the beginning of the time interval t1. Therefore, the adder 13 adds 1 to the current address CA to generate the comparison address MA, and sends the comparison address MA to the mapping circuit 15. Then, at a first time interval t1, the mapping circuit 15 compares the comparison address MA with at least one defective address in the mapping table 16. In this assumption, the comparison address MA conforms to at least one defective address in the mapping table 16, so that the hit parameter HT stored in the first register 17 is changed to a logic high level, and the redundant address RY is temporarily It is stored in the second register 19. In the next clock cycle, the hit parameter HT ’and the redundant address RY’ are at the second time. The interval t2 is transmitted to the multiplexer 21 at the same time. Then, in the second time interval t2, the data stored in the redundant address RY 'is output (this can be represented by the Y-direction address YA in the second time interval t2).

Thus, when the current address CA (original address) points to the wrong row, the Y-direction address YA is switched to the corresponding redundant address RY '; otherwise, the Y-direction address YA is equivalent to the current address CA. Because in this example, as assumed, the third address and the fourth address are not recorded in the mapping table 16. In the third time interval t3 and the fourth time interval t4, the pre-comparison system 300 can set the The Y-direction address YA is set to the current address CA.

Please refer to FIG. 6, which is a schematic diagram of a pre-comparison system 600 according to an embodiment of the present invention. In one embodiment, if the pre-comparison time is longer than the output cycle time, the pre-comparison system 600 in FIG. 6 (including the functional multiplexer 51, 61, 71, 81, address counter 75, and address multiplexer) 70. The line control circuit 74 and the adders 53, 63, 73, and 83 can replace the pre-comparison system 300 in FIG. 3 (including the functional multiplexer 11, the address counter 25, the multiplexer 21, and the line control circuit. 27 and adder 13). The functional multiplexers 51, 61, 71 and 81 can provide different deviation values to the adders 53, 63, 73 and 83. For example, according to the pre-comparison selection signal PM, the functional multiplexer 51 sets the deviation value to 0 or 4, the functional multiplexer 61 sets the deviation value to 1 or 5, and the functional multiplexer 71 sets the deviation value to 2 or 6. The function multiplexer 81 sets the deviation value to 3 or 7.

6 is different from FIG. 3 in that the pre-comparison system 600 of FIG. 6 divides the mapping table 16 into four partial mapping tables 66a to 66d. The number of mapping tables 16 can be adjusted as needed. The pre-comparison system 600 includes four mapping circuits 65a-65d for accessing the corresponding mapping tables 66a-66d. Taking Figure 6 as an example, the mapping of Figure 3 The shooting table 16 is divided into four partial mapping tables 66a to 66d. On the other hand, the defect addresses are sorted and stored in different sub-mapping tables 66a to 66d according to the corresponding defect addresses. In this case, the defect address is a multiple of 4 (also can be expressed as 4n, where n is an integer) and stored in the mapping table 65a; the defect address is 4n + 1, but is stored in the mapping table 65b; The defect address is 4n + 2, which is stored in the mapping table 65c; and the defect address is 4n + 3, which is stored in the mapping table 65d.

In one embodiment, each of the mapping circuits 65a to 65d corresponds to two types of registers, namely, hit flag registers 67a to 67d and redundant address registers 69a to 69d. For example, the mapping circuit 65a is coupled to the hit flag register 67a and the redundant address register 69a. The functions and operation methods of the hit flag registers 67a to 67d are the same as those of the first register 17 shown in FIG. 3, and the functions and operation methods of the redundant address registers 69a to 69d are the same as those shown in FIG. The second register 19 is the same. In addition, the registers 67a to 67d are connected in series, and the registers 69a to 69d are connected in series. For example, the data output end of the register 69b (that is, the Q port of the D-type flip-flop) is coupled to the data input end of the register 69a (that is, the D port of the D-type flip-flop), and the rest can follow this analogy. When the memory load signal MEL is at a logic high level, the hit flag registers 67a ~ 67d and the redundant address registers 69a ~ 69d are connected to the corresponding mapping circuits through the transistors F1 ~ F8. 65a ~ 65d. The transistors F1 to F8 are respectively coupled between the registers 69a to 69d and the mapping circuits 65a to 65d. The transistors F1 ~ F8 are controlled by the memory load signal MEL.

Please refer to FIG. 7, which is a schematic diagram of the operation timing of the pre-comparison system of FIG. 6. It is assumed that the second address needs to be repaired. In one embodiment, the pre-comparison system 600 of FIG. 6 uses a DDR architecture. However, the invention is not limited to the use of DDR Architecture, for example, other embodiments of the present invention may also adopt a single data rate (SDR).

In the waiting time wt, the pre-comparison selection signal PM is set to a logic low level. Accordingly, the comparison addresses MA0 ~ MA3 represent the first 4 addresses, and the current address CA is the initial address (which is the first address). The mapping circuits 65a to 65d compare the comparison addresses MA0 to MA3 with the defect addresses in the mapping tables 66a to 66d. With parallel processing of the mapping circuits 65a to 65d, the comparison time can be extended to 4 times of the CLC cycle.

In the last period of the waiting time wt, the memory load signal MEL has a half period as the high level, so as to transmit the redundant address and the hit flag to the redundant address registers 69a to 69d and the hit flag temporarily. Registers 67a ~ 67d. Because it is assumed that only the second address is defective, when the memory load signal MEL is at a high level, only the hit flag register 67b is logic high, and the other hit flag registers 67a, 67c, and 67d Is logic low. In addition, the redundant address related to the second address is temporarily stored in the redundant address register 69b.

After the four redundant addresses and hit flags located in the mapping circuits 65a to 65d are transmitted to the redundant address registers 69a to 69d and the hit flag registers 67a to 67d, respectively, when the memory load signal MEL is pulled high, and the pre-comparison selection signal PM is pulled high during the fifth clock cycle CLC. The first time interval i1 includes a fifth clock cycle CLC to an eighth clock cycle CLC. In one embodiment, each time interval (for example, time interval i1) includes four clock cycles CLC. In the time interval i1, when the pre-comparison selection signal PM is at a high level, add 4, 5, 6, and 7 to the current address CA (in the fifth clock cycle, the current address CA is still initial Address (first address)) to generate a match Addresses MA0-MA3. According to this, the mapping circuits 65a to 65d obtain the next 4 addresses (that is, the fifth to eighth addresses) for the pre-comparison function.

In one embodiment, at each clock cycle CLC starting from the fifth clock cycle CLC, the following event is performed: the data stored in the redundant address register 69b is moved to the redundant address register 69a (for example, the data stored in the redundant address register 69b overwrites the data stored in the redundant address register 69a), and the data stored in the redundant address register 69c is moved to The redundant address register 69b, the data stored in the redundant address register 69d is moved to the redundant address register 69c.

Because there is no need to repair the first address, the hit flag HT received from the hit flag register 67a in the fifth cycle is logic low. Because, the address multiplexer 70 transmits the current address CA to the row control circuit 74 to output data about the first address. In the sixth clock cycle CLC, because the second address contains a defect, in the fifth cycle CLC, the hit from the hit flag register 67b to the hit of the second address of the hit flag register 67a The flag is sent by the hit flag register 67a and is used as the hit parameter HT (that is, the hit parameter HT is overwritten by the hit flag in the hit flag register 67b), and it has been replaced by a redundant address The related redundant address transmitted from the register 69b to the redundant address register 69a is sent by the redundant address register 69a and regarded as the redundant address RY (that is, the redundant bit The address RY is overwritten by the redundant address in the redundant address register 69b). The hit flags stored in the hit flag registers 67b to 67d are moved to the right hit flag registers 67a to 67c, respectively, and the redundant bits in the redundant address registers 69b to 69d are stored. The addresses are moved to the redundant address registers 69a ~ 69c on the right. Because in this example, the third address and the fourth address are not recorded in the mapping tables 66c and 66d, and within the third time interval t3 and the fourth time interval t4, The pre-comparison system 600 outputs the current address CA.

It should be noted that this case is not limited to the use of four mapping tables. Other possible embodiments of this case may use any number of mapping tables. Therefore, the pre-comparison system can compare tables 66a to 66d to check whether there are defective addresses at the same time, thereby reducing the calculation time. In addition, since each of the partial comparison tables 66a to 66d has a smaller amount of data than the original comparison table, the mapping circuits 65a to 65d can complete the comparison procedure more quickly.

Based on the above description and detailed description of multiple embodiments, the pre-comparison system and pre-comparison method can find out whether the next read address needs to be repaired. In the case of sequential access, the next read address can be easily pre-aligned because subsequent addresses increase linearly. In addition, the next read address is transferred to a mapping table (which contains all defective addresses) to determine whether the next read address is defective. If the next read address matches one of the defective addresses recorded in the mapping table, the mapping circuit obtains the row or column redundant address corresponding to the next read address in advance, and in the next cycle, directly Output the data of related redundant row or column addresses. As a result, the data access time of the NAND flash memory can be shortened, and the transmission speed of the DDR or SDR interface can be effectively supported.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (10)

A pre-comparison system includes: a memory array; an input-output circuit for receiving an initial address; a single-bit counter coupled to the input-output circuit for gradually increasing a current address according to the initial address; An address; an adder coupled to the address counter to add an offset value to the current address to obtain a comparison address; a mapping table to store at least one defective address; a mapping circuit , Coupled to the mapping table and the adder, for comparing the comparison address with the at least one defect address stored in the mapping table to generate a hit parameter and generating a correlation related to the comparison address. A redundant register; a first register coupled to the mapping circuit to store the hit parameter; a second register coupled to the mapping circuit to store the redundant address; and a multiple A worker coupled to the first and the second registers to set a Y-direction address as the current address or the redundant address according to the hit parameter stored in the first register, The Y-direction address is related to the memory array. . The pre-comparison system described in item 1 of the patent application scope further includes: a row of control circuits coupled to the multiplexer for receiving the Y-direction address and triggering the memory array to output the Y-direction. Address data; a repair analysis circuit to check a defect state in the memory array to generate the mapping table; and a functional multiplexer coupled to the adder to respond to a pre-comparison The signal is selected and the deviation value is set to a first integer or a second integer, and if a pre-match function is enabled, the pre-match selection signal is logic high. The pre-comparison system described in item 1 of the scope of the patent application, wherein the mapping circuit is configured to: if the comparison address matches the at least one defect address stored in the mapping table, set the hit parameter Is logic high; if the comparison address does not match any of the at least one defective address stored in the mapping table, the hit parameter is set to logic low; the multiplexer is used: when the hit parameter is logic When high, the Y-direction address is set as the redundant address; and when the hit parameter is logic low, the Y-direction address is set as the current address. The pre-comparison system described in item 1 of the patent application scope, wherein the memory array includes a redundant buffer and a redundant cache memory, and when the Y-direction address is set as the redundant address , The data related to the Y-direction address is written to the redundant buffer and output by the redundant cache memory; and the memory array includes a page buffer and a normal cache memory, when set When the Y-direction address is the current address, data related to the Y-direction address is written to the page buffer and output by the normal cache memory. The pre-comparison system described in item 1 of the scope of patent application, further includes: a lower-level adder for adding a lower-level deviation value to the current address to generate a lower-level comparison address, wherein the lower-level comparison address The deviation value is different from the deviation value; the lower-level mapping table is used to store at least the lower-level defect address; the lower-level mapping circuit is used to compare the lower-level comparison address with the at least lower-level defect stored in the lower-level mapping table Address to generate a lower-level hit parameter, and a lower-level redundant address related to the lower-level comparison address; a lower-level first register for storing the lower-level hit parameter, wherein the lower-level first A data output terminal of the register is coupled to a data input terminal of the first register; a lower-level second register is used to store the lower-level redundant address, and the lower-level second register is A data output is coupled to a data input of the second register; a first transistor is coupled between the first register and the mapping circuit; and a second transistor is coupled to the second register Memory and the mapping circuit; where The first and second transistors are controlled by a memory load signal. A pre-comparison method for a pre-comparison system. The pre-comparison system includes a memory array. The pre-comparison method includes: receiving an initial address; gradually increasing a current address according to the initial address; A deviation value is added to the current address to obtain a comparison address; comparing the comparison address with at least one defective address to generate a hit parameter; and generating a redundant address related to the comparison address; And setting a Y-direction address as the current address or the redundant address according to the hit parameter, the Y-direction address is related to the access to the memory array. The pre-comparison method described in item 6 of the patent application scope further comprises: triggering the memory array to output data related to the address in the Y direction; inspecting a defect state in the memory array to generate a mapping Table, the mapping table is used to store the at least one defect address; and the deviation value is set to a first integer or a second integer in response to a pre-comparison selection signal, wherein if a pre-comparison function is enabled If so, the pre-match selection signal is logic high. The pre-comparison method as described in item 6 of the scope of patent application, wherein generating the hit parameter includes: if the comparison address matches the at least one defective address, setting the hit parameter to a logic high; if the The comparison address does not match any of the at least one defective address, then the hit parameter is set to a logic low; and setting the Y direction address includes: when the hit parameter is a logic high, setting the Y direction address Is the redundant address; and when the hit parameter is logic low, the Y-direction address is set to the current address. The pre-comparison method described in item 6 of the scope of patent application, wherein the memory array includes a redundant buffer and a redundant cache memory, and when the Y-direction address is set as the redundant address , The data related to the Y-direction address is written to the redundant buffer and output by the redundant cache memory; and the memory array includes a page buffer and a normal cache memory, when set When the Y-direction address is the current address, data related to the Y-direction address is written to the page buffer and output by the normal cache memory. The pre-comparison method described in item 6 of the patent application scope further includes: adding a lower-level deviation value to the current address to generate a lower-level comparison address, wherein the lower-level deviation value is different from the deviation value ; Compare the lower-level comparison address with at least one lower-level defect address stored in the lower-level mapping table to generate a lower-level hit parameter; generate a lower-level redundant address related to the lower-level comparison address; use the The lower-level hit parameter overwrites the hit parameter; and the lower-level redundant address overwrites the redundant address.