CN110844891B - Chalcogenide material and electronic device including the same - Google Patents

Chalcogenide material and electronic device including the same Download PDF

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CN110844891B
CN110844891B CN201910688303.XA CN201910688303A CN110844891B CN 110844891 B CN110844891 B CN 110844891B CN 201910688303 A CN201910688303 A CN 201910688303A CN 110844891 B CN110844891 B CN 110844891B
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memory
content
germanium
silicon
chalcogenide material
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CN110844891A (en
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李禹太
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SK Hynix Inc
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    • C01B19/002—Compounds containing, besides selenium or tellurium, more than one other element, with -O- and -OH not being considered as anions
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    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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Abstract

A chalcogenide material and an electronic device including the same are provided. The chalcogenide material may include 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium. The electronic device may include: a switching element comprising a chalcogenide material comprising 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium; a first electrode electrically coupled to the switching element; and a second electrode electrically coupled to the switching element.

Description

Chalcogenide material and electronic device including the same
Cross Reference to Related Applications
The present application claims priority from korean patent application No. 10-2018-0096780, entitled "CHALCOGENIDE MATERIAL AND ELECTRONIC DEVICE INCLUDING THE SAME (chalcogenide material and electronic device including the same), filed on 8-20, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
This patent document relates to memory circuits or memory devices and their use in electronic devices or systems.
Background
Recently, as electronic devices or electric appliances tend to be miniaturized, low power consumption, high performance, multi-function, and the like, it is required to be able to store information in various electronic devices or electric appliances such as computers, portable communication devices, and the like, and research and development on such electronic devices have been conducted. Examples of such electronic devices include electronic devices that can store data using characteristics that switch between different resistance states according to an applied voltage or current, and can be implemented in various configurations, for example, RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), electric fuse, and the like.
Disclosure of Invention
The technology disclosed in this patent document includes memory circuits or memory devices and their use in electronic devices or systems, and various embodiments of electronic devices, where the electronic devices include semiconductor memories (or semiconductor memory devices) that can improve the characteristics of select elements.
In one aspect, the chalcogenide material may include 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium.
Embodiments of the chalcogenide materials described above may include one or more of the following.
The silicon content may be 1-5at%. The germanium content may be 15-20at%. The arsenic content may be 25-30at%. The selenium content may be 42-47at%. The tellurium content may be 2-8at%. The sum of the silicon content and the germanium content may be 20at% or more.
In another aspect, an electronic device may include: a switching element comprising a chalcogenide material comprising 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium; a first electrode electrically coupled to the switching element; and a second electrode electrically coupled to the switching element.
Implementations of the electronic device described above may include one or more of the following.
The silicon content may be 1-5at%. The germanium content may be 15-20at%. The arsenic content may be 25-30at%. The selenium content may be 42-47at%. The tellurium content may be 2-8at%. The sum of the silicon content and the germanium content may be 20at% or more.
In yet another aspect, an electronic device may include a semiconductor memory device, where the semiconductor memory device may include a first memory cell including a first switching element, where the first switching element may include a chalcogenide material including 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium.
Implementations of the electronic device described above may include one or more of the following.
The semiconductor memory device may further include a second memory cell including a second switching element having a chalcogenide material including 1 to 10 atomic percent (at%) of silicon, 10 to 20at% of germanium, 25 to 35at% of arsenic, 40 to 50at% of selenium, and 1 to 10at% of tellurium, and the first and second memory cells may further include first and second memory layers, respectively, each of the first and second memory layers being switched between different resistance states according to a voltage or current applied thereto. The first switching element and the second switching element may control access to the first storage layer and the second storage layer, respectively. The semiconductor memory device may include a plurality of memory cells including a first memory cell, wherein the semiconductor device may further include: a plurality of first lines disposed between the substrate and the plurality of memory cells, each of the plurality of first lines extending in a first direction; and a plurality of second lines disposed over the plurality of memory cells, each of the plurality of second lines extending in a second direction crossing the first direction, and wherein the plurality of memory cells are disposed at respective crossing points of the first lines and the second lines. The semiconductor memory device may further include a capping layer disposed at least on a side surface of the first memory cell. The silicon content may be 1-5at%. The germanium content may be 15-20at%. The arsenic content may be 25-30at%. The selenium content may be 42-47at%. The tellurium content may be 2-8at%. The sum of the silicon content and the germanium content may be 20at% or more.
The electronic device may further include a microprocessor, the microprocessor including: a control unit configured to receive a signal including a command from outside the microprocessor and perform extraction, decoding, or control of input or output of the signal of the microprocessor; an operation unit configured to perform an operation based on a result of decoding the command by the control unit; and a memory unit configured to store data for performing an operation, data corresponding to a result of performing the operation, or an address of the data for performing the operation, wherein the semiconductor memory is a part of the memory unit in the microprocessor.
The electronic device may further include a processor, the processor including: a core unit configured to perform an operation corresponding to a command by using data based on the command input from the outside of the processor; a cache unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of the data for performing the operation; and a bus interface connected between the core unit and the cache unit and configured to transfer data between the core unit and the cache unit, wherein the semiconductor memory is part of the cache unit in the processor.
The electronic device may further include a processing system comprising: a processor configured to decode a command received by the processor and control an operation on information based on a result of decoding the command; a secondary storage device configured to store a program and information for decoding a command; a main storage device configured to call and store a program and information from the auxiliary storage device so that a processor can perform operations using the program and information when the program is run; and an interface device configured to perform communication between at least one of the processor, the auxiliary storage device, and the main storage device and the outside, wherein the semiconductor memory is a part of the auxiliary storage device or the main storage device in the processing system.
The electronic device may further comprise a data storage system comprising: a storage device configured to store data and to hold the stored data regardless of a power source; a controller configured to control input and output of data to and from the storage device according to a command input from the outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller, and the temporary storage device and the outside, wherein the semiconductor memory is a storage device or a part of the temporary storage device in the data storage system.
The electronic device may further include a storage system comprising: a memory configured to store data and to hold the stored data regardless of a power source; a memory controller configured to control input and output of data to and from the memory according to a command input from the outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of a memory, a memory controller, and a buffer memory and the outside, wherein the semiconductor memory is a memory or a portion of a buffer memory in a storage system.
In yet another aspect, an electronic device may include a semiconductor memory device, wherein the semiconductor memory device may include: a substrate; a plurality of first lines disposed over the substrate, and each of the first lines extending in a first direction; a plurality of second lines, each extending in a second direction intersecting the first direction; and a plurality of memory cells disposed at respective intersections of the plurality of first lines and the plurality of second lines, wherein each of the plurality of memory cells may include: a variable resistance layer that switches between different resistance states according to a voltage or a current applied thereto; and a select element layer that controls access to the variable resistance layer, and wherein the select element layer may comprise a chalcogenide material comprising 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium.
Embodiments of the above method may include one or more of the following.
The variable resistance layer may include any one of a metal oxide, a phase change material, a ferroelectric material, a ferromagnetic material, and combinations thereof. The selection element layer may have any one of a single-layer structure and a multi-layer structure. Each of the plurality of memory cells may further include: a lower electrode layer coupled to a lowermost portion of each of the plurality of memory cells and serving as a transmission path of a voltage or a current between a corresponding one of the plurality of first lines and a portion of each of the memory cells other than the lowermost portion; an intermediate electrode layer physically separating the selection element layer from the variable resistance layer and electrically coupling the selection element layer to the variable resistance layer; and an upper electrode layer coupled to an uppermost portion of each of the plurality of memory cells and serving as a transmission path of a voltage or a current between a corresponding one of the plurality of second lines and a portion of each of the memory cells other than the uppermost portion. The semiconductor memory device may further include a capping layer disposed at least on side surfaces of the plurality of memory cells. The silicon content may be 1-5at%. The germanium content may be 15-20at%. The arsenic content may be 25-30at%. The selenium content may be 42-47at%. The tellurium content may be 2-8at%. The sum of the silicon content and the germanium content may be 20at% or more.
These and other aspects, embodiments, and related advantages are described in more detail in the accompanying drawings, description, and claims.
Drawings
Fig. 1 shows normalized band gap energy (Eg) as a function of Te content in chalcogenide material in accordance with an embodiment of the disclosed technology.
Fig. 2 shows normalized off-current (Ioff) as a function of Te content in chalcogenide material in accordance with an embodiment of the disclosed technology.
Fig. 3 shows normalized trap density as a function of Te content in chalcogenide material in accordance with an embodiment of the disclosed technology.
Fig. 4 shows normalized threshold voltages (Vth) according to Te content in chalcogenide materials in accordance with embodiments of the disclosed technology.
Fig. 5 shows a normalized threshold voltage (Vth) distribution according to Te content in a chalcogenide material.
Fig. 6 is a perspective view of a semiconductor memory according to an embodiment of the disclosed technology.
Fig. 7A to 7D are cross-sectional views illustrating an exemplary semiconductor memory and a method of manufacturing the same according to an embodiment of the disclosed technology.
Fig. 8 is a cross-sectional view illustrating a semiconductor memory according to an embodiment of the disclosed technology.
Fig. 9 is an example of a configuration diagram of a microprocessor implementing a memory circuit in accordance with an embodiment of the disclosed technology.
Fig. 10 is an example of a configuration diagram of a processor implementing a memory circuit in accordance with an embodiment of the disclosed technology.
Fig. 11 is an example of a configuration diagram of a system implementing a memory circuit in accordance with an embodiment of the disclosed technology.
Fig. 12 is an example of a configuration diagram of a data storage system implementing a memory circuit in accordance with an embodiment of the disclosed technology.
Fig. 13 is an example of a configuration diagram of a memory system implementing a memory circuit based on an embodiment of the disclosed technology.
Detailed Description
Various examples and embodiments of the disclosed technology are described in detail below with reference to the accompanying drawings.
The figures may not be drawn to scale and in some cases the proportions of at least some of the substrates in the figures may have been exaggerated to show certain features of the described examples or embodiments. Where a particular example is presented in the figures or description having two or more layers in a multi-layer substrate, the relative positional relationship of the layers as shown or the order in which the layers are arranged reflects the particular implementation for the example described or shown, as well as different relative positional relationships or order in which the layers are arranged are possible.
According to embodiments of the present disclosure, a chalcogenide material for a switching element (SWITCHING ELEMENT) may be provided. Chalcogenides are compounds composed of at least one chalcogen anion with one or more cationic materials. Chalcogenide materials may be used as phase change materials or switching elements, depending on the combination of constituent elements and their contents.
In embodiments of the disclosed technology, the chalcogenide material may include 1-10 atomic percent (at%) silicon (Si), 10-20at% germanium (Ge), 25-35at% arsenic (As), 40-50at% selenium (Se), and 1-10at% tellurium (Te). In another embodiment of the disclosed technology, the chalcogenide material may include 1-5at% silicon (Si), 15-20at% germanium (Ge), 25-30at% arsenic (As), 42-47at% selenium (Se), and 2-8at% tellurium (Te). In yet another embodiment of the disclosed technology, the chalcogenide material may include about 1.5at% (e.g., 1.4-1.6at%, 1.45-1.55at%, 1.47-1.53at%, or 1.49-1.51 at%) silicon (Si), about 19.5at% (e.g., 19.4-19.6at%, 19.45-19.55at%, 19.47-19.53at%, or 19.49-19.51 at%) germanium (Ge), about 29.0at% (e.g., 28.9-29.1at%, 28.95-29.05at%, 28.97-29.03at%, or 28.99-29.01 at%) arsenic (As), about 45.0at% (e.g., 44.9-45.1, 44.95-45.05at%, 44.97-45.03at%, or 44.99-45.01 at%) selenium (Se), and 5.0at% (e.g., 4.9-5.1at%, 4.95-29.05 at%, or 4.03-99.95 at% (TE) of TE).
In embodiments of the disclosed technology, each constituent element in the chalcogenide material and its content may be selected such that an electronic device including the chalcogenide material may exhibit overall optimal effects in terms of voltage drift, threshold voltage (Vth), off-current (Ioff), vth distribution, and durability, among others. Although individual characteristics among the above characteristics can be improved by appropriately selecting any one of the constituent elements and the content thereof, other characteristics may be deteriorated. Therefore, it is desirable to select the optimum constituent elements and adjust their contents, which can produce the optimum effect in consideration of the above-described characteristics together. In embodiments of the disclosed technology, each constituent element contained in a chalcogenide material and its content may be determined in consideration of various aspects of balancing device performance.
In chalcogenide materials, silicon (Si) and germanium (Ge) can affect voltage drift (or threshold voltage drift) and thermal stability. The voltage shift may represent a change in threshold voltage (Vth) of the select element according to a delay time (or device delay time) of a device including the select element. For example, the device delay time is the delay between an input pulse applied to a first terminal of a device and an output pulse generated at a second terminal of the device in response to the input pulse, the device including a selection element and a variable resistance element coupled in series with each other. As the value of the voltage drift decreases, the device may exhibit better characteristics. For example, a device according to one embodiment may perform better than a conventional device if it has a difference between a first threshold voltage at a first device delay time and a second threshold voltage at a second given delay time that is less than this difference for the conventional device. Silicon (Si) may be used to substantially suppress the occurrence of voltage drift acceleration, which represents an increase in the difference between threshold voltages, especially when the device delay time is relatively long (e.g., 100ms or more). However, the degree of acceleration of the voltage drift may not be reduced in proportion to the amount of increase in the silicon (Si) content. In contrast, when the silicon (Si) content increases, other device characteristics may deteriorate. Accordingly, the silicon (Si) content may be determined within such a range as to reduce degradation of other device characteristics while reducing voltage drift and enhancing thermal stability.
In embodiments of the disclosed technology, the silicon (Si) content in the chalcogenide material may be 1-10at%, or 1-5at%. When the silicon (Si) content is less than 1at%, vth variation according to the device delay time may be nonlinearly and significantly increased so that voltage drift may be accelerated. When the silicon (Si) content in the chalcogenide material is more than 10at%, other device characteristics may deteriorate. For example, deterioration in durability, increase in voltage drift, increase in Ioff, and increase in Vth distribution due to increase in hard failure and increase in decrease in Vth may occur.
Germanium (Ge) contained in chalcogenide materials can affect voltage drift and thermal stability along with silicon (Si). Germanium (Ge) may be used to substantially suppress voltage drift acceleration (e.g., acceleration of Vth increases) and to control voltage drift, especially when device delay times are relatively short (e.g., 100ms or less). The germanium (Ge) content may be determined within such a range as to reduce degradation of other device characteristics while reducing voltage drift and enhancing thermal stability.
In embodiments of the disclosed technology, the germanium (Ge) content in the chalcogenide material may be 10-20at%, or 15-20at%. When the germanium (Ge) content is less than 15at%, the silicon (Si) content may increase, resulting in degradation of one or more device characteristics. For example, deterioration in durability, increase in voltage drift, increase in Ioff, and increase in Vth distribution due to increase in hard failure and increase in decrease in Vth may occur. When the germanium (Ge) content is more than 20at%, thermal stability may be improved, but voltage drift may be accelerated.
Meanwhile, silicon (Si) content and germanium (Ge) content may affect the thermal stability of chalcogenide materials. As thermal stability increases, margin in subsequent processes may be increased and one or more device characteristics stabilized.
In one embodiment, the sum of the silicon (Si) content and the germanium (Ge) content is preferably 20at% or more in view of thermal stability. When the sum of the silicon (Si) content and the germanium (Ge) content is 20at% or more, stable characteristics can be obtained in a process at a relatively high temperature (for example, about 320 ℃). In this embodiment, when the sum of the silicon (Si) content and the germanium (Ge) content is 20at% or more, the chalcogenide material may exhibit stable characteristics. However, in another embodiment, the chalcogenide material may exhibit stable characteristics even when the sum of silicon (Si) content and germanium (Ge) is less than 20at%, by properly controlling one or more process variables such as process temperature and pressure, etc.
Arsenic (As) contained in the chalcogenide material may contribute to the formation of the amorphous structure of the chalcogenide material.
In embodiments of the disclosed technology, the arsenic (As) content may be 25-35at%, or 25-30at%. When the arsenic (As) content is less than 25at%, the switching operation of a device containing a chalcogenide material may become unstable. When the arsenic (As) content is more than 35at%, the content of each other constituent element may become relatively low due to the excessive arsenic (As) content, resulting in deterioration of device characteristics. It is therefore desirable to select the optimum content of arsenic (As) by considering these aspects together.
Selenium (Se) contained in the chalcogenide material may have an effect on the bandgap energy of the device to control the sneak current (sneak current). Furthermore, selenium (Se) may affect voltage determination. As the bandgap energy increases, the off-current (Ioff) may decrease, thereby reducing the sneak current.
In embodiments of the disclosed technology, the selenium (Se) content in the chalcogenide material may be 40-50at%, or 42-47at%. When the selenium (Se) content is less than 40at%, the device may not operate properly due to an excessively low voltage. When the selenium (Se) content is more than 50at%, the rate of decrease of Vth according to the period increases, thereby deteriorating durability. Therefore, it is desirable to select the optimal content of selenium (Se) taking these aspects into consideration together.
Tellurium (Te) can improve voltage instability and affect the voltage distribution (e.g., threshold voltage Vth distribution) of a device in response to current injected into the device.
In embodiments of the disclosed technology, the tellurium (Te) content may be 1-10at%, or 2-8at%. When the tellurium (Te) content is less than 1at%, the Vth distribution may not be sufficiently improved. When the tellurium (Te) content is more than 10at%, the leakage current may be excessively increased and the threshold voltage may be excessively reduced. Accordingly, as will be explained in more detail below with reference to fig. 1-5, it is desirable to select an optimal content of tellurium (Te) taking these aspects into account together.
Fig. 1 to 5 show the effect of tellurium (Te) content in chalcogenide materials on device characteristics. The chalcogenide materials shown in each of fig. 1 to 5 include tellurium (Te) in contents of 0at%, 5at% and 10at%, respectively. When the content of tellurium (Te) is 10at%, an expected value of the device characteristics is displayed. For example, the values of the device characteristics shown in fig. 1-5 may be calculated by extrapolating two or more values by corresponding atomic percentages of greater than 5at% and less than 10at%.
Referring to fig. 1, the effect of the tellurium (Te) content in each chalcogenide material on the bandgap energy of a device comprising the corresponding chalcogenide material will be described.
Fig. 1 shows normalized band gap energy (Eg) as a function of Te content in chalcogenide material in accordance with an embodiment of the disclosed technology. In fig. 1, the vertical axis represents normalized bandgap energy (Eg), and the horizontal axis represents Te content. For example, the values of the band gap energy (Eg) at the Te content of 0at%, 5at% and 10at% are each normalized by the value of the band gap energy (Eg) at the Te content of 0 at%.
Referring to fig. 1, as the Te content increases, as 2Te3 bonding (bonding) increases and the level of bandgap energy (Eg) decreases, which may lead to an increase in leakage current. Accordingly, the maximum content of tellurium (Te) may be determined in consideration of degradation of one or more device characteristics due to an increase in leakage current.
Fig. 2 shows normalized off-current (Ioff) as a function of Te content in chalcogenide material in accordance with an embodiment of the disclosed technology. In fig. 2, the vertical axis represents normalized off-current (Ioff), and the horizontal axis represents Te content. For example, the magnitude of the off-current (Ioff) at 0at%, 5at% and 10at% of Te content is normalized by the magnitude of the off-current (Ioff) at 0at% of Te content, respectively.
The off-current (Ioff) may refer to the current in the off-state and affect the sneak current. Sneak current may refer to current flowing in one or more paths other than the desired path. For example, the sneak current may include a current flowing through unselected memory cells instead of selected memory cells. In most cases, sneak currents may be undesirable because, for example, sneak currents may cause a decrease in read margin and increase power consumption. When the off-current increases, the sneak current also increases, and thus it may be desirable to reduce the off-current to improve the device characteristics.
Referring to fig. 2, as the Te content increases, the off-current increases. Therefore, the maximum Te content may be determined in consideration of degradation of one or more device characteristics due to an increase in off-current.
Fig. 3 shows normalized trap density as a function of Te content in chalcogenide material in accordance with an embodiment of the disclosed technology. In fig. 3, the vertical axis represents normalized trap density, and the horizontal axis represents Te content. For example, the values of trap density at Te content of 0at%, 5at% and 10at% are each normalized by the value of trap density at Te content of 0 at%.
Referring to fig. 3, as the Te content increases, the trap density increases.
Fig. 4 shows normalized threshold voltages (Vth) according to Te content in chalcogenide materials in accordance with an embodiment of the disclosed technology. In fig. 4, the vertical axis represents normalized Vth, and the horizontal axis represents Te content. For example, the levels of the threshold voltages at the Te content of 0at%, 5at% and 10at% are each normalized by the level of the threshold voltage at the Te content of 0 at%.
Vth should be adjusted to an appropriate level to allow stable operation of the device containing the chalcogenide material. In particular, if Vth is excessively lowered, such a device may not function properly.
Referring to fig. 4, vth decreases as the Te content increases. This is because Eg decreases as the Te content increases (as shown in fig. 1). Therefore, it is considered to determine the maximum content of tellurium (Te) by prohibiting excessive decrease of Vth and keeping Vth at a sufficiently high level to ensure stable operation.
Fig. 5 shows normalized Vth distribution according to Te content in chalcogenide material in accordance with an embodiment of the disclosed technology. In fig. 5, the vertical axis represents the normalized Vth distribution, and the horizontal axis represents the Te content.
The Vth distribution may represent the degree of variation of Vth from repeated measurements of Vth. For example, after a given number of switching operations are performed, the value of the Vth distribution may be the variance (variance) of the threshold voltages in the plurality of select elements. Each of the plurality of select elements may include a chalcogenide material having a particular Te content. The values of the Vth distribution at Te contents of 0at%, 5at% and 10at% can be normalized by the values of the Vth distribution at Te contents of 0 at%. In order to improve device characteristics, it may be desirable to reduce the extent of Vth variation.
Referring to fig. 5, as the Te content increases, the Vth distribution decreases. Without being limited by theory, it is believed that Te doping causes the phonon frequency to be relatively low to reduce irregular collisions, thereby reducing Vth distribution.
When the Te content increases, vth distribution improves, but off-current may increase and Vth may excessively decrease. As a result, it may be difficult to ensure stable operation of the device. Accordingly, it is desirable to determine the Te content in consideration of the overall characteristics of the device. For example, the Te content can be selected to exhibit the beneficial effect of improving Vth distribution and reducing degradation of other device characteristics.
The chalcogenide material according to the above-described embodiment may include silicon (Si), germanium (Ge), arsenic (As), selenium (Se), and tellurium (Te) As constituent elements, wherein the content of each constituent element may be selected to exhibit an optimal effect in consideration of balancing the overall characteristics of the device. For example, the silicon (Si) content may be selected to substantially suppress voltage drift acceleration and reduce degradation of other device characteristics. Also, the tellurium (Te) content may be selected to exhibit the beneficial effects of improving the Vth distribution and reducing degradation of other device characteristics.
Chalcogenide materials can be prepared by various methods such as Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), ion implantation, and the like.
In one embodiment, the Si-Ge-As-Se-Te chalcogenide material may be formed via a physical deposition process (e.g., a sputtering process) by using SIGEASSETE alloy targets.
In another embodiment, the Si-Ge-As-Se-Te chalcogenide material may be formed via a physical deposition process (e.g., a co-sputtering process) using a Te target and SiGeAsSe alloy target.
In yet another embodiment, the Si-Ge-As-Se-Te chalcogenide material may be formed by adding Te to a Si-Ge-As-Se material using a sputtering process, an ion implantation process, or both.
In yet another embodiment, the Si-Ge-As-Se-Te chalcogenide material may be formed by depositing a Te layer and SiGeAsSe layers and performing a heat treatment to cause a reaction between the Te layer and SiGeAsSe layers.
In yet another embodiment, the Si-Ge-As-Se-Te chalcogenide material may be formed by depositing a plurality of Te layers and a plurality of SiGeAsSe layers and performing a heat treatment to cause a reaction between the Te layers and SiGeAsSe layers.
An element containing a chalcogenide material according to one embodiment may be used as a switching element according to the type and composition ratio of constituent elements. Switching elements using chalcogenides may include Ovonic Memory Switching (OMS) elements and Ovonic Threshold Switching (OTS) elements. For OMS elements, the phase of the material is changed when a pulse is applied to the OMS element. When a pulse is applied to the OTS element, the electrical characteristics change from a non-conductive state to a conductive state in a single phase (typically an amorphous phase), and when the pulse is removed, it returns to its original non-conductive state. OTS elements may have a high resistance in response to voltages less than a given threshold voltage (Vth). When a voltage greater than Vth is applied, current flows through the OTS element at a substantially constant relatively low voltage, and the OTS element exhibits low impedance. When the current through the OTS element becomes lower than the holding current (holding current), the OTS element returns to the high-impedance state. Such I-V characteristics of OTS elements may be substantially symmetrical.
Hereinafter, an electronic device including the switching element containing a chalcogenide material according to the above-described embodiment will be described.
Fig. 6 is a perspective view of a semiconductor memory according to an embodiment of the disclosed technology.
The semiconductor memory according to the embodiment in fig. 6 of the present disclosure may have a cross-point structure including: first lines 110 each extending in a first direction; a second line 150 located above the first line 110 and each extending in a second direction crossing the first direction; and a memory cell 120 located between the first line 110 and the second line 150. The memory cells 120 are disposed at respective intersections of the first lines 110 and the second lines 150.
Fig. 7A to 7D are cross-sectional views illustrating a semiconductor memory and a method for manufacturing the semiconductor memory according to an embodiment of the disclosed technology.
Fig. 7D is a cross-sectional view of a portion of the semiconductor device taken along line A-A' of fig. 6.
Referring to fig. 7A, a substrate 100 may be provided that includes a given structure (not shown). For example, a given structure may include one or more transistors for controlling the first line 110, the second line 150, or the first line 110 and the second line 150 of fig. 6 and 7D formed over the substrate 100.
Then, first lines 110 each extending in a first direction (e.g., a horizontal direction in fig. 7A) may be formed on the substrate 100. The first line 110 may have a single-layer structure or a multi-layer structure, and may include a conductive material such as a metal, a metal nitride, or the like. The first line 110 may be formed by depositing a layer including a conductive material and patterning the deposited layer. The space between the first lines 110 may be filled with an insulating material (not shown).
Then, a plurality of memory cells 120 may be formed over the first line 110. In the embodiment shown in fig. 7A, each of the plurality of memory cells 120 may have a pillar shape. The plurality of memory cells 120 may be arranged in a matrix having rows and columns. The rows each extend in a first direction and the columns each extend in a second direction that intersects the first direction. The memory cells 120 may be disposed in respective crossing regions between the first line 110 and the second line 150. The crossing region between one of the first lines 110 and one of the second lines 150 is defined as, for example, a three-dimensional region in which the first lines 110 and the second lines 150 overlap each other in a third direction (for example, a vertical direction in fig. 7A) crossing the first direction and the second direction. In one embodiment, the size of each memory cell 120 may be substantially equal to or less than the size of the intersection area between the corresponding pair of first lines 110 and second lines 150. In another embodiment, the size of each memory cell 120 may be greater than the size of the intersection area between each corresponding pair of first lines 110 and second lines 150.
The memory cell 120 may be formed by: a plurality of material layers (not shown) are deposited over the structure including the first line 110 and the insulating material (not shown), a plurality of hard mask patterns 130 are formed on the plurality of material layers, and the material layers are etched using the hard mask patterns 130 as an etch barrier. Accordingly, each hard mask pattern 130 has sidewalls substantially aligned with sidewalls of each corresponding memory cell 120.
The hard mask pattern 130 may serve as an etch stop layer during etching of a material layer (not shown) used to form the memory cell 120, and include one or more of various materials having etch selectivity with respect to the memory cell 120. For example. Each hard mask pattern 130 may have a single-layer structure or a multi-layer structure, and include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.
Further, in the embodiment of fig. 7A, each of the plurality of memory cells 120 may include a lower electrode layer 121, a selection element layer 123, an intermediate electrode layer 125, a variable resistance layer 127, and an upper electrode layer 129, which are sequentially stacked.
Specifically, the lower electrode layer 121 may be located at the lowermost portion of each memory cell 120 and serve as a transmission path of voltage or current between a corresponding one of the first lines 110 and the rest of each memory cell 120 (e.g., layers 123, 125, 127, and 129). The intermediate electrode layer 125 may physically separate the selection element layer 123 from the variable resistance layer 127 and electrically couple the selection element layer 123 to the variable resistance layer 127. For example, when the voltage level across the selection element layer 123 is equal to or greater than a given threshold voltage, a current flows through the selection element layer 123, the intermediate electrode layer 125, and the variable resistance layer 127. The upper electrode layer 129 may be located at an uppermost portion of each memory cell 120 and serve as a transmission path of voltage or current between the remaining portion of each memory cell 120 (e.g., layers 121, 123, 125, and 127) and a corresponding one of the second lines 150 of fig. 7D. Each of the lower electrode layer 121, the intermediate electrode layer 125, and the upper electrode layer 129 may have a single-layer structure or a multi-layer structure, and may include a conductive material such as a metal, a metal nitride, a conductive carbon material, or the like.
The selection element layer 123 can control access to the variable resistance layer 127. That is, the selection element layer 123 may function as a switching element and have selection element characteristics that substantially prevent current from passing through the selection element layer 123 when the magnitude of an applied voltage or an applied current is below a critical value (or threshold value), and that allow current to pass through the selection element layer 123 when the magnitude of an applied voltage or an applied current is substantially equal to or greater than the critical value. For example, the magnitude of the current passing through the selection element layer 123 is proportional to the magnitude of the voltage or current applied to the selection element layer 123. The selection element layer 123 may have a single-layer structure or a multi-layer structure that exhibits selection element characteristics using a combination of two or more layers.
For example, the selection element layer 123 may include a chalcogenide material according to the above-described embodiments. Specifically, in an embodiment of the disclosed technology, the selection element layer 123 may include a chalcogenide material including 1-10at% silicon (Si), 10-20at% germanium (Ge), 25-35at% arsenic (As), 40-50at% selenium (Se), and 1-10at% tellurium (Te). Further, in an embodiment of the disclosed technology, the selection element layer 123 may include a chalcogenide material including 1-5at% silicon (Si), 15-20at% germanium (Ge), 25-30at% arsenic (As), 42-47at% selenium (Se), and 3-7at% tellurium (Te). Further, in embodiments of the disclosed technology, the select element layer 123 may include a chalcogenide material including about 1.5at% silicon (Si), about 19.5at% germanium (Ge), about 29.0at% arsenic (As), about 45.0at% selenium (Se), and about 5.0at% tellurium (Te). Such chalcogenide materials have been described in detail in the above embodiments, and a detailed description thereof is omitted for the sake of brevity.
As described above, the chalcogenide material included in the selection element layer 123 may include silicon (Si), germanium (Ge), arsenic (As), selenium (Se), and tellurium (Te) As constituent elements, wherein the content of each constituent element may be selected to exhibit an optimal effect in consideration of the overall characteristics of the balance device. For example, the silicon (Si) content may be selected to substantially suppress voltage drift acceleration and reduce degradation of other device characteristics. Also, tellurium (Te) content may be selected to improve Vth distribution and reduce degradation of other device characteristics. Therefore, the voltage drift acceleration can be effectively suppressed in both cases of a relatively short delay time and a relatively long delay time, the Vth distribution can be effectively improved, and deterioration of other device characteristics can be substantially prevented, resulting in excellent device characteristics and improved device reliability.
The variable resistance layer 127 may be switched between different resistance states according to a voltage or current applied to the variable resistance layer 127 via the upper electrode layer 129 and the intermediate electrode layer 125, thereby storing data having different values. For example, when the variable resistance layer 127 is in a low resistance state, data having a first logic value "1" may be stored in the variable resistance layer 127. On the other hand, when the variable resistance layer 127 is in a high resistance state, data having a second logical value "0" may be stored in the variable resistance layer 127. The variable resistance layer 127 may include one or more of various materials for RRAM, PRAM, FRAM or MRAM, etc. For example, the variable resistance layer 127 may include: any of the metal oxides, such as transition metal oxides or perovskite-based materials; phase change materials, such as chalcogenide based materials; a ferroelectric material, a ferromagnetic material; etc. The variable resistance layer 127 may have a single-layer structure or a multi-layer structure that exhibits variable resistance characteristics by a combination of two or more layers. However, other embodiments are also possible. For example, the memory cell 120 may include a memory layer that may store data in a different manner than the variable resistance layer 127 described above.
In the embodiment shown in fig. 7A, each memory cell 120 includes a lower electrode layer 121, a selection element layer 123, an intermediate electrode layer 125, a variable resistance layer 127, and an upper electrode layer 129. However, the embodiments of the present patent document are not limited thereto, and the storage unit 120 may have various structures. In some embodiments, one or more of the lower electrode layer 121, the intermediate electrode layer 125, and the upper electrode layer 129 may be omitted. In some embodiments, the order of stacking the selection element layer 123 and the variable resistance layer 127 may be reversed with respect to the orientation shown in fig. 7A, so that the selection element layer 123 may be disposed over the variable resistance layer 127. In some embodiments, memory cell 120 may include one or more layers (not shown) in addition to layers 121, 123, 125, 127, and 129 shown in fig. 7A to enhance characteristics of memory cell 120, improve manufacturing processes, or both.
An adjacent pair of the plurality of memory cells 120 may be spaced apart from each other at a given interval, and a trench may exist between the plurality of memory cells 120. In one embodiment, the given spacing is a predetermined spacing, and the aspect ratio (or aspect ratio) of the trench between an adjacent pair of the plurality of memory cells 120 may be within the following range: from 1:1 to 40:1, from 10:1 to 20:1, from 5:1 to 10:1, from 10:1 to 15:1, from 1:1 to 25:1, from 1:1 to 30:1, from 1:1 to 35:1, or from 1:1 to 45:1.
In some embodiments, the trench may have sidewalls that are substantially perpendicular to the upper surface of the substrate 100. In some embodiments, adjacent grooves may be substantially equally spaced from one another. For example, a first pair of grooves adjacent to each other in a first direction (e.g., the first direction of fig. 6) may be spaced apart from each other by substantially the same distance as a second pair of grooves adjacent to each other in a second direction (e.g., the second direction of fig. 6). In some embodiments, the distance between adjacent trenches may vary.
Referring to fig. 7B, an interlayer dielectric layer 140 may be formed over the structure shown in fig. 7A. The interlayer dielectric layer 140 may include various insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and the like. In addition, the interlayer dielectric layer 140 may be formed along the lower profile. For example, an interlayer dielectric layer 140 is formed on the first line 110, sidewalls of the memory cells 120, and upper surfaces and sidewalls of the hard mask pattern 130.
Referring to fig. 7C, a planarization process may be performed on the interlayer dielectric layer 140 until the upper electrode layer 129 is exposed. The planarization process may be performed by a Chemical Mechanical Polishing (CMP) process, an etching process, a cleaning process, or any suitable planarization process. Since the planarization process is performed until the upper surface of the upper electrode layer 129 of the memory cell 120 is exposed, the hard mask pattern 130 may be removed through the planarization process.
Referring to fig. 7D, a plurality of second lines 150 may be formed over the memory cells 120 and the interlayer dielectric layer 140. The plurality of second lines 150 may be coupled to upper surfaces of the memory cells 120, respectively. The plurality of second lines 150 each extend in a second direction intersecting the first direction. For example, the second direction may be perpendicular to line A-A' of FIG. 6. Each of the second lines 150 may have a single-layer structure or a multi-layer structure, and include a conductive material such as any one of a metal and a metal nitride. The second line 150 may be formed by depositing a conductive material and patterning the deposited material. The spaces between adjacent second lines 150 may be filled with an insulating material (not shown).
The semiconductor memory shown in fig. 7D can be manufactured by the process described above.
In the embodiment shown in fig. 7D, the semiconductor memory (or semiconductor memory device) may include memory cells 120 disposed at crossing regions between first lines 110 each extending in a first direction and second lines 150 each extending in a second direction. In one embodiment, the select element layer 123 of the memory cell 120 may include a chalcogenide material including 1-10at% silicon (Si), 10-20at% germanium (Ge), 25-35at% arsenic (As), 40-50at% selenium (Se), and 1-10at% tellurium (Te). In one embodiment, the select element layer 123 of the memory cell 120 may include a chalcogenide material including 1-5at% silicon (Si), 15-20at% germanium (Ge), 25-30at% arsenic (As), 42-47at% selenium (Se), and 2-8at% tellurium (Te).
The memory cell 120 may store data having different values according to voltages or currents applied thereto via the first line 110 and the second line 150. Specifically, when the memory cells 120 each include a variable resistance element, each memory cell 120 may store data by switching between different resistance states.
One or more first lines 110 may each function as a word line and one or more second lines 150 may each function as a bit line, or vice versa.
In the semiconductor memory of fig. 7D manufactured by the method according to the embodiment of the present disclosure, the selection element layer 123 of the memory cell 120 includes a chalcogenide material having a specific composition of four components, so that an optimal effect can be exhibited in various aspects of device characteristics (such as voltage drift, vth, VFF, ioff, vth distribution, durability, and the like).
Fig. 8 is a cross-sectional view illustrating a semiconductor memory according to an embodiment of the disclosed technology. For brevity, a detailed description of portions substantially identical to those of the embodiment described above with reference to fig. 7A to 7D will be omitted.
Referring to fig. 8, a capping layer 160 may also be formed on sidewalls of the memory cell 120 and over the first line 110. The capping layer 160 may be used to protect the memory cell 120 and have a single-layer structure or a multi-layer structure including various insulating materials such as silicon nitride and the like.
The cover layer 160 may be formed by: the processes of fig. 7B to 7D are then performed by forming a material layer for the capping layer 160 over the structure of fig. 7A (e.g., on the sidewalls of the memory cell 120 and the sidewalls and upper surface of the hard mask pattern 130).
As a result, first lines 110 each extending in a first direction (e.g., the first direction of fig. 6) and second lines 150 each extending in a second direction (e.g., the second direction of fig. 6) are formed over the substrate 100, and the memory cells 120 may be disposed in respective crossing regions between the first lines 110 and the second lines 150. In one embodiment, the select element layer 123 of each memory cell 120 may comprise a chalcogenide material comprising 1-10at% Si, 10-20at% Ge, 25-35at% As, 40-50at% Se, and 1-10at% Te. In one embodiment, the select element layer 123 of each memory cell 120 may comprise a chalcogenide material comprising 1-5at% silicon (Si), 15-20at% germanium (Ge), 25-30at% arsenic (As), 42-47at% selenium (Se), and 2-8at% tellurium (Te).
The sidewalls of the memory cells 120 may be in direct contact with the capping layer 160. The capping layer 160 may include an insulating material and serve to protect the memory cell 120.
In the embodiments shown in fig. 6 to 8, a semiconductor memory having a single-layer cross-point structure has been described. However, in another embodiment, the semiconductor memory may have a multi-layer cross-point structure in which two or more cross-point structures may be stacked. Each cross-point structure may include a first line 110, a second line 150, and a memory cell 120 located at a respective cross-point between the first line 110 and the second line 150.
Memory circuits or semiconductor devices according to embodiments based on the disclosed technology may be used in a range of devices or systems. Fig. 9-13 provide some examples of devices or systems in which the memory circuits disclosed herein may be implemented.
Fig. 9 is an example of a configuration diagram of a microprocessor implementing a memory circuit based on the disclosed technology.
Referring to FIG. 9, microprocessor 1000 may perform the following tasks: a series of processes for controlling and tuning reception of data from various external devices, processing of the data, and outputting of the processing result to the external devices. Microprocessor 1000 may include a memory unit 1010, an operation unit 1020, a control unit 1030, and the like. Microprocessor 1000 may be a variety of data processing units such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), and an Application Processor (AP).
Memory unit 1010 is the portion of microprocessor 1000 that stores data, such as processor registers or registers. The storage unit 1010 may include data registers, address registers, floating point registers, and the like. Further, the storage unit 1010 may include various registers. The storage unit 1010 may perform the following functions: data for performing an operation by the operation unit 1020, result data for performing the operation, and an address where the data for performing the operation are stored are temporarily stored.
The memory cell 1010 may include one or more of the above-described semiconductor devices according to embodiments. For example, memory cell 1010 may include a plurality of memory cells, each memory cell including a switching element, wherein the switching element may include a chalcogenide material including 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium. Thereby, the data storage characteristics of the memory cell 1010 can be improved. As a result, the operating characteristics of microprocessor 1000 can be improved.
The operation unit 1020 may perform a four-bit arithmetic operation or a logical operation according to the result of decoding the command by the control unit 1030. The operation unit 1020 may include at least one Arithmetic Logic Unit (ALU), or the like.
The control unit 1030 may receive signals from the storage unit 1010, the operation unit 1020, and external devices of the microprocessor 1000, perform extraction of commands, decoding, and control of input and output of signals to the microprocessor 1000, and execute processing represented by programs.
The microprocessor 1000 according to this embodiment may additionally include a cache memory unit 1040 that may temporarily store data to be input from an external device other than the memory unit 1010 or data to be output to the external device. In this case, the cache memory unit 1040 may exchange data with the memory unit 1010, the operation unit 1020, and the control unit 1030 via the bus interface 1050.
Fig. 10 is an example of a configuration diagram of a processor implementing a memory circuit in accordance with an embodiment of the disclosed technology.
Referring to fig. 10, a processor 1100 may improve performance and implement multi-functions by including various functions in addition to those of a microprocessor that performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting the processing results to the external devices. The processor 1100 may include a core unit 1110 functioning as a microprocessor, a cache unit 1120 for temporarily storing data, and a bus interface 1130 for transferring data between an internal device and an external device. The processor 1100 may include various systems on a chip (SoC) such as a multi-core processor, a Graphics Processing Unit (GPU), and an Application Processor (AP).
The core unit 1110 of this embodiment is a component that performs arithmetic logic operation on data input from an external device, and may include a storage unit 1111, an operation unit 1112, and a control unit 1113.
The memory unit 1111 is a means for storing data in the processor 1100, such as a processor register or registers, etc. The storage unit 1111 may include a data register, an address register, a floating point register, and the like. Further, the storage unit 1111 may include various registers. The storage unit 1111 may perform the following functions: data for performing an operation by the operation unit 1112, result data for performing the operation, and an address where the data for performing the operation is stored are temporarily stored. The operation unit 1112 is a component that performs operations in the processor 1100. The operation unit 1112 may perform four arithmetic operations, logical operations, or the like according to the result of decoding the command by the control unit 1113. The operation unit 1112 may include at least one Arithmetic Logic Unit (ALU) or the like. The control unit 1113 may receive signals from the storage unit 1111, the operation unit 1112, and external devices of the processor 1100, perform extraction and decoding of commands, control of input and output of signals to the processor 1100, and execute processing represented by programs.
The cache memory unit 1120 is a part that temporarily stores data to compensate for a difference in data processing speed between the core unit 1110 operating at a high speed and an external device operating at a low speed. The cache memory unit 1120 may include a main storage 1121, a secondary storage 1122, and a tertiary storage 1123. In general, the cache memory unit 1120 includes a main storage 1121 and a secondary storage 1122, and may include a tertiary storage 1123 in the case where a high storage capacity is required. The cache unit 1120 may include an increased number of storage portions as the case may be. That is, the number of storage parts included in the cache memory unit 1120 may be changed according to design. The speeds at which the main storage portion 1121, the secondary storage portion 1122, and the tertiary storage portion 1123 store and differentiate data may be the same or different. In the case where the speeds of the respective storage portions 1121, 1122, and 1123 are different, the speed of the main storage portion 1121 may be maximized. At least one storage part of the main storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory unit 1120 may include one or more of the above-described semiconductor devices according to an embodiment. For example, cache memory unit 1120 may include a plurality of memory cells, each memory cell including a switching element, wherein the switching element may include a chalcogenide material including 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium. Thus, the data storage characteristics of the cache memory unit 1120 can be improved. As a result, the operation characteristics of the processor 1100 may be improved.
Although it is shown in fig. 10 that the main storage 1121, the secondary storage 1122, and the tertiary storage 1123 are all arranged inside the cache memory unit 1120, it should be noted that the main storage 1121, the secondary storage 1122, and the tertiary storage 1123 of the cache memory unit 1120 may all be arranged outside the core unit 1110, and a difference in data processing speed between the core unit 1110 and an external device may be compensated for. Meanwhile, it is noted that the main storage portion 1121 of the cache memory unit 1120 may be provided inside the core unit 1110, and the secondary storage portion 1122 and the tertiary storage portion 1123 may be configured outside the core unit 1110 to enhance a function of compensating for a difference in data processing speed. In another embodiment, the main storage 1121 and the secondary storage 1122 may be provided inside the core unit 1110, and the tertiary storage 1123 may be provided outside the core unit 1110.
Bus interface 1130 is a component that connects core unit 1110, cache unit 1120, and external devices and allows efficient transfer of data.
The processor 1100 according to this embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share the cache unit 1120. The plurality of core units 1110 and cache units 1120 may be connected directly or via bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the above-described configuration of the core units 1110. In the case where the processor 1100 includes a plurality of core units 1110, the main storage 1121 of the cache memory unit 1120 may be configured in each core unit 1110 in correspondence with the number of the plurality of core units 1110, and the secondary storage 1122 and the tertiary storage 1123 may be configured outside the plurality of core units 1110 in a shared manner through the bus interface 1130. The processing speed of the main storage portion 1121 may be greater than the processing speeds of the secondary storage portion 1122 and the tertiary storage portion 1123. In another embodiment, the main storage 1121 and the secondary storage 1122 may be configured in each core unit 1110 corresponding to the number of the plurality of core units 1110, and the tertiary storage 1123 may be configured outside the plurality of core units 1110 in a shared manner through the bus interface 1130.
The processor 1100 according to this embodiment may further include: an embedded storage unit 1140, which stores data; a communication module unit 1150 capable of transmitting and receiving data to and from an external device in a wired or wireless manner; a memory control unit 1160 which drives the external memory device; and a media processing unit 1170 that processes data processed in the processor 1100 or data input from an external input device, and outputs the processed data to an external interface device or the like. Further, the processor 1100 may include a number of various modules and devices. In this case, the added modules may exchange data with the core unit 1110 and the cache unit 1120 via the bus interface 1130 and each other.
The embedded storage unit 1140 may include not only volatile memory but also nonvolatile memory. Volatile memory may include DRAM (dynamic random access memory), mobile DRAM, SRAM (static random access memory), memory having similar functions to the above-described memory, and the like. The nonvolatile memory may include: ROM (read only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive Random Access Memory (RRAM), spin Transfer Torque Random Access Memory (STTRAM), magnetic Random Access Memory (MRAM), memory with similar functionality.
The communication module unit 1150 may include a module capable of connecting with a wired network, a module capable of connecting with a wireless network, and both. The wired network module may include a Local Area Network (LAN), a Universal Serial Bus (USB), an ethernet, a Power Line Communication (PLC), various devices such as transmitting and receiving data via a transmission line, and the like. The wireless network module may include: infrared data association (IrDA), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), frequency Division Multiple Access (FDMA), wireless LAN, zigbee, ubiquitous Sensor Network (USN), bluetooth, radio Frequency Identification (RFID), long Term Evolution (LTE), near Field Communication (NFC), wireless broadband internet (Wibro), high Speed Downlink Packet Access (HSDPA), wideband CDMA (WCDMA), ultra Wideband (UWB), various devices such as transmitting and receiving data without a transmission line, and the like.
The memory control unit 1160 is used to manage and process data transferred between the processor 1100 and external storage devices operating according to different communication standards. The memory control unit 1160 may include various memory controllers, for example, devices that may control IDE (integrated electronics), SATA (serial advanced technology attachment), SCSI (small computer system interface), RAID (redundant array of independent disks), SSD (solid state disk), eSATA (external SATA), PCMCIA (personal computer memory card international association), USB (universal serial bus), secure Digital (SD) card, mini secure digital (mSD) card, micro secure digital (micro SD) card, secure Digital High Capacity (SDHC) card, memory stick card, smart Media (SM) card, multimedia card (MMC), embedded MMC (eMMC), compact Flash (CF) card, and the like.
The media processing unit 1170 may process data processed in the processor 1100 or data input in the form of images, voice, and other forms from an external input device and output the data to an external interface device. The media processing unit 1170 may include a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), a high definition audio device (HD audio), a High Definition Multimedia Interface (HDMI) controller, and the like.
Fig. 11 is an example of a configuration diagram of a system implementing a memory circuit in accordance with an embodiment of the disclosed technology.
Referring to fig. 11, a system 1200 as a means for processing data may perform input, processing, output, communication, storage, etc. to perform a series of manipulations on the data. The system 1200 may include a processor 1210, a primary storage device 1220, a secondary storage device 1230, an interface device 1240, and the like. The system 1200 of this embodiment may be various electronic systems that operate using a processor, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a Global Positioning System (GPS), a video camera, a recorder, a telematics, an audio-visual (AV) system, a smart television, and so forth.
Processor 1210 may decode the entered commands and process operations, comparisons, etc., for data stored in system 1200 and control these operations. Processor 1210 may include: microprocessor units (MPUs), central Processing Units (CPUs), single/multi-core processors, graphics Processing Units (GPUs), application Processors (APs), and Digital Signal Processors (DSPs), among others.
The main storage device 1220 is a storage that can temporarily store, call and run program codes or data from the auxiliary storage device 1230 when running a program and can save the stored contents even when power is cut off. The main memory device 1220 may include a plurality of memory cells, each including a switching element, wherein the switching element may include a chalcogenide material including 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium. Thereby, the data storage characteristics of the main memory device 1220 can be improved. As a result, the operating characteristics of the system 1200 may be improved.
In addition, the main memory device 1220 may further include a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), etc. of a volatile memory type, in which all contents are erased when power is cut off. In contrast, the main memory device 1220 may not include the semiconductor device according to the embodiment, but may include a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), and the like of a volatile memory type, in which all contents are erased when power is turned off.
The secondary storage device 1230 is a storage device for storing program code or data. Although the secondary storage device 1230 is slower than the primary storage device 1220, the secondary storage device 1230 may store a greater amount of data. The auxiliary storage device 1230 may include one or more of the above-described semiconductor devices according to embodiments. For example, the auxiliary memory device 1230 may include a plurality of memory cells, each memory cell including a switching element, wherein the switching element may include a chalcogenide material including 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium. Thereby, the data storage characteristics of the auxiliary storage device 1230 can be improved. As a result, the operating characteristics of the system 1200 may be improved.
In addition, the secondary storage device 1230 may also include a data storage system (see reference numeral 1300 of fig. 12), such as a magnetic tape, a magnetic disk, a laser disk using optics, a magneto-optical disk using both magnetism and optics, a Solid State Disk (SSD), a USB memory (universal serial bus memory), a Secure Digital (SD) card, a mini-secure digital (mSD) card, a micro-secure digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a Compact Flash (CF) card, etc. In contrast, the secondary storage device 1230 may not include the semiconductor device according to the embodiment, but may include a data storage system (see reference numeral 1300 of fig. 12) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disk using both magnetism and optics, a Solid State Disk (SSD), a USB memory (universal serial bus memory), a Secure Digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a Compact Flash (CF) card, and the like.
The interface device 1240 may be used to perform exchanges of commands and data between the system 1200 of this embodiment and external devices. Interface device 1240 may be a keypad, keyboard, mouse, speaker, microphone, display, various Human Interface Devices (HIDs), and communications devices, among others. The communication device may include a module capable of connecting to a wired network, a module capable of connecting to a wireless network, and both. The wired network module may include a Local Area Network (LAN), a Universal Serial Bus (USB), an ethernet, a Power Line Communication (PLC), various devices such as transmitting and receiving data through a transmission line, and the like. The wireless network module may include: infrared data association (IrDA), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), frequency Division Multiple Access (FDMA), wireless LAN, zigbee, ubiquitous Sensor Network (USN), bluetooth, radio Frequency Identification (RFID), long Term Evolution (LTE), near Field Communication (NFC), wireless broadband internet (Wibro), high Speed Downlink Packet Access (HSDPA), wideband CDMA (WCDMA), ultra Wideband (UWB), various devices such as transmitting and receiving data without a transmission line, and so forth.
Fig. 12 is an example of a configuration diagram of a data storage system implementing a memory circuit in accordance with an embodiment of the disclosed technology.
Referring to fig. 12, a data storage system 1300 may include: a storage device 1310 having a nonvolatile characteristic as a component for storing data; a controller 1320 that controls the storage device 1310; an interface 1330 for connecting with an external device; and a temporary storage device 1340 for temporarily storing data. The data storage system 1300 may be of a disk type such as a Hard Disk Drive (HDD), compact Disk Read Only Memory (CDROM), digital Versatile Disk (DVD), and Solid State Disk (SSD), etc., and may be of a card type such as a USB memory (universal serial bus memory), a Secure Digital (SD) card, a mini-secure digital (MSD) card, a micro-secure digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a Compact Flash (CF) card, etc.
Storage 1310 may include nonvolatile memory that semi-permanently stores data. The nonvolatile memory may include: ROM (read only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive Random Access Memory (RRAM), and Magnetic Random Access Memory (MRAM), etc.
The controller 1320 may control the exchange of data between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing the following operations: processes commands and the like input from outside the data storage system 1300 through the interface 1330.
Interface 1330 is used to perform exchanges of commands and data between data storage system 1300 and external devices. In the case where the data storage system 1300 is of a card type, the interface 1330 may be compatible with interfaces used in devices such as USB memory (universal serial bus memory), secure Digital (SD) card, mini-secure digital (MSD) card, micro-secure digital (micro SD) card, secure Digital High Capacity (SDHC) card, memory stick card, smart Media (SM) card, multimedia card (MMC), embedded MMC (eMMC), compact Flash (CF) card, etc., or with interfaces used in devices similar to those described above. In the case where data storage system 1300 is of the disk type, interface 1330 may be compatible with the following interfaces: such as IDE (integrated electronics), SATA (serial advanced technology attachment), SCSI (small computer system interface), eSATA (external SATA), PCMCIA (personal computer memory card international association), and USB (universal serial bus), etc., or is compatible with interfaces similar to those described above. Interface 1330 may be compatible with one or more interfaces having different types from each other.
Temporary storage 1340 may temporarily store data to efficiently transfer data between interface 1330 and storage 1310 according to the variety and high performance of interfaces with external devices, controllers, and systems. The temporary storage device 1340 for temporarily storing data may include one or more of the above-described semiconductor devices according to embodiments. Temporary storage device 1340 may include a plurality of memory cells, each of which includes a switching element, where the switching element may include a chalcogenide material including 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium. Thereby, data storage characteristics of the storage device 1310 or the temporary storage device 1340 can be improved. As a result, the operating characteristics and data storage characteristics of the data storage system 1300 may be improved.
Fig. 13 is an example of a configuration diagram of a memory system implementing a memory circuit based on an embodiment of the disclosed technology.
Referring to fig. 13, a storage system 1400 may include: a memory 1410 having a nonvolatile characteristic as a component for storing data; a memory controller 1420 controlling the memory 1410; and an interface 1430 for connecting with an external device, and the like. The storage system 1400 may be of a card type such as a Solid State Disk (SSD), USB memory (universal serial bus memory), secure Digital (SD) card, mini-secure digital (MSD) card, micro-secure digital (micro SD) card, secure Digital High Capacity (SDHC) card, memory stick card, smart Media (SM) card, multimedia card (MMC), embedded MMC (eMMC), and Compact Flash (CF) card, among others.
The memory 1410 for storing data may include one or more of the above-described semiconductor devices according to embodiments. For example, memory 1410 may include a plurality of memory cells, each memory cell including a switching element, wherein the switching element may include a chalcogenide material including 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium. Thus, the data storage characteristics of the memory 1410 may be improved. As a result, the operation characteristics and data storage characteristics of the memory system 1400 may be improved.
In addition, the memory 1410 according to the embodiment may further include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a Magnetic Random Access Memory (MRAM), and the like having nonvolatile characteristics.
Memory controller 1420 may control the exchange of data between memory 1410 and interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing the following operations: commands input from outside the memory system 1400 via the interface 1430 are processed.
Interface 1430 is used to perform exchanges of commands and data between storage system 1400 and external devices. The interface 1430 may be compatible with interfaces used in devices such as USB memory (universal serial bus memory), secure Digital (SD) card, mini-secure digital (MSD) card, micro-secure digital (micro SD) card, secure Digital High Capacity (SDHC) card, memory stick card, smart Media (SM) card, multimedia card (MMC), embedded MMC (eMMC), and Compact Flash (CF) card, etc., or with interfaces used in devices similar to those described above. Interface 1430 may be compatible with one or more interfaces having different types from each other.
The memory system 1400 according to this embodiment may further include a buffer memory 1440 for efficiently transferring data between the interface 1430 and the memory 1410 according to the variety and high performance of interfaces with external devices, memory controllers, and memory systems. For example, the buffer memory 1440 for temporarily storing data may include one or more of the above-described semiconductor devices according to embodiments. Buffer memory 1440 may include a plurality of memory cells, each memory cell including a switching element, wherein the switching element may include a chalcogenide material including 1-10 atomic percent (at%) silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium. Thus, the data storage characteristics of the buffer memory 1440 can be improved. As a result, the operation characteristics and data storage characteristics of the memory system 1400 may be improved.
In addition, the buffer memory 1440 according to this embodiment may further include SRAM (static random access memory) and DRAM (dynamic random access memory) or the like having volatile characteristics, and phase change random access memory (PRAM), resistive Random Access Memory (RRAM), spin Transfer Torque Random Access Memory (STTRAM), magnetic Random Access Memory (MRAM) or the like having nonvolatile characteristics. In contrast, the buffer memory 1440 may not include the semiconductor device according to the embodiment, but may include SRAM (static random access memory) and DRAM (dynamic random access memory) or the like having volatile characteristics, and phase change random access memory (PRAM), resistive Random Access Memory (RRAM), spin Transfer Torque Random Access Memory (STTRAM), magnetic Random Access Memory (MRAM) or the like having nonvolatile characteristics.
The features of the above examples of electronic devices or systems in fig. 9-13 based on the memory devices disclosed in this document may be implemented in various devices, systems, or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or laptop computers, gaming machines, smart televisions, television set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, wristwatches or other wearable devices with wireless communication capabilities.
Although this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as features specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Furthermore, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only some embodiments and examples are described. Other embodiments, enhancements, and variations can be made based on what is described and illustrated in this patent document.

Claims (18)

1. A chalcogenide material comprising 1-5 atomic percent at% silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium,
Wherein the total atomic percent of silicon, germanium, arsenic, selenium and tellurium is 100at%.
2. The chalcogenide material of claim 1, wherein the germanium is present in an amount of 15-20at%.
3. The chalcogenide material of claim 1, wherein arsenic is present in an amount of 25-30at%.
4. The chalcogenide material of claim 1, wherein the amount of selenium is 42-47at%.
5. The chalcogenide material of claim 1, wherein the tellurium is present in an amount of 2-8at%.
6. The chalcogenide material of claim 1, wherein the sum of the silicon content and the germanium content is 20at% or more.
7. An electronic device, comprising:
A switching element comprising a chalcogenide material comprising 1-5 atomic percent at% silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium;
a first electrode electrically coupled to the switching element; and
A second electrode electrically coupled to the switching element,
Wherein the total atomic percent of silicon, germanium, arsenic, selenium and tellurium is 100at%.
8. The electronic device of claim 7, wherein the germanium is present in an amount of 15-20at%.
9. The electronic device of claim 7, wherein the arsenic content is 25-30at%.
10. The electronic device of claim 7, wherein the selenium is present in an amount of 42-47at%.
11. The electronic device of claim 7, wherein the tellurium content is 2-8at%.
12. The electronic device of claim 7, wherein a sum of silicon content and germanium content is 20at% or more.
13. An electronic apparatus includes a semiconductor memory device including a first memory cell including a first switching element,
Wherein the first switching element comprises a chalcogenide material comprising 1-5 atomic percent at% silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium, and 1-10at% tellurium,
Wherein the total atomic percent of silicon, germanium, arsenic, selenium and tellurium is 100at%.
14. The electronic device according to claim 13, wherein the semiconductor memory device further comprises:
a second memory cell comprising a second switching element having a chalcogenide material comprising 1-5 atomic percent at% silicon, 10-20at% germanium, 25-35at% arsenic, 40-50at% selenium and 1-10at% tellurium, and
Wherein in the second memory cell, the total atomic percentage of silicon, germanium, arsenic, selenium and tellurium is 100at%,
Wherein the first memory cell and the second memory cell further comprise a first memory layer and a second memory layer, respectively, each of the first memory layer and the second memory layer being switched between different resistance states according to a voltage or a current applied thereto.
15. The electronic device of claim 14, wherein the first and second switching elements control access to the first and second storage layers, respectively.
16. The electronic device of claim 13, wherein the semiconductor memory device comprises a plurality of memory cells including the first memory cell,
Wherein the semiconductor memory device further comprises:
A plurality of first lines disposed between the substrate and the plurality of memory cells, each of the plurality of first lines extending in a first direction; and
A plurality of second lines disposed over the plurality of memory cells, each of the plurality of second lines extending in a second direction intersecting the first direction, an
Wherein the plurality of memory cells are disposed at respective intersections of the first lines and the second lines.
17. The electronic device according to claim 13, wherein the semiconductor memory device further comprises a cover layer provided at least on a side surface of the first memory cell.
18. The electronic device of claim 13, wherein a sum of silicon content and germanium content is 20at% or more.
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