CN110838435A - Epitaxial layer transfer method - Google Patents
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Abstract
The invention relates to an epitaxial layer transfer method, and belongs to the technical field of semiconductors. The epitaxial layer transfer method comprises the following steps: s1, forming a porous interface layer on the surface of the mother substrate; s2, growing an epitaxial layer on the porous interface layer; and S3, adhering the epitaxial layer to the supporting substrate through a bonding technology to perform epitaxial layer transfer, and then separating the epitaxial layer from the mother substrate. According to the invention, the porous silicon germanium alloy layer is added at the interface of the mother substrate and the epitaxial layer, so that the epitaxial layer can be conveniently transferred at a low temperature without H ion implantation, and the thermal budget and the processing cost are reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to an epitaxial layer transfer method.
Background
The manufacture of thin film semiconductors is a key step in the development of low cost flexible electronic and photovoltaic devices. Epitaxial growth has proven to be the most suitable way to produce such ultra-thin single crystal layers, since it allows perfect control of layer thickness and doping, and when performed at low temperatures (<200 ℃), epitaxy is a low cost process. The epitaxial layer needs to be transferred to a foreign carrier/support substrate (e.g., glass) to enable its use, and how to simply and efficiently effect the transfer of the epitaxial layer is a crucial step in the successful application of thin film semiconductors.
Various transfer methods have been proposed in the prior art, and the following three methods are commonly used. i) Smart-Cut process: a lift-off method for inducing deep lift-off regions by hydrogen implantation; this process tends to require higher annealing temperatures (>600 deg.C) and high dose H implant (1X 10)17cm-2) The separation of the epitaxial layer from the mother substrate can be realized and the epitaxial layer can be damaged to a certain extent. ii) porous silicon based processes: generating at least two regions of different porosity on the surface of the mother substrate by electrochemical etching in a hydrofluoric acid (HF) solution prior to epitaxy; this method requires the use of hazardous HF solutions and can damage the mother substrate affecting the lifetime of the mother substrate. iii) using the sacrificial film as a crystallization template for growth, etching or removing the crystallization template after obtaining the epitaxial layer, the method is mainly used for III-V semiconductor epitaxy.
Disclosure of Invention
The invention aims to provide a convenient and easy-to-implement epitaxial layer transfer method aiming at the problems in the prior art.
The purpose of the invention can be realized by the following technical scheme:
an epitaxial layer transfer method, comprising the steps of:
s1, forming a porous interface layer on the surface of the mother substrate;
s2, growing an epitaxial layer on the porous interface layer;
and S3, adhering the epitaxial layer to the supporting substrate through a bonding technology to perform epitaxial layer transfer, and then separating the epitaxial layer from the mother substrate.
Preferably, the mother substrate is subjected to a cleaning treatment to remove native oxides and surface contaminants before forming a porous interfacial layer on the surface; the cleaning treatment is usingHydrofluoric acid solution or fluorine-based plasma treatment, in which SiF can be used4And the like.
Preferably, the mother substrate is a silicon wafer substrate.
Preferably, the porous interface layer is a SiGe alloy layer having a porous structure.
Preferably, the thickness of the SiGe alloy layer is 13nm to 28nm, and the content of Ge in the SiGe alloy layer is 0.2 at.% to 2.0 at.% of Si.
Preferably, the SiGe alloy layer and the epitaxial layer are formed by PECVD method, and the SiGe alloy layer is prepared by adding GeH during the preparation process4And (4) obtaining.
Preferably, the SiGe alloy layer is formed under the following conditions: the temperature is 180-230 ℃, the total pressure is 1.7-2.3 Torr, and the power density is 30mW/cm2-40mW/cm2，SiH4The flow rate is 3.6-4.5 SCCM, H2Flow rate of 180SCCM-220SCCM, GeH4And H2The flow rate of the mixed gas is 0.6-1.3 SCCM, the growth time is 100-150 s, and the GeH4And H2In the mixed gas of (1), GeH4At H2The concentration in (a) is 0.7 at.% to 1.3 at.%.
Preferably, the epitaxial layer comprises a Si epitaxial layer, a SiGe epitaxial layer or a Ge epitaxial layer.
Preferably, when the epitaxial layer is a Si epitaxial layer, the epitaxial layer formation conditions are: the temperature is 180-230 ℃, the total pressure is 1.7-2.3 Torr, and the power density is 30mW/cm2-40mW/cm2，SiH4The flow rate is 3.6-4.5 SCCM, H2The flow rate is 180-220 SCCM, and the growth time is 1500-2200 s;
when the epitaxial layer is a SiGe epitaxial layer, the forming conditions of the epitaxial layer are as follows: the temperature is 180-230 ℃, the total pressure is 1.7-2.3 Torr, and the power density is 30mW/cm2-40mW/cm2，SiH4The flow rate is 3.6-4.5 SCCM, H2Flow rate of 180SCCM-220SCCM, GeH4And H2The mixed gas flow rate of the GeH is 80-120 SCCM, the growth time is 1500-2200 s, and the GeH4And H2In the mixed gas of (1), GeH4At H2The concentration in (a) is 0.7 at.% to 1.3 at.%.
When the epitaxial layer is a Ge epitaxial layer, the epitaxial layer forming conditions are as follows: the temperature is 180 ℃ and 230 ℃, the total pressure is 1.7Torr-2.3Torr, and the power density is 30mW/cm2-40mW/cm2，GeH4And H2The mixed gas flow rate of the GeH is 80-120 SCCM, the growth time is 1500-2200 s, and the GeH4And H2In the mixed gas of (1), GeH4At H2The concentration in (a) is 0.7 at.% to 1.3 at.%.
Preferably, the supporting substrate of step S3 includes a glass substrate, a polymer substrate, the bonding technique includes anodic bonding, polymer adhesive bonding, and the separation of the epitaxial layer from the mother substrate is achieved by annealing or mechanical force.
Preferably, in step S3, when the support substrate is glass, the anodic bonding is performed by bonding the epitaxial layer to the mother substrate at a temperature of 180 ℃ to 220 ℃ and a voltage of 800V to 1200V for 8min to 13min, and then annealing at a temperature of 170 ℃ to 220 ℃ for 4min to 6 min.
According to the invention, the porous interface layer is deposited between the mother substrate and the epitaxial layer in advance, so that the interface between the mother substrate and the epitaxial layer is weakened, and the epitaxial layer can be conveniently transferred to the support substrate.
Compared with the prior art, the invention has the following beneficial effects: .
According to the invention, the silicon-germanium alloy layer is added at the interface of the mother substrate and the epitaxial layer to form the porous interface layer, so that the epitaxial layer can be conveniently transferred without H injection, the damage caused by introducing H ions in the traditional Smart-Cut process is avoided, a dangerous solution such as HF is not required, and the process can be carried out at a low process temperature (about 200 ℃), so that the thermal budget and the processing cost are reduced.
Drawings
Fig. 1 is a schematic view of the present invention utilizing an epitaxial sige alloy layer to transfer an epitaxial layer.
FIG. 2 is a characteristic diagram of samples to be transferred prepared in example 1 of the present invention and comparative example 1, in which (a) is an EDX distribution diagram of germanium atoms; graph (b) is a SIMS graph of hydrogen concentration distribution at two interfaces at the interface; fig. (c) is an elliptical polarization detection diagram.
Detailed Description
The following are specific examples of the present invention and further describe the technical solutions of the present invention, but the present invention is not limited to these examples.
Example 1
The epitaxial layer transfer method in this embodiment has the following steps:
(1) preparing a silicon wafer substrate, cleaning the silicon substrate with hydrofluoric acid solution to remove surface native oxide and surface contaminants, the silicon wafer substrate being shown in FIG. 1(a), and then loading the silicon wafer substrate into a PECVD reactor using H2As a carrier gas to effect deposition of the porous interfacial layer and the epitaxial layer.
(2) Forming a porous interface layer, namely a SiGe alloy layer with a porous structure by adopting the following PECVD process conditions: the temperature is 200 ℃, the total pressure is 2.3Torr, and the power density is 35mW/cm2，SiH4Flow rate of 4SCCM, H2Flow rate of 200SCCM, GeH4And H2The flow rate of the mixed gas is 1SCCM, the growth time is 120s, and the GeH4And H2In the mixed gas of (1), GeH4At H2Concentration in (1 at.%); SiGe alloy layer formed on a silicon wafer substrate As shown in FIG. 1(b), the SiGe alloy layer has a thickness of 20nm and a Ge content of 0.7 at.% of Si.
(3) The silicon epitaxial layer is formed by adopting the following PECVD process conditions: the temperature is 200 ℃, the total pressure is 2.3Torr, and the power density is 35mW/cm2，SiH4Flow rate of 4SCCM, H2The flow rate was 200SCCM, the growth time was 1800 seconds, and the silicon epitaxial layer was formed as shown in FIG. 1 (c).
(4) As shown in FIG. 1(d), an epitaxial layer of silicon was bonded to glass at a temperature of 200 ℃ and a voltage of 1000V for 10min by anodic bonding using glass as a support substrate, the epitaxial layer was bonded to the glass, and then annealed at a temperature of 200 ℃ for 5min to separate the epitaxial layer from the silicon wafer substrate.
Example 2
The epitaxial layer transfer method in this embodiment has the following steps:
(1) preparing a silicon wafer substrate, cleaning the silicon substrate with hydrofluoric acid solution to remove surface native oxide and surface contaminants, the silicon wafer substrate being shown in FIG. 1(a), and then loading the silicon wafer substrate into a PECVD reactor using H2As a carrier gas to effect deposition of the porous interfacial layer and the epitaxial layer.
(2) Forming a porous interface layer, namely a SiGe alloy layer with a porous structure by adopting the following PECVD process conditions: the temperature is 200 ℃, the total pressure is 2.3Torr, and the power density is 35mW/cm2，SiH4Flow rate of 4SCCM, H2Flow rate of 200SCCM, GeH4And H2The flow rate of the mixed gas is 1SCCM, the growth time is 120s, and the GeH4And H2In the mixed gas of (1), GeH4At H2Concentration in (1 at.%); SiGe alloy layer formed on a silicon wafer substrate As shown in FIG. 1(b), the SiGe alloy layer has a thickness of 20nm and a Ge content of 0.7 at.% of Si.
(3) Forming a SiGe epitaxial layer by adopting the following PECVD process conditions: the temperature is 200 ℃, the total pressure is 2.3Torr, and the power density is 35mW/cm2，SiH4Flow rate of 4SCCM, H2Flow rate of 200SCCM, GeH4And H2The flow rate of the mixed gas is 100SCCM, the growth time is 1800s, and the GeH4And H2In the mixed gas of (1), GeH4At H2The concentration in (a) is 1 at.%, and the SiGe epitaxial layer is formed as shown in fig. 1 (c).
(4) As shown in FIG. 1(d), an epitaxial layer of silicon was bonded to glass at a temperature of 200 ℃ and a voltage of 1000V for 10min by anodic bonding using glass as a support substrate, the epitaxial layer was bonded to glass, and then the SiGe epitaxial layer was separated from the silicon wafer substrate by annealing at a temperature of 200 ℃ for 5 min.
Example 3
The epitaxial layer transfer method in this embodiment has the following steps:
(1) preparing a silicon wafer substrate, cleaning the silicon substrate by using hydrofluoric acid solution to remove natural oxide on the surface and surface pollutants, wherein the silicon wafer substrate is shown in figure 1(a), then loading the silicon wafer substrate into a PECVD reactor, and depositing a porous interface layer and an epitaxial layer by a PECVD process.
(2) Forming a porous interface layer, namely a SiGe alloy layer with a porous structure by adopting the following PECVD process conditions: the temperature is 200 ℃, the total pressure is 2.3Torr, and the power density is 35mW/cm2，SiH4Flow rate of 4SCCM, H2Flow rate of 200SCCM, GeH4And H2The flow rate of the mixed gas is 1SCCM, the growth time is 120s, and the GeH4And H2In the mixed gas of (1), GeH4At H2Concentration in (1 at.%); SiGe alloy layer formed on a silicon wafer substrate As shown in FIG. 1(b), the SiGe alloy layer has a thickness of 20nm and a Ge content of 0.7 at.% of Si.
(3) Forming a Ge epitaxial layer by adopting the following PECVD process conditions: the temperature is 200 ℃, the total pressure is 2.3Torr, and the power density is 35mW/cm2，GeH4And H2The flow rate of the mixed gas is 100SCCM, the growth time is 1800s, and the GeH4And H2In the mixed gas of (1), GeH4At H2Is 1 at.%, the Ge epilayer is formed as shown in fig. 1 (c).
(4) As shown in FIG. 1(d), the Ge epitaxial layer was bonded to the glass at a temperature of 200 ℃ and a voltage of 1000V for 10min by anodic bonding using glass as a support substrate, the epitaxial layer was bonded to the glass, and then annealed at a temperature of 200 ℃ for 5min to separate the Ge epitaxial layer from the silicon wafer substrate.
Comparative example 1
The same procedure as in example 1 was repeated except that the SiGe alloy layer was not deposited on the silicon wafer substrate, and the silicon epitaxial layer was directly formed on the silicon wafer substrate
As shown in fig. 2(a), which shows the composition distribution (EDX; Energy-dispersive X-ray) of germanium atoms in each layer of the sample to be transferred prepared in step (3) of example 1 of the present invention, it can be seen from fig. 2(a) that the average germanium component in the SiGe alloy layer is 0.7 at.%.
FIG. 2(b) shows the hydrogen concentration distribution at the interface between the sample to be transferred with the SiGe alloy layer obtained in example 1 and the sample to be transferred without the SiGe alloy layer obtained in comparative example 1Characterized by SIMS (Secondary Ion Mass Spectrometry), it can be seen from FIG. 2(b) that in the case of SiGe alloy layers (solid curves), a relatively high accumulation of hydrogen atoms (8X 10) is observed at the interface21at/cm3) Whereas in the case of no SiGe alloy layer, the hydrogen content at the interface is only 2X 1021at/cm3The hydrogen cumulative concentration of the interface layer in example 1 was 4 times that in the case of the comparative document without the SiGe alloy layer. Thus, although the Ge atomic content in the SiGe alloy layer is very small (only 0.7 at.%), the H incorporation in the interfacial layer can be greatly improved.
FIG. 2(c) shows the results of ellipsometry of two samples to be transferred prepared in example 1 of the present invention and comparative example 1. As can be seen from FIG. 2(c), the sample to be transferred having the SiGe alloy layer (solid curve) in example 1 has a pseudo dielectric function ε at low photon energiesiHas a significantly small amplitude oscillation, which is characteristic of the interfacial porosity between the silicon wafer substrate and the silicon epitaxial layer; whereas the sample to be transferred without the SiGe alloy layer (dashed curve) in comparative example 1 has a pseudo-dielectric function ε at low photon energiesiThe vibration is gentle and does not exist; therefore, the SiGe alloy layer of the sample to be transferred in the embodiment has higher porosity; whereas at low photon energies, the samples of example 1 and comparative example 1 have very similar waveforms, indicating that both have similar crystal quality.
In addition, the sample to be transferred prepared in comparative example 1 could not transfer the epitaxial layer to the glass substrate under the same anodic bonding and annealing conditions as in example 1, and even if the annealing temperature was increased to 500 ℃ and annealed for 5min, the transfer of the silicon epitaxial layer could not be achieved.
In other embodiments of the present invention and alternative embodiments of embodiments 1-3, the mother substrate may also be another wafer; the cleaning process for the mother substrate may also be a fluorine-based plasma process, in which SiF may be used4And the like, fluorine-containing gas; the support substrate may be a polymer substrate in addition to a glass substrate; the epitaxial layer of the sample to be transferred and the supporting substrate can be bonded by using a polymer adhesive besides anodic bonding; the epitaxial layer is connected withMother substrate separation can also be achieved by mechanical force in addition to annealing.
The technical scope of the invention claimed by the embodiments of the present application is not exhaustive, and new technical solutions formed by equivalent replacement of single or multiple technical features in the technical solutions of the embodiments are also within the scope of the invention claimed by the present application; in all the embodiments of the present invention, which are listed or not listed, each parameter in the same embodiment only represents an example (i.e., a feasible embodiment) of the technical solution, and there is no strict matching and limiting relationship between the parameters, wherein the parameters may be replaced with each other without departing from the axiom and the requirements of the present invention, unless otherwise specified.
The technical means disclosed by the scheme of the invention are not limited to the technical means disclosed by the technical means, and the technical scheme also comprises the technical scheme formed by any combination of the technical characteristics. While the foregoing is directed to embodiments of the present invention, it will be appreciated by those skilled in the art that various changes may be made in the embodiments without departing from the principles of the invention, and that such changes and modifications are intended to be included within the scope of the invention.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (8)
1. An epitaxial layer transfer method is characterized by comprising the following steps:
s1, forming a porous interface layer on the surface of the mother substrate;
s2, growing an epitaxial layer on the porous interface layer;
and S3, adhering the epitaxial layer to the supporting substrate through a bonding technology to perform epitaxial layer transfer, and then separating the epitaxial layer from the mother substrate.
2. The method according to claim 1, wherein the porous interface layer is a SiGe alloy layer having a porous structure.
3. The method according to claim 2, wherein the thickness of the SiGe alloy layer is 13nm-28nm, and the content of Ge in the SiGe alloy layer is 0.2 at.% to 2.0 at.% of Si.
4. The method according to claim 2, wherein the SiGe alloy layer and the epitaxial layer are formed by PECVD, and the SiGe alloy layer is formed by adding GeH during the preparation process4And (4) obtaining.
5. The production method according to claim 4, wherein the SiGe alloy layer is formed under conditions of: the temperature is 180-230 ℃, the total pressure is 1.7-2.3 Torr, and the power density is 30mW/cm2-40mW/cm2，SiH4The flow rate is 3.6-4.5 SCCM, H2Flow rate of 180SCCM-220SCCM, GeH4And H2The flow rate of the mixed gas is 0.6-1.3 SCCM, the growth time is 100-150 s, and the GeH4And H2In the mixed gas of (1), GeH4At H2The concentration in (a) is 0.7 at.% to 1.3 at.%.
6. The method of claim 1, wherein the epitaxial layer comprises a Si epitaxial layer, a SiGe epitaxial layer, or a Ge epitaxial layer.
7. The method for preparing a semiconductor device according to claim 1, wherein the supporting substrate of step S3 comprises a glass substrate, a polymer substrate, the bonding technique comprises anodic bonding, polymer adhesive bonding, and the separation of the epitaxial layer from the mother substrate is achieved by annealing or mechanical force.
8. The method of claim 7, wherein in step S3, when the supporting substrate is glass, the anodic bonding is performed by bonding the epitaxial layer to the mother substrate at a temperature of 180 ℃ to 220 ℃ and a voltage of 800V to 1200V for 8min to 13min, and then annealing at a temperature of 170 ℃ to 220 ℃ for 4min to 6 min.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050082526A1 (en) * | 2003-10-15 | 2005-04-21 | International Business Machines Corporation | Techniques for layer transfer processing |
| US20050145837A1 (en) * | 2004-01-07 | 2005-07-07 | International Business Machines Corporation | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain |
| CN1956149A (en) * | 2005-10-26 | 2007-05-02 | 国际商业机器公司 | Methods for forming germanium-on-insulator semiconductor structures and semiconductor structures formed by these methods |
| CN102741980A (en) * | 2010-02-05 | 2012-10-17 | 国际商业机器公司 | Layer transfer using boron-doped sige layer |
| WO2019096947A1 (en) * | 2017-11-15 | 2019-05-23 | Centre National De La Recherche Scientifique | Process for fabricating a transferable thin layer |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050082526A1 (en) * | 2003-10-15 | 2005-04-21 | International Business Machines Corporation | Techniques for layer transfer processing |
| US20050145837A1 (en) * | 2004-01-07 | 2005-07-07 | International Business Machines Corporation | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain |
| CN1956149A (en) * | 2005-10-26 | 2007-05-02 | 国际商业机器公司 | Methods for forming germanium-on-insulator semiconductor structures and semiconductor structures formed by these methods |
| CN102741980A (en) * | 2010-02-05 | 2012-10-17 | 国际商业机器公司 | Layer transfer using boron-doped sige layer |
| WO2019096947A1 (en) * | 2017-11-15 | 2019-05-23 | Centre National De La Recherche Scientifique | Process for fabricating a transferable thin layer |
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