CN110832643A

CN110832643A - Three-dimensional memory device with self-aligned multi-level drain select gate electrode and method of fabricating the same

Info

Publication number: CN110832643A
Application number: CN201880040507.6A
Authority: CN
Inventors: M·堤; S·亚达; 张艳丽
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2017-09-14
Filing date: 2018-05-31
Publication date: 2020-02-21
Anticipated expiration: 2038-05-31
Also published as: WO2019055075A1; EP3619745B1; US10192878B1; CN110832643B; EP3619745A1

Abstract

A sacrificial memory opening fill structure formed by alternating stacking of insulating layers and sacrificial material layers is disclosed. A combination of a photoresist layer including linear openings and a pair of rows of sacrificial memory opening fill structures as an etch mask is employed to form drain select level isolation trenches extending through a layer of drain select level sacrificial material. Sacrificial spacers are formed on sidewalls of the drain select level isolation trenches. A drain select level isolation dielectric structure is formed in a remaining volume of the drain select level isolation trench. Replacing the sacrificial memory opening fill structure with a memory stack structure. Replacing the sacrificial material layer and the sacrificial spacer with a conductive material to form a conductive layer and a conductive connector spacer. The drain select level isolation dielectric structure is self-aligned with the memory stack structure and separates drain select level conductive layers.

Description

Three-dimensional memory device with self-aligned multi-level drain select gate electrode and method of fabricating the same

RELATED APPLICATIONS

This application claims priority to U.S. non-provisional application serial No. 15/704,286, filed on 2017, 9, 14, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates generally to the field of semiconductor devices and, in particular, to three-dimensional memory devices employing self-aligned multi-level drain select level gate electrodes and methods of fabricating the same.

Background

Three-dimensional vertical NAND strings With one bit per Cell are disclosed in an article entitled "Novel ultra high Density Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM proc. (2001)33-36 by t.endoh et al.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a three-dimensional memory device including: an alternating stack of insulating layers and conductive layers positioned over a substrate; and memory stack structures extending through the alternating stack, wherein each memory stack structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The two or more uppermost layers of the conductive layers include first and second stripe portions laterally spaced apart from each other by a drain select level isolation dielectric structure comprising an alternating sequence of a pair of non-concave sidewall portions and concave sidewall portions.

According to another aspect of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers and conductive layers over a substrate; memory stack structures extending through the alternating stack, wherein each memory stack structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film; a first conductive connector spacer connected to each first stripe portion of the two or more uppermost layers in the conductive layer; and a second conductive connector spacer connected to each second strip portion of the two or more uppermost layers in the conductive layer. Each of the first and second conductive connector spacers includes an alternating sequence of conductive non-concave sidewall portions and conductive concave sidewall portions.

According to another aspect of the present disclosure, there is provided a method of forming a three-dimensional memory device, the method including: forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming a drain select level isolation trench through two or more uppermost layers of the sacrificial material layer; forming a sacrificial spacer on sidewalls of the drain select level isolation trench; forming memory stack structures extending through the alternating stack, wherein each memory stack structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film; and partially replacing the sacrificial material layer and the sacrificial material with a conductive material. In one embodiment, the conductive layer is formed within a volume of the layer of sacrificial material and the conductive connector spacer is formed within a volume of the sacrificial spacer. Each conductive connector spacer provides an electrical connection between two or more uppermost layers of the conductive layer.

Drawings

Fig. 1 is a vertical cross-sectional view of an exemplary structure after forming at least one peripheral device and a layer of semiconductor material, according to an embodiment of the present disclosure.

Fig. 2 is a vertical cross-sectional view of an exemplary structure after forming an alternating stack of insulating layers and sacrificial material layers, according to an embodiment of the present disclosure.

Fig. 3 is a vertical cross-sectional view of an example structure after forming stepped platforms and backward stepped dielectric material portions according to an embodiment of the disclosure.

Fig. 4A is a vertical cross-sectional view of an example structure after forming a memory opening and a support opening, according to an embodiment of the present disclosure.

Fig. 4B is a top view of the exemplary structure of fig. 4A. The vertical plane a-a' is the plane of the cross-section of fig. 4A.

Fig. 5 is a vertical cross-sectional view of an exemplary structure after forming a pedestal channel portion, according to an embodiment of the present disclosure.

Fig. 6 is a vertical cross-sectional view of an exemplary structure after forming a sacrificial semiconductor oxide plate, a sacrificial memory opening fill structure, and a sacrificial support opening fill structure, according to an embodiment of the present disclosure.

Fig. 7A is a vertical cross-sectional view of an exemplary structure after application and patterning of a photoresist layer, according to an embodiment of the present disclosure.

Fig. 7B is a top view of the exemplary structure of fig. 7A. The vertical plane a-a' is the plane of the cross-section of fig. 7A.

Figure 8A is a vertical cross-sectional view of an exemplary structure after forming a drain select layer isolation trench, according to an embodiment of the present disclosure.

Fig. 8B is a top view of the exemplary structure of fig. 8A. The vertical plane a-a' is the plane of the section of fig. 8A.

Figure 9 is a vertical cross-sectional view of an exemplary structure after forming a layer of sacrificial spacer material, according to an embodiment of the present disclosure.

Figure 10A is a vertical cross-sectional view of an exemplary structure after forming sacrificial spacers, according to an embodiment of the present disclosure.

Fig. 10B is a top view of the exemplary structure of fig. 10A. The vertical plane a-a' is the plane of the cross-section of fig. 10A.

Figure 11 is a top view of an exemplary structure after the sacrificial spacers are separated by removing longitudinal end portions of the sacrificial spacers, according to an embodiment of the present disclosure.

Fig. 12A is a vertical cross-sectional view of an exemplary structure after formation of a drain select layer isolation dielectric structure, according to an embodiment of the present disclosure.

Fig. 12B is a top view of the exemplary structure of fig. 12A. The vertical plane a-a' is the plane of the cross-section of fig. 12A.

Fig. 13A-13H are sequential vertical cross-sectional views of a memory opening during formation of a memory stack structure according to an embodiment of the disclosure.

Figure 14 is a vertical cross-sectional view of an example structure after forming a memory stack structure, according to an embodiment of the present disclosure.

Fig. 15A is a vertical cross-sectional view of an example structure after forming backside trenches, according to an embodiment of the present disclosure.

Fig. 15B is a top view of the exemplary structure of fig. 15A. Vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 15A.

Fig. 16 is a vertical cross-sectional view of an exemplary structure after forming a backside recess by removing a layer of sacrificial material relative to an insulating layer, according to an embodiment of the disclosure.

Fig. 17A-17D are sequential vertical cross-sectional views of an exemplary structure between forming a backside recess and forming a conductive layer in a region between a backside trench and a memory opening, according to an embodiment of the present disclosure.

Fig. 18A is a vertical cross-sectional view of the exemplary structure at the processing step of fig. 17D.

Fig. 18B is a horizontal cross-sectional view of an area of the exemplary structure taken along horizontal plane B-B' in fig. 18A.

Fig. 18C is a horizontal cross-sectional view of an area of the exemplary structure taken along horizontal plane C-C in fig. 18A.

Fig. 19 is a vertical cross-sectional view of an example structure after removing deposited conductive material from within backside trenches, according to an embodiment of the present disclosure.

Fig. 20A is a vertical cross-sectional view of an exemplary structure after forming an insulating spacer and a backside contact structure within each backside trench, according to an embodiment of the present disclosure.

Fig. 20B is a vertical cross-sectional view of the exemplary structure of fig. 20A in a region between a backside trench and a memory opening.

Fig. 21A is a vertical cross-sectional view of an exemplary structure after forming an additional contact via structure, according to an embodiment of the present disclosure.

Fig. 21B is a top view of the exemplary structure of fig. 21A. Vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 21A.

Detailed Description

As discussed above, the present disclosure relates to three-dimensional memory devices employing self-aligned multi-level drain select level gate electrodes and methods of fabricating the same, various aspects of which are described below. Embodiments of the present disclosure may be used to form various structures, including multi-level memory structures, non-limiting examples of which include semiconductor devices, such as three-dimensional monolithic memory array devices that include multiple NAND memory strings.

The figures are not drawn to scale. Where a single instance of an element is illustrated, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated to be absent repetition of the element. Ordinal numbers such as "first," "second," and "third" are used merely to identify similar elements, and different ordinal numbers may be employed throughout the specification and claims of the present disclosure. The same reference numerals indicate the same elements or similar elements. Elements having the same reference number are assumed to have the same composition unless otherwise specified. As used herein, a first element that is positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element.

As used herein, "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range that is less than the range of an underlying or overlying structure. In addition, a layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above and/or below.

A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, without an intervening substrate. The term "monomer" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. Instead, a two-dimensional array may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories are constructed by forming Memory levels on separate substrates and vertically stacking the Memory levels, as described in U.S. patent No. 5,915,167, entitled Three-dimensional Structure Memory. The substrate may be thinned or removed from the memory level prior to bonding, but such memories are not true monolithic three dimensional memory arrays because the memory level is initially formed over a separate substrate. Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices, and may be fabricated employing the various embodiments described herein.

Referring to fig. 1, an exemplary structure according to an embodiment of the present disclosure is shown that may be used, for example, to fabricate a device structure containing a vertical NAND memory device. An exemplary structure includes a substrate, which may be a semiconductor substrate (9, 10). The substrate may comprise a substrate semiconductor layer 9. The substrate semiconductor layer 9 may be a semiconductor wafer or a layer of semiconductor material, and may include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate may have a main surface 7, which may be, for example, the topmost surface of the substrate semiconductor layer 9. The main surface 7 may be a semiconductor surface. In one embodiment, major surface 7 can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

As used herein, "semiconductor material" is meant to have a chemical composition of 1.0X 10^-6S/cm to 1.0X 10⁵A material having an electrical conductivity in the range of S/cm. As used herein, "semiconductor material" refers to a material having a molecular weight of 1.0 x 10 in the absence of an electrical dopant therein^-6S/cm to 1.0X 10⁵A material having an electrical conductivity in the range of S/cm and capable of being produced with appropriate doping of an electrical dopant having a conductivity in the range of 1.0S/cm to 1.0X 10⁵A doping material of conductivity in the range of S/cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to a valence band within the band structure, or an n-type dopant that adds electrons to a conduction band within the band structure. As used herein, "conductive material" means having a thickness of greater than 1.0 x 10⁵S/cm of conductivity. As used herein, "insulator material" or "dielectric material" is meant to have a thickness of less than 1.0 x 10^-6S/cm of conductivity. As used herein, "heavily doped semiconductor material" refers to a material that is doped with an electrical dopant at a sufficiently high atomic concentration to become electrically conductive (i.e., has an atomic concentration greater than 1.0 x 10)⁵Electrical conductivity of S/cm). The "doped semiconductor material" may be a heavily doped semiconductor material, or may be a material including a metal provided at 1.0 × 10^-6S/cm to 1.0X 10⁵A semiconductor material of electrical dopant (i.e., p-type dopant and/or n-type dopant) at a concentration of conductivity in the range of S/cm. "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material may be semiconducting or conducting, and may be intrinsic or doped semiconductor material. The doped semiconductor material may be semiconducting or conducting, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metallic element therein. All conductivity measurements were performed under standard conditions.

At least one semiconductor device 700 of the peripheral circuit may be formed on a portion of the substrate semiconductor layer 9. The at least one semiconductor device may comprise a field effect transistor, for example. For example, the at least one shallow trench isolation structure 120 may be formed by etching a portion of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate capping dielectric layer may be formed over the substrate semiconductor layer 9 and may be subsequently patterned to form at least one gate structure (150,152,154,158), each of which may include a gate dielectric 150, a gate electrode (152,154), and a gate capping dielectric 158. The gate electrode (152,154) may comprise a stack of a first gate electrode portion 152 and a second gate electrode portion 154. At least one gate spacer 156 may be formed around the at least one gate structure (150,152,154,158) by depositing and anisotropically etching a dielectric liner. The active region 130 may be formed in an upper portion of the substrate semiconductor layer 9, for example by introducing electrical dopants employing the at least one gate structure (150,152,154,158) as a masking structure. Additional masks may be employed as desired. The active region 130 may include a source region and a drain region of a field effect transistor. First dielectric liner 161 and second dielectric liner 162 may optionally be formed. Each of the first dielectric liner 161 and the second dielectric liner 162 may include a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms per silicon atom. Silica is preferred. In an exemplary example, the first dielectric liner 161 may be a silicon oxide layer, and the second dielectric liner 162 may be a silicon nitride layer. The at least one semiconductor device of the peripheral circuitry may contain a driver circuit of a subsequently formed memory device, which may include at least one NAND device.

A dielectric material, such as silicon oxide, may be deposited over the at least one semiconductor device and may subsequently be planarized to form a planarized dielectric layer 170. In one embodiment, the planarized top surface of the planarized dielectric layer 170 may be coplanar with the top surfaces of the dielectric pads (161, 162). Subsequently, the planarization dielectric layer 170 and the dielectric pads (161,162) may be removed from a certain area to physically expose the top surface of the substrate semiconductor layer 9. As used herein, a surface is "physically exposed" if the surface is in physical contact with a vacuum or a gas phase material (such as air).

An optional layer of semiconductor material 10 may be formed on the top surface of the substrate semiconductor layer 9 by depositing a single crystal semiconductor material (e.g., by selective epitaxy). The deposited semiconductor material may be the same as or different from the semiconductor material of the substrate semiconductor layer 9. The deposited semiconductor material may be any material that may be used for the semiconductor substrate layer 9, as described above. The monocrystalline semiconductor material of the semiconductor material layer 10 may be epitaxially aligned with the monocrystalline structure of the substrate semiconductor layer 9. The portion of the deposited semiconductor material positioned above the top surface of the planarization dielectric layer 170 may be removed, for example, by Chemical Mechanical Planarization (CMP). In this case, the semiconductor material layer 10 may have a top surface coplanar with a top surface of the planarization dielectric layer 170. The layer of semiconductor material 10 may be doped with an electrical dopant of the first conductivity type, which may be p-type or n-type.

A region (i.e., region) of the at least one semiconductor device 700 is referred to herein as a peripheral device region 200. The device region in which the memory array is subsequently formed is referred to herein as the memory array region 100. A contact region 300 for a stepped mesa for subsequent formation of a conductive layer may be provided between the memory array region 100 and the peripheral device region 200.

Referring to fig. 2, a stack of alternating layers of a first material (which may be an insulating layer 32) and a second material (which may be a sacrificial material layer 42) is formed over the top surface of the substrate (9, 10). As used herein, a "layer of material" refers to a layer that includes the material throughout and throughout. As used herein, the alternating pluralities of first and second elements refers to structures in which instances of the first elements alternate with instances of the second elements. Each instance of a first element that is not an end element of the alternating plurality of elements abuts two instances of a second element on both sides, and each instance of a second element that is not an end element of the alternating plurality of elements abuts two instances of the first element on both ends. The first elements may have the same thickness therebetween, or may have different thicknesses. The second elements may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of a first material layer or an instance of a second material layer and may end with an instance of a first material layer or an instance of a second material layer. In one embodiment, the instances of the first element and the instances of the second element may form a unit that repeats periodically within alternating multiple elements.

Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32 and each second material layer may be a sacrificial material layer. In this case, the stack may include a plurality of alternating layers of insulating layers 32 and sacrificial material layers 42, and constitute a prototype stack including alternating layers of insulating layers 32 and sacrificial material layers 42. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

The stack of alternating pluralities is referred to herein as an alternating stack (32, 42). In one embodiment, the alternating stack (32,42) may include an insulating layer 32 composed of a first material and a sacrificial material layer 42 composed of a second material, wherein the second material is different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. Thus, each insulating layer 32 may be a layer of insulating material. Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

The second material of the sacrificial material layer 42 is a sacrificial material that is selectively removable with respect to the first material of the insulating layer 32. As used herein, the removal of a first material is "selective" for a "second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process for the first material relative to the second material.

The sacrificial material layer 42 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may then be replaced with a conductive electrode that may serve, for example, as a control gate electrode for a vertical NAND device. Non-limiting examples of the second material include silicon nitride.

In one embodiment, the insulating layer 32 may comprise silicon oxide and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The first material of the insulating layer 32 may be deposited, for example, by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, Tetraethylorthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the sacrificial material layer 42 may be formed, such as CVD or Atomic Layer Deposition (ALD).

The sacrificial material layer 42 may be appropriately patterned such that portions of conductive material subsequently formed by replacing the sacrificial material layer 42 may serve as conductive electrodes, such as control gate electrodes of subsequently formed monolithic three-dimensional NAND string memory devices. The layer of sacrificial material 42 may comprise portions having a strip shape extending substantially parallel to the main surface 7 of the substrate.

The thickness of the insulating layer 32 and the sacrificial material layer 42 may be in the range of 20nm to 50nm, although lesser and greater thicknesses may be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the pair of insulating layers 32 and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42 may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although greater numbers of repetitions may also be employed. The top gate electrode and the bottom gate electrode in the stack may be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32,42) may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42.

Although the present disclosure is described with an embodiment in which the layer of spacer material is a layer of sacrificial material 42 that is subsequently replaced by a conductive layer, embodiments are expressly contemplated herein in which the layer of sacrificial material is formed as a conductive layer. In this case, the step of replacing the spacer material layer with the conductive layer may be omitted.

Optionally, an insulating cap layer 70 may be formed over the alternating stack (32, 42). The insulating cap layer 70 comprises a dielectric material different from the material of the sacrificial material layer 42. In one embodiment, the insulating cap layer 70 may comprise a dielectric material as described above as may be used for the insulating layer 32. The insulating capping layer 70 may have a greater thickness than each of the insulating layers 32. The insulating cap layer 70 may be deposited by, for example, chemical vapor deposition. In one embodiment, the insulating cap layer 70 may be a silicon oxide layer.

Referring to fig. 3, the stepped cavity may be formed within a contact region 300 positioned between the memory array region 100 and a peripheral device region 200 containing at least one semiconductor device for peripheral circuitry. The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity varies stepwise according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etch process that vertically increases the cavity depth by one or more levels and a second type of etch process that laterally extends the region to be vertically etched in a subsequent etch process of the first type. As used herein, a "level" of a structure comprising alternating pluralities is defined as the relative position of a pair of first and second material layers within the structure.

After forming the stepped cavities, peripheral portions of the alternating stacks (32,42) may have stepped surfaces after forming the stepped cavities. As used herein, "stepped surface" refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface abuts a first vertical surface extending upward from a first edge of the horizontal surface and abuts a second vertical surface extending downward from a second edge of the horizontal surface. "stepped cavity" refers to a cavity having a stepped surface.

The mesa region is formed by patterning the alternating stack (32, 42). Each sacrificial material layer 42 within the alternating stack (32,42) except for the topmost sacrificial material layer 42 extends laterally further than any overlying sacrificial material layer 42 within the alternating stack (32, 42). The land region includes a stepped surface of the alternating stack (32,42) that continuously extends from a lowermost layer within the alternating stack (32,42) to a uppermost layer within the alternating stack (32, 42).

The backward stepped dielectric material portion 65 (i.e., the insulating fill material portion) may be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from over the top surface of the insulating cap layer 70, for example, by Chemical Mechanical Planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes a backward stepped dielectric material portion 65. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is used for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may or may not be doped with dopants, such as B, P and/or F.

Referring to fig. 4A and 4B, a photolithographic material stack (not shown) including at least a photoresist layer may be formed over the insulating cap layer 70 and the retro-stepped dielectric material portion 65, and may be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the contact region 300. The pattern in the stack of photolithographic material can be transferred through the insulating cap layer 70 or the retro-stepped dielectric material portion 65 and through the alternating stack (32,42) by at least one anisotropic etch using the patterned stack of photolithographic material as an etch mask. Portions of the alternating stack (32,42) below the openings in the patterned stack of photolithographic material are etched to form memory openings 49 and support openings 19. As used herein, "memory opening" refers to a structure in which a memory element, such as a memory stack structure, is subsequently formed therein. As used herein, "support opening" refers to a structure in which a support structure (such as a support post structure) is subsequently formed that mechanically supports other elements. The memory openings 49 are formed through the integral formation of the alternating stacks (32,42) in the insulating cap layer 70 and the memory array region 100. Support openings 19 are formed through the backward stepped dielectric material portion 65 and portions of the alternating stacks (32,42) that are located below the stepped surface in the contact region 300.

A reservoir opening 49 extends through the entirety of the alternating stack (32, 42). The support openings 19 extend through a subset of the layers within the alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch through the material of the alternating stack (32,42) may be alternated to optimize the etching of the first and second materials in the alternating stack (32, 42). The anisotropic etch may be, for example, a series of reactive ion etches. The sidewalls of the reservoir opening 49 and the support opening 19 may be substantially vertical or may be tapered. The patterned stack of photolithographic material can then be removed, for example, by ashing.

The memory openings 49 and the support openings 19 may extend from a top surface of the alternating stack (32,42) at least to a horizontal plane including a topmost surface of the substrates (9, 10). In one embodiment, the overetch of the semiconductor material layer 10 may optionally be performed after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19. The overetch may be performed before or after the stack of photolithographic materials is removed. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the unprocessed top surface of the semiconductor material layer 10 by a recess depth. The recess depth may be in the range of, for example, 1nm to 50nm, although lesser and greater depths may also be employed. The over-etching is optional and may be omitted. The bottom surfaces of the memory openings 49 and the support openings 19 may be coplanar with the topmost surface of the layer of semiconductor material 10 if no over-etching is performed.

Each of the memory opening 49 and the support opening 19 may include a sidewall (or sidewalls) that extends substantially perpendicular to a topmost surface of the substrate. A two-dimensional array of memory openings 49 may be formed in the memory array region 100. A two-dimensional array of support openings 19 may be formed in the contact area 300. The substrate semiconductor layer 9 and the semiconductor material layer 10 together constitute a substrate (9,10), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the memory opening 49 and the support opening 19 may extend to the top surface of the substrate semiconductor layer 9.

In one embodiment, the memory openings 49 may be formed as two-dimensional periodic arrays, such that each two-dimensional periodic array includes rows extending along a first horizontal direction hd1, and has a uniform inter-row spacing p along a second horizontal direction hd2 that may be perpendicular to the first horizontal direction hd 1. In one embodiment, a plurality of two-dimensional periodic arrays may be formed such that each two-dimensional periodic array is formed as a cluster laterally spaced from an adjacent two-dimensional periodic array along the second horizontal direction. Each two-dimensional periodic array may include a respective row extending along the first horizontal direction hd1 and having a uniform inter-row spacing p along the second horizontal direction hd 2.

Referring to fig. 5, an optional pedestal channel portion 11 may be formed at a bottom portion of each memory opening 49 and each support opening 19, for example, by a selective semiconductor material deposition process. The selective semiconductor material deposition process grows semiconductor material from physically exposed semiconductor surfaces and does not grow semiconductor material from dielectric surfaces. The pedestal channel portion 11 may be monocrystalline or polycrystalline. In the case where the layer of semiconductor material 10 comprises a single crystal semiconductor material, each pedestal channel portion 11 may comprise a single crystal semiconductor material that is epitaxially aligned with the single crystal semiconductor material of the layer of semiconductor material 10.

In one embodiment, the top surface of each pedestal channel portion 11 may be formed above a horizontal plane that includes the top surface of the bottommost sacrificial material layer 42. In this case, at least one source select gate electrode may be subsequently formed by replacing the bottommost sacrificial material layer 42 located below the horizontal plane including the top surface of the pedestal channel portion 11 with a corresponding conductive material layer. Each pedestal channel portion 11 may be a portion of a transistor channel that extends between a source region that will be subsequently formed in the substrate (9,10) and a drain region that will be subsequently formed in an upper portion of the memory opening 49. A cavity is present in the unfilled portion of the memory opening 49 above each pedestal channel portion 11. In one embodiment, each pedestal channel portion 11 may comprise monocrystalline silicon. In one embodiment, each pedestal channel portion 11 may have a doping of a first conductivity type that is the same as the conductivity type of the semiconductor material layer 10 that the pedestal channel portion contacts. If the layer of semiconductor material 10 is not present, each pedestal channel portion 11 may be formed directly on the substrate semiconductor layer 9, which may have a doping of the first conductivity type.

Referring to fig. 6, the sacrificial semiconductor oxide plate 113 may be formed by oxidizing a surface portion of the pedestal channel portion 11. The sacrificial memory opening fill structures 31 and the sacrificial support opening fill structures 131 may be formed by depositing a sacrificial material in the remaining volumes of the memory openings 49 and the support openings 19, respectively. Excess portions of the sacrificial material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70. The sacrificial memory opening fill structures 31 and the sacrificial support opening fill structures 131 comprise sacrificial material that can be removed in a manner that is selective to the material of the insulating layer 32, the sacrificial material layer 42, the insulating cap layer 70, and the retro-stepped dielectric material portion 65. In a non-limiting illustrative example, the insulating layer 32, the insulating cap layer 70, and the backward stepped dielectric material portion 65 may comprise silicon oxide, the sacrificial material layer 42 may comprise silicon nitride, and the sacrificial memory opening fill structures 31 and the sacrificial support opening fill structures 131 may comprise amorphous silicon, polysilicon, a silicon germanium alloy, amorphous carbon, diamond-like carbon (DLC), or a silicon-containing polymer.

Referring to fig. 7A and 7B, a photoresist layer 147 may be applied over the insulating cap layer 70 and the backward stepped dielectric material portion 65, and may be lithographically patterned to form openings, such as linear openings 148 therethrough. As used herein, "linear opening" refers to an opening having a linear shape defined by a pair of longitudinal edges that are parallel to each other. Thus, each linear opening 148 may have a constant uniform width along the longitudinal direction of the linear opening. In one embodiment, the linear opening 148 through the photoresist layer 147 may comprise a rectangular opening. The photoresist layer 147 overlies a respective row of sacrificial memory opening fill structures 31 around the longitudinal sidewalls of each linear opening, the row of sacrificial memory opening fill structures being a row of memory opening fill structures in two adjacent rows of memory opening fill structures 31 that are partially exposed beneath the linear opening in the photoresist layer 147. In one embodiment, the linear opening 148 does not extend into the contact region 300 or the peripheral device region 200.

The shape of the linear openings through photoresist layer 147 may be selected such that subsequently formed linear openings or backside trenches are disposed between adjacent memory opening sub-blocks. As used herein, a "subblock" refers to the smallest group of cells of a memory stack structure activated by a common drain select gate electrode, or the smallest group of cells of a memory opening in which the corresponding smallest group of cells of the memory stack structure activated by a common drain select gate electrode is subsequently formed. As used herein, a "block" refers to a set of memory stack structures that are located between a pair of adjacent backside trenches (to be subsequently formed), or a set of memory openings in which a set of memory stack structures that are located between a pair of adjacent backside trenches are to be subsequently formed. All memory stacks located in the same block may be surrounded by the same word line in a given device level (e.g., the same set of vertically spaced word lines may surround each memory stack in a given block).

In one implementation, the shape of the linear openings 148 through the photoresist layer 147 may be selected such that each longitudinal edge of the linear openings extends over a respective row of sacrificial memory opening fill structures 31 in a pair of adjacent rows of sacrificial memory opening fill structures. For example, a pair of adjacent rows of sacrificial memory opening fill structures 31 may include a first row of sacrificial memory opening fill structures 31 arranged along a first horizontal direction hd1 and a second row of sacrificial memory opening fill structures 31 arranged along the first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd 2. In one implementation, the location of the sacrificial memory opening fill structures 31 may be laterally offset in the first horizontal direction hd1 by half the spacing of the sacrificial memory opening fill structures 31 between the first and second rows in the first horizontal direction hd 1. Thus, a first vertical sidewall of the photoresist layer 147 may contact and extend laterally over the first row of sacrificial memory opening fill structures 31, and a second vertical sidewall of the photoresist layer 147 may contact and extend laterally over the second row of sacrificial memory opening fill structures 31. The percentage of the physically exposed top surface portion of each sacrificial memory opening fill structure 31 relative to the total area of the top surface of the respective sacrificial memory opening fill structure 31 may be in the range of 20% to 80%, such as 40% to 60%.

Referring to fig. 8A and 8B, an anisotropic etch process may be performed to form drain select level isolation trenches 119, which etches the material of the insulating cap layer 70, insulating layer 32, and sacrificial material layer 42, and is selective to the material of the sacrificial memory opening fill structures 31. The photoresist layer 147 and the sacrificial memory opening fill structure 31 collectively serve as an etch mask to form the drain select level isolation trenches 119. Intersection of the region of the drain select level isolation trench 119 with the region of the linear opening 148 in the photoresist layer 147 corresponds to the complement of the region of the sacrificial memory opening fill structure 31. A drain select level isolation trench 119 is formed through each level at which a drain select gate electrode will be subsequently formed. As used herein, a drain select gate electrode refers to an electrode that activates a subset of the memory stack structures by applying a bias voltage to a region of the semiconductor channel near the drain of the vertical field effect transistor. Drain select level isolation trenches 119 are formed through the insulating cap layer 70, through the two or more uppermost layers in the sacrificial material layer 42, and through any one or more intervening insulating layers 32, but preferably without significantly etching the sacrificial memory opening fill structures 31.

In one implementation, each drain select level isolation trench 119 may extend vertically through both topmost sacrificial material layers 42 and the insulating layer 32 therebetween. In another embodiment, each drain select level isolation trench 119 may extend vertically through the three topmost sacrificial material layers 42 and the two insulating layers 32 therebetween. In another embodiment, each drain select level isolation trench 119 may extend vertically through the four topmost sacrificial material layers 42 and the three insulating layers therebetween. The level of sacrificial material layer 42 through which drain select level isolation trenches 119 extend vertically is referred to herein as the drain select level.

Each drain select level isolation trench 119 is formed to have a pair of longitudinal sidewalls extending generally along the first horizontal direction hd1, as shown in fig. 8B. Each of the pair of longitudinal sidewalls of drain select level isolation trench 119 may include an alternating sequence of a pair of non-convex sidewall portions 29P and convex sidewall portions 29C. Each non-convex sidewall portion 29P may be a flat portion if adjacent memory openings 49 that receive the sacrificial memory opening fill structures 31 are spaced apart a distance long enough to provide a flat portion, or each portion 29P may be a concave portion if adjacent memory openings are spaced too close to one another to leave space for a flat portion. Each convex sidewall portion may comprise a sidewall of a respective one of the sacrificial memory opening fill structures 31. In particular, each convex sidewall portion 29C can be a physically exposed sidewall of a sacrificial memory opening fill structure 31, and each non-convex (e.g., flat or concave) sidewall 29P can include a vertically coincident sidewall of an insulating layer 32 and a sacrificial material layer 42 at a level of a drain select gate electrode to be subsequently formed. The photoresist layer 147 can then be removed, for example, by ashing.

Referring to fig. 9, a layer of sacrificial spacer material 122L may be deposited on the physically exposed surfaces of the drain select level isolation trenches 119 and the top surfaces of the insulating cap layer 70 and the retro-stepped dielectric material portions 65. The sacrificial spacer material layer 122L comprises a material different from the material of the insulating layer 32, the insulating cap layer 70, the retro-stepped dielectric material portion 65, and the sacrificial memory opening fill structure 31. The material of the sacrificial spacer material layer 122L may be the same as or different from the material of the sacrificial material layer 42. In one embodiment, the sacrificial spacer material layer 122L and the sacrificial material layer 42 may comprise a silicon nitride material. The sacrificial spacer material layer 122L may be deposited by a conformal deposition method, such as low pressure chemical vapor deposition or atomic layer deposition. The thickness of the sacrificial spacer material layer 122L may be less than half of the narrowest portion between a pair of longitudinal sidewalls of each drain select level isolation trench 119. Thus, a continuous cavity extends laterally within each drain select level isolation trench 119 generally along the first horizontal direction hd 1.

Referring to fig. 10A and 10B, an anisotropic etching process is performed to remove horizontal portions of the sacrificial spacer material layer 122L. The remaining vertical portion of the layer of sacrificial spacer material 122L in the drain select level isolation trench 119 constitutes a sacrificial spacer 122.

Referring to fig. 11, a photoresist layer (not shown) may be applied over the exemplary structure. Openings may be formed through the photoresist layer by photolithographic exposure and development. An opening in the photoresist layer may be formed in a region located at a longitudinal end of the drain select level isolation trench 119. An etch process that removes material of sacrificial spacer 122 may be performed to remove the physically exposed portions of sacrificial spacer 122. Each sacrificial spacer 122 may be separated into two physically separated sacrificial spacers 122.

Each sacrificial spacer 122 may be formed on a convex sidewall of the sacrificial memory opening fill structure 31 and the two or more uppermost non-convex (e.g., flat or concave) sidewalls through which the drain select level isolation trenches 119 in the sacrificial material layer 42 vertically extend (i.e., flat or concave sidewalls of the sacrificial material layer 42 at the drain select level). Each sacrificial material layer 42 through which a drain select level isolation trench 119 vertically extends includes a stripe portion extending laterally in the first horizontal direction hd1 between a pair of adjacent drain select level isolation trenches 119. Within each drain select level isolation trench 119, a first sacrificial spacer 122A may contact a sidewall of a first strip portion of each of two or more uppermost layers at the drain select level in the sacrificial material layer 42, and a second sacrificial spacer 122B may contact a sidewall of a second strip portion of each of the two or more uppermost layers at the drain select level in the sacrificial material layer 42. Each of the first and second sacrificial spacers (122A,122B) includes an outer sidewall that includes an alternating sequence of non-concave (e.g., flat or convex) sidewall portions and concave sidewall portions. The non-concave sidewall portions contact sidewalls of a subset of the layers within the alternating stack (32, 42). The sacrificial spacer (122A,122B) also has an inner sidewall that includes an alternating sequence of non-convex (e.g., flat or concave) sidewall portions and physically exposed convex sidewall portions. Each inner concave sidewall portion of the sacrificial spacer 122 may contact a respective one of the sacrificial memory opening filling structures 31, and each outer convex sidewall portion of the sacrificial spacer 122 may be equidistant from a respective one of the sacrificial memory opening filling structures 31. After forming sacrificial spacers 122 in each drain select level isolation trench 119, a cavity exists within the unfilled volume of each drain select level isolation trench 119.

Referring to fig. 12A and 12B, a dielectric material is deposited within the cavity in the drain select level isolation trench 119. The dielectric material comprises a material that is different from the material of sacrificial spacers 122 and sacrificial memory opening fill structures 31. For example, the dielectric material may include silicon oxide. Excess portions of the dielectric material may be removed from above a horizontal plane including the top surfaces of the insulating cap layer 70 and the retro-stepped dielectric material portions 65 by a planarization process, which may include Chemical Mechanical Planarization (CMP) and/or a recess etch. Each remaining portion of the dielectric material in the drain select level isolation trenches 119 constitutes a dielectric structure, referred to herein as a drain select level isolation dielectric structure 124. The drain select level isolation dielectric structure 124 extends laterally along the first horizontal direction hd 1.

Each sacrificial material layer 42 at the drain select level includes a strip portion extending laterally along the first horizontal direction hd1 and laterally spaced apart from each other by the drain select level isolation dielectric structure 124. Each drain select level isolation dielectric structure 124 includes an alternating sequence of a pair of non-concave (e.g., flat or convex) sidewall portions and concave sidewall portions. The non-concave sidewall portions may be flat if the reservoir openings 49 are spaced apart a sufficient distance, or convex if the reservoir openings 49 are spaced apart a distance insufficient to form a flat portion. Each of the concave sidewall portions is equidistant from an outer sidewall of a respective one of the sacrificial memory opening fill structures 31. The distance between each concave sidewall portion and a respective one of the sacrificial memory opening fill structures 31 can be a lateral thickness of the sacrificial spacer 122. In one embodiment, each pair of alternating sequences of non-concave sidewall portions and concave sidewall portions may comprise a first alternating sequence of first flat sidewall portions and first concave sidewall portions contacting a first sacrificial spacer within a pair of sacrificial spacers 122 in the drain select level isolation trench 119, and a second alternating sequence of second flat sidewall portions and second concave sidewall portions contacting a second sacrificial spacer within the pair of sacrificial spacers 122. In one embodiment, the first planar sidewall portion can lie in a first vertical plane and the second planar sidewall portion can lie in a second vertical plane parallel to the first vertical plane.

Fig. 13A-13H illustrate structural changes to the memory opening 49 during replacement of the memory opening fill structure 31 with a memory stack structure, which is one of the memory openings 49 in the exemplary structures of fig. 12A and 12B. The same structural changes occur in each of the other reservoir openings 49 and the support openings 19 simultaneously.

Referring to fig. 13A, a memory opening 49 in the exemplary device structure of fig. 12A and 12B is shown. The memory opening 49 extends through the insulating cap layer 70, the alternating stack (32,42), and optionally into an upper portion of the semiconductor material layer 10. Each memory opening 49 may be filled with a pedestal channel portion 11, a sacrificial semiconductor oxide plate 113, and a sacrificial memory opening fill structure 31. In this processing step, each support opening 19 may extend through a backward-stepped dielectric material portion 65, a subset of the layers in the alternating stack (32,42), and optionally through an upper portion of the semiconductor material layer 10. The recess depth of the bottom surface of each memory opening relative to the top surface of the layer of semiconductor material 10 may be in the range of 0nm to 30nm, although greater recess depths may also be employed.

Referring to fig. 13B, the memory opening fill structures 31 may be removed in a manner selective to the insulating cap layer 70, the alternating stack (32,42), the drain select level isolation dielectric structure 124, and the sacrificial semiconductive oxide panel 113. For example, if the memory opening fill structure 31 comprises amorphous silicon, the memory opening fill structure 31 may be removed using a wet etch using KOH solution or trimethyl-2 hydroxyethylammonium hydroxide (TMY) solution that is selective to the insulating cap layer 70, the alternating stack (32,42), the drain select level isolation dielectric structure 124, and the sacrificial semiconductor oxide plate 113. Subsequently, the sacrificial semiconductor oxide plate 113 may be removed by isotropic etching (such as wet etching with dilute hydrofluoric acid) or anisotropic etching.

Referring to fig. 13C, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional first semiconductor channel layer 601 may be sequentially deposited in the memory opening 49.

The blocking dielectric layer 52 may comprise a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one non-metallic element, such as nitrogen. In one embodiment, the blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride).

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Lanthanum oxide (LaO)₂) Yttrium oxide (Y)₂O₃) Tantalum oxide (Ta)₂O₅) Silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer may be deposited, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Pulsed Laser Deposition (PLD), liquid source atomized chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, although lesser and greater thicknesses may also be employed. Subsequently, the dielectric metal oxide layer may serve as a dielectric material portion that blocks stored charge from leaking to the control gate electrode. In one embodiment, the barrier dielectric layer 52 comprises aluminum oxide. In one embodiment, the blocking dielectric layer 52 may include a plurality of dielectric metal oxide layers having different material compositions.

Alternatively or in addition, the blocking dielectric layer 52 may comprise a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may comprise silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 may be formed by a conformal deposition method, such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be employed. Alternatively, the blocking dielectric layer 52 may be omitted, and the backside blocking dielectric layer may be formed after forming a backside recess on the surface of the memory film to be formed later.

Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of charge trapping material including a dielectric charge trapping material (which may be silicon nitride, for example). Alternatively, the charge storage layer 54 may comprise a continuous layer or patterned discrete portions of conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within the lateral recesses. In one embodiment, charge storage layer 54 comprises a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer.

In another embodiment, the sacrificial material layer 42 may be recessed laterally relative to the sidewalls of the insulating layer 32, and a combination of a deposition process and an anisotropic etching process may be employed to form the charge storage layer 54 as a plurality of vertically spaced apart memory material portions. Although the present disclosure is described with an embodiment in which charge storage layer 54 is a single continuous layer, embodiments are expressly contemplated herein in which charge storage layer 54 is replaced by a plurality of vertically spaced apart portions of memory material (which may be portions of charge trapping material or electrically isolated portions of conductive material).

The charge storage layer 54 may be formed as a single charge storage layer of uniform composition, or may include a stack of a plurality of charge storage layers. The plurality of charge storage layers, if employed, may comprise a plurality of spaced apart floating gate material layers containing conductive material (e.g., metals such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and/or semiconductor material (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or in addition, the charge storage layer 54 may include an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage layer 54 may comprise conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage layer 54 may be formed, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of charge storage layer 54 may be in the range of 2nm to 20nm, but lesser and greater thicknesses may also be employed.

The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling may be performed by hot carrier injection or by fowler-nordheim tunneling induced charge transfer, depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunnel dielectric layer 56 may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be employed.

The optional first semiconductor channel layer 601 includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 includes amorphous silicon or polysilicon. The first semiconductor channel layer 601 may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the first semiconductor channel layer 601 may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be employed. A cavity 49' is formed in the volume of each reservoir opening 49 that is not filled with a deposited material layer (52,54,56, 601).

Referring to fig. 13D, the optional first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 are sequentially anisotropically etched using at least one anisotropic etching process. Portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 positioned above the top surface of the insulating cap layer 70 may be removed by at least one anisotropic etching process. In addition, horizontal portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 at the bottom of each cavity 49' may be removed to form an opening in the remaining portions thereof. Each of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 may be etched by an anisotropic etching process.

Each remaining portion of the first semiconductor channel layer 601 may have a tubular configuration. The charge storage layer 54 may include a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 may include a vertical stack of charge storage regions that store charge when programmed. In one embodiment, the charge storage layer 54 may be a charge storage layer, wherein each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

The surface of the pedestal channel portion 11 (or the surface of the semiconductor substrate layer 10 in the case where the pedestal channel portion 11 is not employed) may be physically exposed below the opening through the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each cavity 49 'may be vertically recessed such that the recessed semiconductor surface below the cavity 49' is vertically offset from the topmost surface of the pedestal channel portion 11 (or semiconductor substrate layer 10 if pedestal channel portion 11 is not employed) by a recessed distance. A tunneling dielectric layer 56 is positioned over charge storage layer 54. A set of blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 in memory opening 49 form a memory film 50 that includes a plurality of charge storage regions (e.g., embodied as charge storage layer 54) that are insulated from the surrounding material by blocking dielectric layer 52 and tunneling dielectric layer 56. In one embodiment, the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 may have vertically coincident sidewalls.

Referring to fig. 13E, the second semiconductor channel layer 602 may be deposited directly on the semiconductor surface of the pedestal channel portion 11 (or on the semiconductor substrate layer 10 if the portion 11 is omitted) and directly on the first semiconductor channel layer 601. The second semiconductor channel layer 602 includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602 includes amorphous silicon or polysilicon. The second semiconductor channel layer 602 may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the second semiconductor channel layer 602 may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be employed. The second semiconductor channel layer 602 may completely fill the cavity in each memory opening 49.

The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is the aggregate of all the semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.

Referring to fig. 13F, in the event that the memory cavity 49' in each memory opening is not completely filled by the second semiconductor channel layer 602, a dielectric core layer 62L may be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L may be deposited by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD) or by a self-planarizing deposition process such as spin-coating.

Referring to fig. 13G, the horizontal portion of the dielectric core layer 62L may be removed, for example, by a recess etch from above the top surface of the insulating cap layer 70. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62. In addition, horizontal portions of the second semiconductor channel layer 602 above the top surface of the insulating cap layer 70 may be removed by a planarization process, which may employ a recess etch or Chemical Mechanical Planarization (CMP). Each remaining portion of the second semiconductor channel layer 602 may be positioned entirely within the memory opening 49 or entirely within the support opening 19. Each contiguous pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 may collectively form a vertical semiconductor channel 60 through which current may flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds portions of the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 collectively comprise a memory film 50 that can store charge with macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and may be subsequently formed after the backside recess is formed. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a persistent memory device, such as a retention time in excess of 24 hours.

Referring to fig. 13H, the top surface of each dielectric core 62 may be further recessed into each memory opening, for example by a recess etch to a depth between the top surface of the insulating cap layer 70 and the bottom surface of the insulating cap layer 70. Drain region 63 may be formed by depositing a doped semiconductor material within each recessed region above dielectric core 62. The drain region 63 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of drain region 63 may be in the range of 5.0 x 1019/cm3 to 2.0 x 1021/cm3, although lesser and greater dopant concentrations may also be employed. The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from over the top surface of the insulating cap layer 70, such as by Chemical Mechanical Planarization (CMP) or a recess etch, to form drain regions 63.

Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. Memory stack structure 55 is a combination of a semiconductor channel, a tunneling dielectric layer, a plurality of memory elements embodied as part of charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of pedestal channel portion 11 (if present), memory stack structure 55, dielectric core 62, and drain region 63 within memory opening 49 is referred to herein as a memory opening fill structure (11,55,62, 63).

Referring to fig. 14, an exemplary structure after the processing step of fig. 13H is shown. Each combination of pedestal channel portion 11 (if present) within each support opening 19, memory film 50, vertical semiconductor channel 60, dielectric core 62, and drain region 63 fills the respective support opening 19 and constitutes a support pillar structure 20.

Referring to fig. 15A and 15B, a drain-level dielectric material layer 73 may be formed over the insulating cap layer 70 and the backward stepped dielectric material portion 65. The drain-level dielectric material layer 73 comprises a dielectric material such as silicon oxide, organosilicate glass, silicon nitride, or a combination thereof. In one implementation, the drain-level dielectric material layer 73 may comprise silicon oxide. The thickness of the drain-level dielectric material layer 73 may be in the range of 30nm to 600nm, such as 60nm to 300nm, although lesser and greater thicknesses may also be employed.

A layer of photoresist (not shown) may be applied over the drain-level dielectric material layer 73 and lithographically patterned to form openings in the regions between the blocks of the memory stack structure 55. The pattern in the photoresist layer may be transferred through the drain level dielectric material layer 73, the insulating cap layer 70, the alternating stacks (32,42), and/or the retro-stepped dielectric material portions 65 using an anisotropic etch to form backside trenches 79. The backside trench 79 extends vertically at least to the top surface of the substrate (9,10) and laterally extends through the memory array region 100 and the contact region 300.

Each subset of memory stack structures 55 located between a pair of adjacent backside trenches 79 constitutes a block of memory stack structures 55. Each subset of the memory stack structures 55 located between a pair of adjacent back-side trenches of the entire set of back-side trenches 79 and the drain select level isolation dielectric structure 124 constitute a sub-block of the memory stack structures 55. Each block of memory stack structure 55 includes two or more sub-blocks of memory stack structure 55. Subsequently, the sacrificial material layer 42 and the sacrificial spacer 122 have portions of conductive material.

Referring to fig. 16 and 17A, an etchant may be introduced into the backside trench 79, for example, using an etching process, which etches the second material of the sacrificial material layer 42 selectively to the first material of the insulating layer 32. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. A laterally undulating cavity 123 extending through each drain select level and laterally along the first horizontal direction hd1 may form a volume from which sacrificial spacer 122 is removed. The sacrificial material layer 42 and the sacrificial spacers 122 may be removed during the same isotropic etching process.

The second material of the sacrificial material layer 42 and the material of the sacrificial spacer 122 may be removed in a manner that is selective to the first material of the insulating layer 32, the material of the retro-stepped dielectric material portion 65, the semiconductor material of the semiconductor material layer 10, and the outermost material of the memory film 50. In one embodiment, the sacrificial material layer 42 and the sacrificial spacer 122 may comprise silicon nitride, and the material of the insulating layer 32, the support post structures 20, and the retro-stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide.

The etching process of selectively removing the second material with respect to the first material and the outermost layer of the memory film 50 may be a wet etching process using a wet etching solution, or may be a gas-phase (dry) etching process of introducing an etchant into the backside trench 79 in a vapor phase. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process may be a wet etching process that immerses the exemplary structure in a wet etch bath comprising phosphoric acid, which etches silicon nitride selectively to silicon oxide, silicon, and various other materials employed in the art. The support pillar structures 20, the retro-stepped dielectric material portions 65, and the memory stack structures 55 provide structural support when the backside recesses 43 are present within the volume previously occupied by the sacrificial material layer 42.

Each backside recess 43 may be a laterally extending cavity having a lateral dimension greater than a vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 may be greater than the height of the backside recess 43. A plurality of backside recesses 43 may be formed in the volume of the second material from which the sacrificial material layer 42 is removed. The memory openings in which the memory stack structures 55 are formed are referred to herein as front-side openings or front-side cavities, in contrast to the backside recesses 43. In one implementation, the memory array region 100 includes a monolithic three-dimensional array of NAND strings having a plurality of device levels disposed above a substrate (9, 10). In this case, each backside recess 43 may define a space for receiving a respective word line of the monolithic three-dimensional NAND string array.

Each lateral relief cavity 123 may have a uniform width at each level of the insulating layer 32 located between a pair of drain select levels. Each sacrificial spacer 122 has the same shape as the laterally undulating cavity 123 formed by removing the sacrificial spacer 122. Thus, each laterally undulating cavity 123 has a laterally undulating horizontal cross-sectional shape and a uniform width, which is the width of the sacrificial spacer 122.

Each of the plurality of backside recesses 43 may extend substantially parallel to a top surface of the substrate (9, 10). The backside recess 43 may be vertically defined by a top surface of the lower insulating layer 32 and a bottom surface of the cover insulating layer 32. In one embodiment, each of the backside recesses 43 may have a uniform height throughout.

The optional pedestal channel portion 11 and the physically exposed surface portion of the semiconductor material layer 10 may be converted into a dielectric material portion by thermally and/or plasma converting the semiconductor material into a dielectric material. For example, thermal conversion and/or plasma conversion may be employed to convert a surface portion of each pedestal channel portion 11 into a tubular dielectric spacer 116 and to convert each physically exposed surface portion of the layer of semiconductor material 10 into a planar dielectric portion 616. In one embodiment, each tubular dielectric spacer 116 may be topologically homeomorphic, i.e., substantially annular. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without breaking a hole or forming a new hole into the shape of the torus. The tubular dielectric spacer 116 comprises a dielectric material comprising the same semiconductor element as the pedestal channel portion 11 and additionally comprises at least one non-metallic element such as oxygen and/or nitrogen, such that the material of the tubular dielectric spacer 116 is a dielectric material. In one embodiment, the tubular dielectric spacers 116 may comprise a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the base channel portion 11. Likewise, each planar dielectric portion 616 includes a dielectric material that includes the same semiconductor element as the layer of semiconductor material and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of planar dielectric portion 616 is a dielectric material. In one embodiment, planar dielectric portion 616 may comprise a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of semiconductor material layer 10.

Referring to fig. 17B, a backside blocking dielectric layer 44 may optionally be formed. Backside blocking dielectric layer 44 (if present) comprises a dielectric material that serves as a control gate dielectric for a control gate subsequently formed in backside recess 43. The backside blocking dielectric layer is optional with the presence of the blocking dielectric layer 52 within each memory opening. In the case where the blocking dielectric layer 52 is omitted, a backside blocking dielectric layer is present.

A backside blocking dielectric layer 44 may be formed in the backside recesses 43, in the lateral relief cavities 123, and on the sidewalls of the backside trenches 79. The backside blocking dielectric layer 44 may be formed directly on horizontal surfaces of the insulating layer 32 and directly on physically exposed sidewalls of the drain select level isolation dielectric structures 124, physically exposed sidewalls of the insulating layer 32 surrounding each lateral insulating cavity 123, and sidewalls of the memory stack structures 55 within the backside recess 43. The backside blocking dielectric layer 44 may be formed as a single continuous layer of material. If the backside blocking dielectric layer 44 is formed, it is optional to form the tubular dielectric spacers 116 and the planar dielectric portion 616 prior to forming the backside blocking dielectric layer 44. In one embodiment, the backside blocking dielectric layer 44 may be formed by a conformal deposition process such as Atomic Layer Deposition (ALD). The backside blocking dielectric layer 44 may consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer 44 may be in the range of 1nm to 15nm, such as 2nm to 6nm, although lesser and greater thicknesses may also be employed.

The dielectric material of the backside blocking dielectric layer 44 may be a dielectric metal oxide (such as aluminum oxide), a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one lanthanide element. Alternatively or in addition, the backside blocking dielectric layer may comprise a silicon oxide layer. The backside barrier dielectric layer may be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The thickness of the backside blocking dielectric layer may be in the range of 1nm to 10nm, but smaller and larger thicknesses may also be employed. A backside blocking dielectric layer is formed on the sidewalls of the backside trench 79, the horizontal surfaces and sidewalls of the insulating layer 32, the portions of the sidewall surfaces of the memory stack structure 55 that are physically exposed to the backside recess 43, and the top surface of the planar dielectric portion 616. A backside cavity 79' exists within the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer.

Referring to fig. 17C, a metal barrier layer 46A may be deposited in the backside recesses 43, in the lateral relief cavities 123, on the sidewalls of the at least one backside trench 79, and over the top surface of the contact level dielectric layer 73. The metal barrier layer 46A comprises a conductive metal material that can serve as a diffusion barrier and/or adhesion promoting layer for subsequently deposited metallic filler materials. The metallic barrier layer 46A may comprise a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer 46A may be deposited by a conformal deposition process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The thickness of the metallic barrier layer 46A may be in the range of 2nm to 8nm, such as 3nm to 6nm, although lesser and greater thicknesses may also be employed. In one embodiment, the metallic barrier layer 46A may consist essentially of a conductive metal nitride such as TiN.

Referring to fig. 17D and 18A-18C, a metallic fill material is deposited on the physically exposed surface of the metallic barrier layer 46A to form a metallic fill material layer 46B. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic filler material layer 46B may consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer 46B may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic filler material layer 46B may consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas such as WF6 may be used to deposit the metallic filler material layer 46B. In one embodiment, the metallic filler material layer 46B may be a tungsten layer including residual-grade fluorine atoms as impurities. The metallic filler material layer 46B is spaced apart from the insulating layer 32 and the memory stack structure 55 by a metallic barrier layer 46A, the metallic barrier layer 46A being a metallic barrier layer that prevents fluorine atoms from diffusing therethrough.

The deposition of the at least one conductive material, such as the materials of the metallic barrier layer 46A and the metallic filler material layer 46B, simultaneously forms the conductive layer 46, the conductive connector spacer 126, and the continuous metallic material layer 46L. A plurality of conductive layers 46 may be formed in the plurality of backside recesses 43. A plurality of conductive connector spacers 126 may be formed in the plurality of laterally undulating cavities 123. A continuous layer of metallic material 46L may be formed on the sidewalls of each backside trench 79 and over the contact level dielectric layer 73. Each of the conductive layer 46, the conductive connector spacer 126, and the continuous metallic material layer 46L includes a respective portion of the metallic barrier layer 46A and a respective portion of the metallic fill material layer 46B.

A conductive layer 46 is formed within the volume of the sacrificial material layer 42. Conductive connector spacers 126 are formed within the volume of sacrificial spacer 122. Each conductive connector spacer 126 provides an electrical connection between two or more uppermost layers of the conductive layer 46, which is a drain select level conductive layer.

A pair of conductive connector spacers 126 and a drain select level isolation dielectric structure 124 are formed within each drain select level isolation trench 119. The pair of conductive connector spacers 126 includes a first conductive connector spacer and a second conductive connector spacer that are laterally spaced apart and electrically isolated from each other by the drain select level isolation dielectric structure 124. The first conductive connector spacer 126 and a first strip portion of the two or more uppermost layers 46SGD (e.g., drain select gate electrodes) in the conductive layer 46 are formed as a first continuous conductive structure. The second conductive connector spacer and the second strip portions of the two or more uppermost layers 46SGD in the conductive layer 46 are formed as a second continuous conductive structure. One or more of the lowermost layers 46SGS of the conductive layers 46 form source select gate electrodes. The remaining conductive layer 46WL serves as a word line/control gate electrode.

The insulating layers 32 and the conductive layers 46 form an alternating stack (32, 46). A plurality of alternating stacks (32,46) are formed such that each alternating stack (32,46) is laterally spaced from an adjacent alternating stack (32,46) by a backside trench 79. In one implementation, a pair of backside trenches 79 may extend laterally along a longitudinal direction (i.e., the first horizontal direction hd1, e.g., the word line direction) of the drain select level isolation dielectric structure 124. In one embodiment, a first strip portion is formed between the drain select level isolation dielectric structure 124 and one of the pair of backside trenches 79, and a second strip portion is formed between the drain select level isolation dielectric structure 124 and the other of the pair of backside trenches 79.

Thus, each sacrificial material layer 42 may be replaced by a conductive layer 46. Each sacrificial spacer 122 may be replaced with a conductive connector spacer 126. A backside cavity 79' is present in the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44 and the continuous metallic material layer 46L. A tubular dielectric spacer 116 laterally surrounds the pedestal channel portion 11. In forming the conductive layer 46, the bottommost conductive layer 46 laterally surrounds each tubular dielectric spacer 116.

Referring to fig. 19, the deposited metallic material of the continuous layer of conductive material 46L is etched back, for example by isotropic wet etching, anisotropic dry etching, or a combination thereof, from the sidewalls of each backside trench 79 and from above the contact level dielectric layer 73. Each remaining portion of the deposited metal material in the backside recesses 43 constitutes a conductive layer 46. Each conductive layer 46 may be a conductive line structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46.

Referring to fig. 20A and 20B, a layer of insulating material may be formed in the at least one backside trench 79 and over the drain-level dielectric material layer 73 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The layer of insulating material comprises an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the layer of insulating material may comprise silicon oxide. The layer of insulating material may be formed, for example, by Low Pressure Chemical Vapor Deposition (LPCVD) or Atomic Layer Deposition (ALD). The thickness of the layer of insulating material may be in the range of 1.5nm to 60nm, but lesser and greater thicknesses may also be employed.

If a backside barrier dielectric layer 44 is present, a layer of insulating material may be formed directly on the surface of the backside barrier dielectric layer 44 and directly on the sidewalls of the conductive layer 46. If backside blocking dielectric layer 44 is not employed, a layer of insulating material can be formed directly on the sidewalls of insulating layer 32 and directly on the sidewalls of conductive layer 46.

An anisotropic etch is performed to remove horizontal portions of the layer of insulating material from above the drain-level dielectric material layer 73 and at the bottom of each backside contact trench 79. Each remaining portion of the layer of insulating material constitutes an insulating spacer 74. A backside cavity 79' exists within the volume surrounded by each insulating spacer 74.

The anisotropic etch process may continue with or without an etch chemistry change to remove the optional backside blocking dielectric layer 44 and the portion of the planar dielectric portion 616 that is located below the opening through the insulating spacer 74. The top surface of the semiconductor material layer 10 may be physically exposed at the bottom of each backside contact trench 79.

Source regions 61 may be formed at surface portions of the semiconductor material layer 10 below each backside cavity 79' by implanting electrical dopants into the physically exposed surface portions of the semiconductor material layer 10. Each source region 61 is formed in a surface portion of the substrate (9,10) that is located below a respective opening through the insulating spacer 74. Each source region 61 may have a lateral extent greater than a lateral extent of an opening through the insulating spacer 74 due to the diffusion of implanted dopant atoms during the implantation process and the lateral diffusion of implanted dopant atoms during the subsequent activation anneal process. Each source region 61 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa.

The upper portion of the layer of semiconductor material 10 extending between the source region 61 and the plurality of pedestal channel portions 11 constitutes a horizontal semiconductor channel 59 for a plurality of field effect transistors. The horizontal semiconductor channels 59 are connected to the plurality of vertical semiconductor channels 60 through the respective base channel portions 11. The horizontal semiconductor channel 59 contacts the source region 61 and the plurality of pedestal channel portions 11. The bottommost conductive layer 46 provided when forming the conductive layers 46 within the alternating stack (32,46) may comprise a select gate electrode of a field effect transistor. Each source region 61 is formed in an upper portion of a semiconductor substrate (9, 10).

Contact via structures 76 may be formed within each cavity 79'. Each contact via structure 76 may fill a respective cavity 79'. The contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume of the backside contact trench 79 (i.e., the backside cavity 79'). For example, the at least one conductive material may include a conductive pad 76A and a conductive filler material portion 76B. The conductive pad 76A may comprise a conductive metal pad such as TiN, TaN, WN, TiC, TaC, WC, alloys thereof, or stacks thereof. The thickness of the conductive pad 76A may be in the range of 3nm to 30nm, although lesser and greater thicknesses may also be employed. The conductive filler material portion 76B may comprise a metal or metal alloy. For example, the conductive fill material portion 76B may include W, Cu, Al, Co, Ru, Ni, alloys thereof, or stacks thereof.

The at least one conductive material may be planarized using a layer 73 of drain-level dielectric material overlying the alternating stack (32,46) as a stop layer. If a Chemical Mechanical Planarization (CMP) process is employed, the drain-level dielectric material layer 73 may serve as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside contact trench 79 constitutes a backside contact via structure 76. A backside contact via structure 76 extends through the alternating stack (32,46) and contacts a top surface of the source region 61. If a backside blocking dielectric layer 44 is employed, the backside contact via structure 76 may contact sidewalls of the backside blocking dielectric layer 44.

Referring to fig. 21A and 21B, additional contact via structures (88,86,8P) may be formed through the contact level dielectric layer 73, and optionally through the retro-stepped dielectric material portion 65. For example, a drain contact via structure 88 may be formed through the contact level dielectric layer 73 on each drain region 63. Word line contact via structures 86 may be formed on conductive layer 46 through contact level dielectric layer 73 and through stepped-back dielectric material portion 65. The peripheral device contact via structures 8P may be formed directly on the corresponding nodes of the peripheral devices through the backward stepped dielectric material portions 65.

Referring to all of the drawings of the present disclosure, there is provided a three-dimensional memory device including: an alternating stack of insulating layers 32 and conductive layers 46 positioned over the substrate (9,10), and a memory stack structure 55 extending through the alternating stack (32, 46). Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60 contacting an inner sidewall of the memory film 50. The two or more uppermost layers 46SGD in the conductive layer 46 include a first stripe portion and a second stripe portion laterally spaced apart from each other by the drain select level isolation dielectric structure 124. The drain select level isolation dielectric structure 124 may comprise an alternating sequence of a pair of non-concave (e.g., flat or convex) sidewall portions (12P1 or 12P2) and concave sidewall portions (12C1 or 12C2), as shown in fig. 18B and 18C. Each concave sidewall portion (12C1,12C2) is equidistant from a sidewall of a respective one of memory stack structures 55.

In one embodiment, the alternating sequence of the pair of non-concave (e.g., flat or convex) sidewall portions (12P1 or 12P2) and concave sidewall portions (12C1 or 12C2) comprises: a first alternating sequence of first flat sidewall portions 12P1 and first concave sidewall portions 12C1, and a second alternating sequence of second flat sidewall portions 12P2 and second concave sidewall portions 12C 2. In one embodiment, the first planar sidewall portion 12P1 lies within a first vertical plane VP1 and the second planar sidewall portion 12P2 lies within a second vertical plane VP2 that is parallel to the first vertical plane VP1, as shown in fig. 18B and 18C.

In one embodiment, the two or more uppermost ones 46SGD of the conductive layers 46 comprise drain select level conductive layers, and a subset of the conductive layers 46 that are below the two or more uppermost ones of the conductive layers 46 comprise word line conductive layers 46WL of the memory stack structure 55.

In one embodiment, the three-dimensional memory device may further include: a first conductive connector spacer 126A connected to each first stripe portion of the two or more uppermost layers 46SGD in the conductive layer 46; and a second conductive connector spacer 126B connected to each second strip portion of the two or more uppermost layers 46SGD in the conductive layer 46, as shown in fig. 18C.

In one implementation, each of the first and second conductive connector spacers (126A,126B) includes an alternating sequence of conductive non-concave (e.g., flat or convex) sidewall portions 6P and conductive concave sidewall portions 6C that are equidistant from a respective one of the memory stack structures 55, as shown in fig. 18B and 18C. In one embodiment, the first and second conductive connector spacers (126A,126B) comprise the same material as the conductive layer 46.

In one embodiment, the three-dimensional memory device further includes a backside blocking dielectric layer 44 that includes a horizontal portion between each pair of adjacent insulating layers 32 and conductive layers 46, and a vertical portion between the drain select level isolation dielectric structure 124 and the first and second conductive connector spacers (126A, 126B). In one embodiment, the backside blocking dielectric layer 44 further includes additional vertical portions that contact sidewalls of a subset of the insulating layers 32 between a lowermost of the two or more uppermost layers 46SGD of the conductive layers 46 and a topmost of the two or more uppermost layers 46SGD of the conductive layers 46, i.e., between a bottommost drain select level conductive layer 46SGD and a topmost drain select level conductive layer 46SGD, as shown in fig. 18B.

In one embodiment, the first conductive connector spacer 126A and a first strip portion of the two or more uppermost layers 46SGD of the conductive layers 46 constitute a first continuous conductive structure, and the second conductive connector spacer 126B and a second strip portion of the two or more uppermost layers 46SGD of the conductive layers 46 constitute a second continuous conductive structure.

In one embodiment, the three-dimensional memory device may further include a pair of backside trenches 79 extending vertically through the alternating stack (32,46) and laterally along a longitudinal direction of the drain select level isolation dielectric structure 124. The first strip portion is located between the drain select level isolation dielectric structure 124 and one of the pair of backside trenches 79, and the second strip portion is located between the drain select level isolation dielectric structure 124 and the other of the pair of backside trenches 79.

In one embodiment, the alternating stack (32,46) includes a plateau region in which each conductive layer 46 except the topmost conductive layer 46 within the alternating stack (32,46) extends laterally further than any overlying conductive layer 46 within the alternating stack (32, 46). The land region includes a stepped surface of the alternating stack (32,46) that extends continuously from a lowermost layer in the alternating stack (32,46) to a topmost layer in the alternating stack (32, 46). The support post structures 20 extend through the stepped surface and through a rearwardly stepped dielectric material portion 65 covering the stepped surface.

Exemplary structures may include three-dimensional memory devices. In one embodiment, the three-dimensional memory device comprises a vertical NAND memory device. Conductive layer 46 can include or can be electrically connected to a respective word line of a monolithic three-dimensional NAND memory device. The substrate (9,10) may comprise a silicon substrate. A vertical NAND memory device can include a monolithic three-dimensional array of NAND strings over a silicon substrate. At least one memory cell in a first device level of the monolithic three-dimensional NAND string array (e.g., implemented as part of charge storage layer 54 at the level of conductive layer 46 WL) may be located above another memory cell in a second device level of the monolithic three-dimensional NAND string array (e.g., implemented as another part of charge storage layer 54 at the level of another conductive layer 46). The silicon substrate may contain integrated circuitry including driver circuitry for the memory devices positioned thereon. Conductive layer 46WL may include a plurality of control gate electrodes having a stripe shape extending substantially parallel to a top surface of substrate (9,10), e.g., between a pair of backside trenches 79. The plurality of control gate electrodes includes at least a first control gate electrode positioned in a first device level and a second control gate electrode positioned in a second device level. The monolithic three dimensional NAND string array can include: a plurality of semiconductor channels (59,11,60), wherein at least one end portion (60) of each of the plurality of semiconductor channels (59,11,60) extends substantially perpendicular to a top surface of the substrate (9, 10); and a plurality of charge storage elements (e.g., implemented as portions of charge trapping material). Each charge storage element may be positioned adjacent a respective one of the plurality of semiconductor channels (59,11, 60).

Embodiments of the present disclosure provide drain select gate electrodes located at multiple levels and electrically shorted to each other by respective conductive connector spacers 126. Each conductive connector spacer 126 is self-aligned with the memory stack structure 55 and is laterally spaced apart from adjacent conductive connector spacers 124 by a drain select level isolation dielectric structure 124. The drain select level isolation dielectric structure 124 is self-aligned with the conductive connector spacer 126 and the memory stack structure 55. The multiple levels of the drain select gate electrode reduce the overall resistance of the drain select gate electrode. The self-alignment of the conductive connector spacers 126 with the memory stack structures 55 minimizes the volume occupied by the drain select level isolation dielectric structures 124 and thereby provides a more compact design layout for a three-dimensional memory device.

While the foregoing refers to certain preferred embodiments, it is to be understood that the disclosure is not so limited. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and such modifications are intended to be within the scope of the present disclosure. Embodiments employing specific structures and/or configurations are shown in the present disclosure, it being understood that the present disclosure may be practiced in any other compatible structures and/or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered to be impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and conductive layers positioned over a substrate;

a drain select level isolation dielectric structure; and

memory stack structures extending through the alternating stack, wherein each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting inner sidewalls of the memory film,

wherein:

two or more uppermost layers of the conductive layer comprise first and second stripe portions laterally spaced apart from each other by the drain select level isolation dielectric structure; and is

The drain select level isolation dielectric structure comprises an alternating sequence of a pair of non-concave sidewall portions and concave sidewall portions.

2. The three-dimensional memory device of claim 1, the alternating sequence of the pair of non-concave sidewall portions and concave sidewall portions comprising:

a first alternating sequence of first flat sidewall portions and first concave sidewall portions; and

a second alternating sequence of second flat sidewall portions and second concave sidewall portions, wherein:

the first planar sidewall portion lies in a first vertical plane; and is

The second planar sidewall portion lies in a second vertical plane parallel to the first vertical plane.

3. The three-dimensional memory device of claim 1, wherein:

each of the concave sidewall portions is equidistant from a sidewall of a respective one of the memory stack structures;

the two or more uppermost ones of the conductive layers comprise a drain select level conductive layer; and is

A subset of the conductive layers that are below the two or more uppermost ones of the conductive layers comprise word line conductive layers of the memory stack structure.

4. The three-dimensional memory device of claim 1, further comprising:

a first conductive connector spacer connected to each of the first strap portions of the two or more uppermost layers in the conductive layer; and

a second conductive connector spacer connected to each of the second strip portions of the two or more uppermost layers in the conductive layer.

5. The three-dimensional memory device of claim 4, wherein each of the first and second conductive connector spacers comprises an alternating sequence of conductive non-concave sidewall portions and conductive concave sidewall portions.

6. The three-dimensional memory device of claim 4, wherein the first conductive connector spacer and the second conductive connector spacer each comprise a same material as the conductive layer.

7. The three-dimensional memory device of claim 4, further comprising a backside blocking dielectric layer comprising a horizontal portion between each pair of adjacent insulating layers and conductive layers and a vertical portion between the drain select level isolation dielectric structure and the first and second conductive connector spacers.

8. The three-dimensional memory device of claim 7, wherein the backside blocking dielectric layer further comprises additional vertical portions that contact sidewalls of a subset of the insulating layers between a bottommost one of the two or more uppermost layers in the conductive layer and a topmost one of the two or more uppermost layers in the conductive layer.

9. The three-dimensional memory device of claim 4, wherein:

the first conductive connector spacer and the first strip portions of the two or more uppermost layers of the conductive layers constitute a first continuous conductive structure; and is

The second conductive connector spacer and the second strip portions of the two or more uppermost layers of the conductive layers constitute a second continuous conductive structure.

10. The three-dimensional memory device of claim 1, further comprising a pair of backside trenches extending vertically through the alternating stack and laterally along a longitudinal direction of the drain select level isolation dielectric structure,

wherein:

the first stripe portion is located between the drain select level isolation dielectric structure and one of the pair of backside trenches; and is

The second strip portion is located between the drain select level isolation dielectric structure and the other one of the pair of backside trenches.

11. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

a subset of the conductive layers includes or is electrically connected to a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises a monolithic three-dimensional NAND string array over the silicon substrate;

at least one memory cell in a first device level of the monolithic three-dimensional NAND string array is positioned above another memory cell in a second device level of the monolithic three-dimensional NAND string array;

the silicon substrate contains an integrated circuit including driver circuitry for the memory device positioned thereon;

the conductive layer comprises a plurality of control gate electrodes having a stripe shape extending substantially parallel to the top surface of the substrate and including at least a first control gate electrode in the first device level and a second control gate electrode in the second device level; and is

The monolithic three dimensional NAND string array comprises:

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the top surface of the substrate, an

A plurality of charge storage elements, each charge storage element positioned adjacent to a respective one of the plurality of semiconductor channels.

12. A three-dimensional memory device, comprising:

memory stack structures extending through the alternating stack, wherein each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;

a first conductive connector spacer connected to each first stripe portion of two or more uppermost layers in the conductive layer; and

a second conductive connector spacer connected to each second strip portion of the two or more uppermost layers in the conductive layer,

wherein each of the first and second conductive connector spacers comprises an alternating sequence of conductive non-concave sidewall portions and conductive concave sidewall portions.

13. A method of forming a three-dimensional memory device, comprising:

forming an alternating stack of insulating layers and sacrificial material layers over a substrate;

forming a drain select level isolation trench through two or more uppermost layers of the sacrificial material layers;

forming sacrificial spacers on sidewalls of the drain select level isolation trenches;

forming memory stack structures extending through the alternating stacks, wherein each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film; and

partially replacing the sacrificial material layer and the sacrificial material with a conductive material.

14. The method of claim 13, wherein:

forming a conductive layer within a volume of the layer of sacrificial material;

forming a conductive connector spacer within a volume of the sacrificial spacer;

each of the conductive connector spacers provides an electrical connection between two or more uppermost layers of the conductive layer;

after forming the sacrificial spacer, a cavity exists within an unfilled volume of the drain select level isolation trench; and is

The method also includes forming a drain select level isolation dielectric structure by depositing a dielectric material within the cavity.

15. The method of claim 14, further comprising:

forming a memory opening through the alternating stack; and

a sacrificial memory opening fill structure is formed in the memory opening,

wherein the drain select level isolation trenches are formed by an anisotropic etch process that etches the material of the insulating layer and sacrificial material layers selective to the material of the sacrificial memory opening fill structures.

16. The method of claim 15, further comprising applying and patterning a photoresist layer over the alternating stack to form linear openings having a uniform width, wherein:

longitudinal sidewalls of the photoresist layer overlie respective rows of sacrificial memory opening fill structures; and is

The photoresist layer is used as an etch mask during the anisotropic etch process.

17. The method of claim 15, wherein:

the drain select level isolation trench is formed having a pair of longitudinal sidewalls;

each longitudinal sidewall of the pair of longitudinal sidewalls comprises an alternating sequence of a pair of non-convex sidewall portions and convex sidewall portions; and is

Each of the convex sidewall portions includes a sidewall of a respective one of the sacrificial memory opening fill structures.

18. The method of claim 17, further comprising:

depositing and anisotropically etching a layer of sacrificial spacer material in the drain select level isolation trench, wherein the sacrificial spacer comprises a remaining portion of the layer of sacrificial spacer material;

removing the sacrificial material layer and the sacrificial spacer using the same isotropic etching process; and

the conductive layer and the conductive connector spacer are simultaneously formed by depositing at least one conductive material.

19. The method of claim 15, further comprising replacing the sacrificial memory opening fill structures with memory stack structures after forming the sacrificial spacers, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel that contacts inner sidewalls of the memory film.

20. The method of claim 19, wherein:

the sacrificial spacer is formed on a convex sidewall of the sacrificial memory opening fill structure and the two or more uppermost non-convex sidewalls in the sacrificial material layer; and is

Forming the conductive layer and the conductive connector spacer after forming the memory stack structure.

21. The method of claim 14, wherein:

the conductive connector spacer comprises a first conductive connector spacer and a second conductive connector spacer laterally spaced from and electrically isolated from each other by the drain select level isolation dielectric structure;

the first conductive connector spacer and the first strip portions of the two or more uppermost layers of the conductive layers are formed as a first continuous conductive structure; and is

The second conductive connector spacer and the second strip portions of the two or more uppermost layers of the conductive layers are formed as a second continuous conductive structure.

22. The method of claim 21, further comprising forming a pair of backside trenches extending vertically through the alternating stack and laterally along a longitudinal direction of the drain select level isolation dielectric structure,

wherein:

the first stripe portion is formed between the drain select level isolation dielectric structure and one of the pair of backside trenches; and is

The second stripe portion is formed between the drain select level isolation dielectric structure and another backside trench of the pair of backside trenches.