CN112466883A - Three-dimensional NAND memory and preparation method thereof - Google Patents
Three-dimensional NAND memory and preparation method thereof Download PDFInfo
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- CN112466883A CN112466883A CN202011328734.4A CN202011328734A CN112466883A CN 112466883 A CN112466883 A CN 112466883A CN 202011328734 A CN202011328734 A CN 202011328734A CN 112466883 A CN112466883 A CN 112466883A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention provides a three-dimensional NAND memory and a preparation method thereof, wherein the method comprises the steps of arranging support holes, wherein the support holes comprise a first support hole and a second support hole which are vertical to each other, the length of the top of the first support hole along a first direction is larger than that of the first support hole along a second direction, and the length of the top of the second support hole along the second direction is larger than that of the second support hole along the first direction, so that the opening area of the support holes is effectively increased, and the difficulty of etching deep holes with high depth-to-width ratio is reduced; meanwhile, the supporting holes are arranged to be mutually vertical, so that the impact reflection effect of non-vertical etching ions on the mask and the hole wall in the etching process can be effectively reduced, and the Bow size of the supporting holes is relieved, so that the supporting holes cannot extrude a process window of a subsequent process; and finally, a functional conductive hole area of the device can be arranged between the adjacent second support holes, so that the opening area of the support holes is effectively increased on the premise of not sacrificing the functional conductive hole area.
Description
Technical Field
The invention belongs to the technical field of semiconductor design and manufacture, and particularly relates to a three-dimensional NAND memory and a preparation method thereof.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to address the difficulties encountered with flat flash memory and to pursue lower production costs per unit cell, various three-dimensional (3D) memory structures have come into force, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory, which can enable a greater number of memory cells per memory die in a memory device.
In the preparation process of the 3D NAND memory, a stack structure formed by alternately stacking dielectric layers and sacrificial layers is generally formed at first, and the stack structure comprises a core storage area, a word line connection area and a bottom selection gate lead-out area. A core storage area for storage of information; the word line connecting area is positioned outside the core storage area and used for transmitting control information to the core storage area so as to realize the reading and writing of the information in the core storage area; and the bottom selection gate lead-out area is positioned outside the word line connecting area and is used for transmitting control information to the bottom selection gate of the core storage area. The word line connection region and the bottom selection gate lead-out region are generally provided with support pillars penetrating through the stacked structure to support the stacked structure and prevent the stacked structure from collapsing.
The existing supporting column is generally formed by forming a circular supporting hole and filling an insulating supporting material in the circular supporting hole, but as the number of stacked layers of a stacked structure increases, the etching difficulty of the circular supporting hole gradually increases, a top size large enough to ensure that the supporting hole can be etched to the bottom is required, but even if the bottom is opened by a larger top size, the bottom shape of the supporting hole changes due to the etching load effect, the poor conformality has a negative effect on the supporting effect of the supporting column near the bottom, so that the stacked structure is easily collapsed, and meanwhile, the large top size also makes the Bow size of the supporting hole larger, and extrudes a process window of a subsequent process, so that in the deep hole etching process of the supporting hole, obtaining the supporting hole meeting the process conditions faces a great challenge.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a three-dimensional NAND memory and a method for manufacturing the same, which are used to solve the problems that the three-dimensional NAND memory in the prior art uses a circular support pillar to support a stacked structure, and is prone to collapse and squeeze a process window of a subsequent process.
In order to achieve the above objects and other related objects, the present invention provides a method for fabricating a three-dimensional NAND memory, the method comprising:
providing a substrate, and forming a laminated structure formed by alternately stacking dielectric layers and sacrificial layers on the substrate, wherein the laminated structure comprises a core storage area and a word line connecting area;
forming a channel hole in the core memory region, and forming a memory film and a channel layer in the channel hole;
forming support holes in the word line connection regions, wherein the support holes include first support holes extending in a first direction and second support holes extending in a second direction and communicating with the first support holes, the first direction and the second direction are perpendicular to each other, a top length of the first support holes in the first direction is greater than a top length of the first support holes in the second direction, and a top length of the second support holes in the second direction is greater than a top length of the second support holes in the first direction;
and filling an insulating support material in the support hole to form a support column.
Optionally, the stacked structure further includes a bottom select gate lead-out region; when the support hole is formed in the word line connection region, the support hole is formed in the bottom selection gate lead-out region.
Optionally, a top length of the first support hole in the first direction is more than twice a top length of the first support hole in the second direction, and a top length of the second support hole in the second direction is between one and two times a top length of the second support hole in the first direction.
Optionally, a top length of the first support hole in the second direction is identical to a top length of the second support hole in the first direction.
Optionally, a top length of the first support hole along the first direction is between 730nm and 770nm, a top length of the first support hole along the second direction is between 180nm and 220nm, a top length of the second support hole along the second direction is between 300nm and 340nm, and a top length of the second support hole along the first direction is between 180nm and 220 nm.
Optionally, the preparation method further comprises: removing the sacrificial layer of the laminated structure to form a gap between the adjacent dielectric layers; and filling the gap with a gate layer.
Optionally, removing the sacrificial layer comprises the steps of: forming a gate line isolation groove in the laminated structure; and removing the sacrificial layer through the grid line separation groove by adopting a wet etching process.
Optionally, the first support hole extending along the first direction and the gate line separation groove are parallel to each other.
The present invention also provides a three-dimensional NAND memory comprising:
a substrate;
the stacked structure is formed on the substrate and comprises a core storage area and a word line connection area, wherein the core storage area is provided with a channel hole, a memory film and a channel layer are formed in the channel hole, the word line connection area is provided with a support hole penetrating through the word line connection area, and a support pillar is filled in the support hole;
the supporting holes comprise first supporting holes extending along a first direction and second supporting holes extending along a second direction and communicated with the first supporting holes, the first direction and the second direction are perpendicular to each other, the length of the tops of the first supporting holes along the first direction is larger than that of the tops of the first supporting holes along the second direction, and the length of the tops of the second supporting holes along the second direction is larger than that of the tops of the second supporting holes along the first direction.
Optionally, the memory further comprises: and the bottom selection gate lead-out area is positioned outside the word line connecting area and is provided with the support holes, and the support columns are filled in the support holes.
Optionally, the word line connection area includes a stepped structure, the stepped structure and the bottom selective gate lead-out area are covered with insulating layers, a through hole is formed in the insulating layer, a conductive layer is filled in the through hole, the conductive layer of the word line connection area forms a word line conductor layer, the conductive layer of the bottom selective gate lead-out area forms a bottom selective gate conductive layer, and the word line conductive layer is connected with the gate layer in the stepped structure.
Optionally, a top length of the first support hole in the first direction is more than twice a top length of the first support hole in the second direction, and a top length of the second support hole in the second direction is between one and two times a top length of the second support hole in the first direction.
Optionally, a top length of the first support hole in the second direction is identical to a top length of the second support hole in the first direction.
Optionally, a top length of the first support hole along the first direction is between 730nm and 770nm, a top length of the first support hole along the second direction is between 180nm and 220nm, a top length of the second support hole along the second direction is between 300nm and 340nm, and a top length of the second support hole along the first direction is between 180nm and 220 nm.
Optionally, the stacked structure includes gate layers and dielectric layers stacked alternately, and gate line separation grooves are further formed in the stacked structure.
Optionally, the first support hole extending along the first direction and the gate line separation groove are parallel to each other.
As described above, the three-dimensional NAND memory and the method for manufacturing the same of the present invention have the following advantageous effects:
by arranging the supporting holes between the adjacent grid line spacing groove regions, setting the top length X1 of the first supporting hole along the first direction to be greater than the top length Y1 of the first supporting hole along the second direction, and setting the top length Y2 of the second supporting hole along the second direction to be greater than the top length X2 of the second supporting hole along the first direction, the opening area of the supporting holes is effectively increased, the difficulty of etching the deep hole with the high depth-to-width ratio is reduced, and the shape retention of the hole is improved; meanwhile, the supporting holes are arranged to be mutually vertical, so that the impact reflection effect of non-vertical etching ions on the mask and the hole wall in the etching process can be effectively reduced, and the Bow size of the supporting holes is relieved, so that the supporting holes cannot extrude a process window of a subsequent process; and finally, a functional conductive hole area of the device can be arranged between the adjacent second support holes, so that the opening area of the support holes is effectively increased on the premise of not sacrificing the functional conductive hole area.
Drawings
FIG. 1 shows a top profile SEM image of support pillars in a conventional three-dimensional NAND memory.
FIG. 2 shows an SEM image of the bottom topography of a support pillar in a conventional three-dimensional NAND memory.
FIG. 3 is a SEM image of the cross-sectional profile of a support pillar in a conventional three-dimensional NAND memory.
Fig. 4 is a process flow chart of a method for manufacturing a three-dimensional NAND memory according to a first embodiment of the invention.
Fig. 5 to 16 are schematic structural diagrams showing steps of a method for manufacturing a three-dimensional NAND memory according to a first embodiment of the invention, wherein fig. 15 is a schematic structural diagram of a three-dimensional NAND memory according to a second embodiment of the invention.
FIG. 17 is a top view of a prior art stack structure showing the top topography of the support posts for the word line connection regions and the bottom select gate lead-out regions.
Description of the element reference numerals
100 substrate
101 laminated structure
102 dielectric layer
103 sacrificial layer
104 channel hole
105 memory film
106 channel layer
107 support hole
108 first support aperture
109 second support hole
110 support column
111 gap
112 gate layer
113 grid line isolation groove
114 insulating layer
115 word line conductive layer
116 doped polysilicon layer
117 grid line spacer region
118 bottom select gate conductive layer
119 conductive layer
11 core memory area
12 word line connection region
13 bottom select gate lead-out region
14 upper selection gate lead-out region
S1-S4
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In the process of manufacturing the three-dimensional NAND memory, a stack structure formed by alternately stacking dielectric layers and sacrificial layers is generally formed, the sacrificial layers are subsequently removed to form a gap, and then the gap is filled with a gate layer. In this process, in order to avoid collapse of the stacked structure after the gap is formed, it is usually necessary to form a support hole penetrating through the stacked structure, fill the support hole with an insulating support material, and form a support pillar to support the stacked structure during the replacement of the sacrificial layer with the gate layer. As shown in fig. 1 to 3, a circular hole is generally used as a conventional support hole, but as the number of stacked layers of a stacked structure increases, the difficulty of etching the circular support hole gradually increases, and it can be ensured that the support hole can be etched to the bottom only by increasing the top size of the circular hole, but even if the bottom is opened by a larger top size, the bottom shape of the support hole changes due to the load effect of etching, as shown in fig. 1 and 2, the distance between two adjacent support holes at the top of the support hole is about 267nm, and the distance between two adjacent support holes after etching to the bottom is about 390nm, which is different by about 120nm from top to bottom, which deteriorates the bottom support effect of the support hole; on the other hand, as shown in fig. 3, increasing the top size of the circular hole may also increase the Bow size of the support hole, where the Bow size of the support hole refers to that the support hole formed by etching is not in a shape gradually decreasing from top to bottom, but in a section of the support hole (generally, the section is located in the upper section of the support hole) the Bow size is larger than the top size, similar to a protruding belly, and the Bow size may press the process window of the subsequent process, increase the process difficulty, and easily cause a leakage risk.
In view of the above problems, the inventors of the present invention have conducted extensive studies and believe that when forming a support hole with a high aspect ratio, due to the small size of the opening of the hole, during the etching process, non-vertical etching ions may collide with the sidewall of the mask and then reflect to the sidewall of the hole to accelerate the etching of the sidewall, thereby forming Bow, and based on this knowledge, the inventors consider to design a novel shape of the support hole, and reduce the impact reflection effect of the etching ions while increasing the opening of the support hole, thereby forming a support hole with good conformality and capable of relieving the Bow size, so as to meet the process requirements.
As shown in fig. 4, the present embodiment provides a method for manufacturing a three-dimensional NAND memory, including the following steps:
as shown in fig. 4, 5 and 6, step S1 is performed to provide a substrate 100, and form a stacked structure 101 formed by alternately stacking dielectric layers 102 and sacrificial layers 103 on the substrate 100, where the stacked structure 101 includes a core storage region 11, a word line connection region 12 and a bottom select gate lead-out region 13.
The core memory area 11 is used for storing information, and the core memory area 11 may further include an upper select gate lead-out area 14 to implement transmission of control information to an upper select gate of the core memory area 11; the word line connection region 12 is located at an end region of the stacked structure 101, and is used for transmitting control information to the core storage region 11, so as to realize reading and writing of information in the core storage region 11; the bottom select gate lead-out region 13 is located outside the word line connection region 12, and is configured to transmit control information to the bottom select gate of the core memory region 11.
By way of example, the substrate 100 may be selected according to actual requirements of a device, and may include, but is not limited to, a silicon substrate, a germanium substrate, a silicon germanium substrate, a SOI substrate, a GOI substrate, or the like.
As an example, the stacked structure 101 may be formed by using a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), an atomic layer deposition method (ALD), or the like, the dielectric layer 102 of the stacked structure 101 includes but is not limited to a silicon dioxide layer, the sacrificial layer 103 of the stacked structure 101 includes but is not limited to a silicon nitride layer, and the dielectric layer 102 and the sacrificial layer 103 have a certain selectivity in the same etching/etching process.
As shown in fig. 6, as an example, the word line connection region 12 is etched sequentially to form a word line connection region having a step structure and the insulating layer 114 is covered on the word line connection region 12, and the step structure may facilitate the extraction of the subsequent gate layer 112.
As shown in fig. 4, 7, and 8, step S2 is performed to form a channel hole 104 in the core memory region 11, and form a memory film 105 and a channel layer 106 in the channel hole 104.
As shown in fig. 7, for example, a trench hole 104 may be formed in the core region 11 by using a photolithography process and an etching process, and the trench hole 104 penetrates through the stacked structure 101. When the channel hole 104 is formed, the word line connection region 12 is kept in a shielding state, for example, a photoresist or/and a hard mask is used to shield the word line connection region 12, so that no support hole is formed in the word line connection region 12. Then, a doped polysilicon layer 116 may be formed at the bottom of the channel hole 104 by selective epitaxial growth or the like, and the subsequently formed channel layer 106 is in contact with the doped polysilicon layer 116, so that the doped polysilicon layer 116 may effectively reduce the resistance between the channel layer 106 and a memory common-source line layer (not shown in the figure).
As shown in fig. 8, the memory film 105 includes a blocking layer, a charge trapping layer, and a tunneling layer. As an example, the step of forming the memory film 105 and the channel layer 106 in the channel hole 104 includes: forming a barrier layer on sidewalls of the channel hole 104; forming a charge trapping layer on the blocking layer; forming a tunneling layer on the charge trapping layer; the channel layer 106 is formed on the tunneling layer, and the channel layer 106 is in contact with the doped polysilicon layer 116. The material of the blocking layer includes, but is not limited to, silicon dioxide, the material of the charge trapping layer includes, but is not limited to, silicon nitride, the material of the tunneling layer includes, but is not limited to, silicon dioxide, and the material of the channel layer 106 includes, but is not limited to, p-type doped polysilicon.
As shown in fig. 4 and 9-11, wherein, fig. 10 is a top view of the support holes of the word line connection region and the bottom select gate lead-out region in the stacked structure, fig. 9 is a sectional view taken along line AA in fig. 10, fig. 11 is an enlarged view of one support hole in a dotted frame B in fig. 10, followed by step S3, a support hole 107 is formed in the word line connection region 12 and the bottom select gate lead-out region 13, the support holes 107 include first support holes 108 extending in a first direction and second support holes 109 extending in a second direction and communicating with the first support holes 108, the first direction and the second direction being perpendicular to each other, wherein a top length X1 of the first support aperture along the first direction 108 is greater than a top length Y1 of the first support aperture 108 along the second direction, the top length Y2 of the second support hole 109 in the second direction is greater than the top length X2 of the second support hole 109 in the first direction. The support holes 107 may be "T" like or "cross" like or "L" like as shown in fig. 10. This embodiment is preferably "T" -like in shape.
It should be noted that parameters such as the number of stacked layers of the stacked structure 101, the number and distribution of the etching of the trench holes 104, the number and distribution of the etching of the support holes 107, and the like are set according to practical application requirements, and are not limited herein.
By arranging the support holes 107 between adjacent gate line spacing groove regions 117, and making the top length X1 of the first support hole 108 along the first direction greater than the top length Y1 of the first support hole 108 along the second direction, and the top length Y2 of the second support hole 109 along the second direction greater than the top length X2 of the second support hole 109 along the first direction, the open area of the support holes is effectively increased, the difficulty of etching high-aspect-ratio deep holes is reduced, and the conformality of the holes is improved; meanwhile, the supporting holes are arranged to be mutually vertical, so that the impact reflection effect of non-vertical etching ions on the mask and the hole wall in the etching process can be effectively reduced, and the Bow size of the supporting holes is relieved, so that the supporting holes cannot extrude a process window of a subsequent process; finally, the functional conductive hole region of the device can be disposed between the adjacent second support holes 109, so that the opening area of the support hole is effectively increased without sacrificing the functional conductive hole region.
As shown in fig. 10, by way of example, the top length X1 of the first support hole 108 in the first direction is more than twice the top length Y1 of the first support hole 108 in the second direction, and the top length Y2 of the second support hole 109 in the second direction is between one and two times the top length X2 of the second support hole 109 in the first direction.
As shown in fig. 11, a top length Y1 of the first support hole 108 in the second direction is identical to a top length X2 of the second support hole 109 in the first direction. In this embodiment, the top length X1 of the first supporting hole 108 along the first direction is between 730nm and 770nm, the top length Y1 of the first supporting hole 108 along the second direction is between 180nm and 220nm, the top length Y2 of the second supporting hole 109 along the second direction is between 300nm and 340nm, and the top length X2 of the second supporting hole 109 along the first direction is between 180nm and 220 nm. It should be noted that the distance X3 from the outside of the second support hole 109 to the outside of the first support hole 108 can be set differently according to the needs of the functional conductive hole region, and in this embodiment, the value of X3 is selected to be between 280nm and 320 nm.
As an example, a support hole 107 may be formed in the word line connection region 12 and the bottom select gate lead-out region 13 by using a photolithography process and an etching process. In addition, the support hole 107, or a conventional circular support hole, may be formed at the upper selection gate lead-out region 14 at the same time.
As shown in fig. 4 and 12, step S4 is finally performed to fill the supporting hole 107 with an insulating supporting material to form the supporting pillar 110. That is, the supporting pillars 110 are perpendicular to each other, and the supporting pillars have a better supporting effect than the circular supporting pillars.
For example, an insulating support material may be filled in the support holes 107 by using a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), an atomic layer deposition method (ALD), or the like.
As shown in fig. 13 and fig. 14, after forming the supporting pillars 110, the method further includes removing the sacrificial layer 103 of the stacked structure 101, forming a gap 111 between adjacent dielectric layers 102 (as shown in fig. 13), and filling a gate layer 112 in the gap 111 (as shown in fig. 14).
As shown in fig. 10 and 13, for example, the removing of the sacrificial layer 103 includes the steps of: forming a gate line spacer 113 in the gate line spacer region 117 of the stacked structure 101, and then removing the sacrificial layer 103 through the gate line spacer 113 by using a wet etching process. In addition, in one embodiment, the method further comprises the steps of: a material layer is filled in the gate line spacer groove 113. The gate line isolation trench 113 may divide a plurality of memory cells into memory blocks (blocks), and may lead a common source line layer to a circuit on the top, which may increase flexibility of circuit design and layout.
As shown in fig. 16, as an example, the first support hole 108 extending in the first direction may be disposed parallel to the gate line slit 113. To improve the removal of the sacrificial layer 103 and the subsequent deposition of the gate layer 112.
As shown in fig. 15 to 17, fig. 16 is a top view of a support pillar in a word line connection region and a bottom selection gate lead-out region in the stacked structure of the embodiment, fig. 15 is a cross-sectional view taken along line AA in fig. 16, fig. 17 is a top view of a support pillar in a word line connection region and a bottom selection gate lead-out region in a stacked structure of the prior art, and after forming the gate layer 112, the method further includes forming a via hole in the insulating layer 114 and filling a conductive layer in the via hole to form a word line conductive layer 115 and a bottom selection gate conductive layer 118, where the word line conductive layer 115 is connected to the gate layer 112 in the ladder structure to realize the lead-out of the gate layer 112 (as shown in fig. 15).
As shown in fig. 16 and 17, to facilitate understanding, the functional pillar formed in the functional conductive hole region is referred to as a conductive layer 119, and as shown by a dashed box D in fig. 16 and a dashed box C in fig. 17, the support hole 107 of the present embodiment may be formed by connecting the existing circular support hole shapes adjacent to each other along the first direction and the second direction, so as to form a support hole similar to a "T" shape of the present embodiment, thereby effectively increasing the opening area of the support hole without affecting the process window of the conductive layer 119, and simultaneously not affecting the removal of the sacrificial layer and the deposition of the gate layer.
In an actual application process, the preparation method of the three-dimensional NAND memory further includes other process steps, and the process steps can be realized by adopting a conventional process in the prior art, and are not described herein again.
Example two
This embodiment provides a three-dimensional NAND memory, which can be fabricated by the fabrication method of the first embodiment, but is not limited to the fabrication method of the first embodiment, as long as the memory structure can be formed. Please refer to embodiment one, and details are not repeated herein.
As shown in fig. 11, 15, and 16, the structure includes:
a substrate 100;
a stack structure formed on the substrate 100, the stack structure including a core storage region 11 and a word line connection region 12, the core storage region 11 having a channel hole 104, the channel hole 104 having a memory film 105 and a channel layer 106 formed therein, the word line connection region 12 having a support hole 107 penetrating the word line connection region 12, the support hole 107 being filled with a support pillar 110;
the bottom select gate lead-out region 13 is located outside the word line connection region 12, the bottom select gate lead-out region 13 has the support hole 107, and the support pillar 110 is filled in the support hole 107;
wherein the support holes 107 include a first support hole 108 extending along a first direction and a second support hole 109 extending along a second direction and communicating with the first support hole 108, the first direction and the second direction being perpendicular to each other, wherein a top length X1 of the first support hole 108 along the first direction is greater than a top length Y1 of the first support hole 108 along the second direction, and a top length Y2 of the second support hole 109 along the second direction is greater than a top length X2 of the second support hole 109 along the first direction.
As an example, the top length X1 of the first support hole 108 in the first direction is more than two times the top length Y1 of the first support hole 108 in the second direction, and the top length Y2 of the second support hole 109 in the second direction is between one and two times the top length X2 of the second support hole 109 in the first direction.
As an example, a top length Y1 of the first support hole 108 in the second direction coincides with a top length X2 of the second support hole 109 in the first direction. In this embodiment, the top length X1 of the first supporting hole 108 along the first direction is between 730nm and 770nm, the top length Y1 of the first supporting hole 108 along the second direction is between 180nm and 220nm, the top length Y2 of the second supporting hole 109 along the second direction is between 300nm and 340nm, and the top length X2 of the second supporting hole 109 along the first direction is between 180nm and 220 nm.
As shown in fig. 15, the stacked structure includes alternately stacked gate electrode layers 112 and dielectric layers 102, and gate line spacer grooves 113 are further formed in the stacked structure.
As shown in fig. 16, the first support hole 108 extending in the first direction and the gate line slit 113 are parallel to each other, as an example.
As shown in fig. 15, as an example, the word line connection region 12 includes a ladder structure, the ladder structure and the bottom selection gate lead-out region 13 are covered with an insulating layer 114, a through hole is formed in the insulating layer 114, a conductive layer is filled in the through hole, the conductive layer of the word line connection region 12 forms a word line conductor layer 115, the conductive layer of the bottom selection gate lead-out region 13 forms a bottom selection gate conductive layer 118, and the word line conductive layer 115 is connected to the gate layer 112 in the ladder structure.
As described above, the three-dimensional NAND memory and the method for manufacturing the same of the present invention have the following advantageous effects:
by arranging the supporting holes between the adjacent grid line spacing groove regions, arranging that the top length X1 of the first supporting hole along the first direction is greater than the top length Y1 of the first supporting hole along the second direction, and arranging that the top length Y2 of the second supporting hole along the second direction is greater than the top length X2 of the second supporting hole along the first direction by one time to two times, the opening area of the supporting holes is effectively increased, the difficulty in etching the deep holes with high depth-to-width ratio is reduced, and the shape-preserving property of the holes is improved; meanwhile, the supporting holes are arranged to be mutually vertical, so that the impact reflection effect of non-vertical etching ions on the mask and the hole wall in the etching process can be effectively reduced, and the Bow size of the supporting holes is relieved, so that the supporting holes cannot extrude a process window of a subsequent process; and finally, a functional conductive hole area of the device can be arranged between the adjacent second support holes, so that the opening area of the support holes is effectively increased on the premise of not sacrificing the functional conductive hole area.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (16)
1. A preparation method of a three-dimensional NAND memory is characterized by comprising the following steps:
providing a substrate, and forming a laminated structure formed by alternately stacking dielectric layers and sacrificial layers on the substrate, wherein the laminated structure comprises a core storage area and a word line connecting area;
forming a channel hole in the core memory region, and forming a memory film and a channel layer in the channel hole;
forming support holes in the word line connection regions, wherein the support holes include first support holes extending in a first direction and second support holes extending in a second direction and communicating with the first support holes, the first direction and the second direction are perpendicular to each other, a top length of the first support holes in the first direction is greater than a top length of the first support holes in the second direction, and a top length of the second support holes in the second direction is greater than a top length of the second support holes in the first direction;
and filling an insulating support material in the support hole to form a support column.
2. The method of claim 1, wherein: the laminated structure also comprises a bottom selection gate lead-out area; when the support hole is formed in the word line connection region, the support hole is formed in the bottom selection gate lead-out region.
3. The method of claim 1, wherein: the length of the top of the first support hole in the first direction is more than twice the length of the top of the first support hole in the second direction, and the length of the top of the second support hole in the second direction is between one and two times the length of the top of the second support hole in the first direction.
4. The method of claim 1, wherein: the top length of the first support hole in the second direction is identical to the top length of the second support hole in the first direction.
5. The method of claim 4, wherein: the length of the top of the first supporting hole along the first direction is 730 nm-770 nm, the length of the top of the first supporting hole along the second direction is 180 nm-220 nm, the length of the top of the second supporting hole along the second direction is 300 nm-340 nm, and the length of the top of the second supporting hole along the first direction is 180 nm-220 nm.
6. The method of manufacturing according to claim 1, further comprising:
removing the sacrificial layer of the laminated structure to form a gap between the adjacent dielectric layers;
and filling the gap with a gate layer.
7. The production method according to claim 6, wherein the removing of the sacrifice layer includes the steps of:
forming a gate line isolation groove in the laminated structure;
and removing the sacrificial layer through the grid line separation groove by adopting a wet etching process.
8. The method of claim 7, wherein: the first supporting holes extending along the first direction are parallel to the gate line separation grooves.
9. A three-dimensional NAND memory, comprising:
a substrate;
the stacked structure is formed on the substrate and comprises a core storage area and a word line connection area, wherein the core storage area is provided with a channel hole, a memory film and a channel layer are formed in the channel hole, the word line connection area is provided with a support hole penetrating through the word line connection area, and a support pillar is filled in the support hole;
the supporting holes comprise first supporting holes extending along a first direction and second supporting holes extending along a second direction and communicated with the first supporting holes, the first direction and the second direction are perpendicular to each other, the length of the tops of the first supporting holes along the first direction is larger than that of the tops of the first supporting holes along the second direction, and the length of the tops of the second supporting holes along the second direction is larger than that of the tops of the second supporting holes along the first direction.
10. The memory of claim 9, further comprising: and the bottom selection gate lead-out area is positioned outside the word line connecting area and is provided with the support holes, and the support columns are filled in the support holes.
11. The memory of claim 10, wherein: the word line connecting area comprises a stepped structure, insulating layers are covered on the stepped structure and the bottom selective gate leading-out area, a through hole is formed in each insulating layer, a conducting layer is filled in each through hole, the conducting layer of the word line connecting area forms a word line conducting layer, the conducting layer of the bottom selective gate leading-out area forms a bottom selective gate conducting layer, and the word line conducting layer is connected with the grid layer in the stepped structure.
12. The memory of claim 9, wherein: the length of the top of the first support hole in the first direction is more than twice the length of the top of the first support hole in the second direction, and the length of the top of the second support hole in the second direction is between one and two times the length of the top of the second support hole in the first direction.
13. The memory of claim 9, wherein: the top length of the first support hole in the second direction is identical to the top length of the second support hole in the first direction.
14. The memory of claim 13, wherein: the length of the top of the first supporting hole along the first direction is 730 nm-770 nm, the length of the top of the first supporting hole along the second direction is 180 nm-220 nm, the length of the top of the second supporting hole along the second direction is 300 nm-340 nm, and the length of the top of the second supporting hole along the first direction is 180 nm-220 nm.
15. The memory of claim 9, wherein: the stacked structure comprises gate layers and dielectric layers which are stacked alternately, and gate line separation grooves are formed in the stacked structure.
16. The memory of claim 15, wherein: the first supporting holes extending along the first direction are parallel to the gate line separation grooves.
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