CN110828525A

CN110828525A - Array substrate, preparation method thereof, display panel and display device

Info

Publication number: CN110828525A
Application number: CN201911139583.5A
Authority: CN
Inventors: 韩影; 王玲; 林奕呈; 徐攀; 靳倩
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-11-20
Filing date: 2019-11-20
Publication date: 2020-02-21
Anticipated expiration: 2039-11-20
Also published as: CN110828525B

Abstract

The disclosure provides an array substrate, a preparation method of the array substrate, a display panel and a display device, and belongs to the technical field of display. The array substrate disclosed by the disclosure has the advantages that the thickness of the pixel definition layer is increased or the pixel electrode is arranged at the bottom of the groove of the planarization layer, so that the height difference between the dam layer and the pixel electrode can be increased, the quantum dot layer of the array substrate can be thicker, and the conversion efficiency of the quantum dot layer can be improved.

Description

Array substrate, preparation method thereof, display panel and display device

Technical Field

The disclosure relates to the technical field of display, and in particular to an array substrate, a preparation method thereof, a display panel and a display device.

Background

QD-OLED (quantum dot-organic electroluminescent device) has the advantages of high resolution, high color gamut, no viewing angle dependence, capability of being applied to large-sized medium-sized high-color-gamut high-resolution products and the like.

When preparing the quantum dot layer, it is necessary to prepare a Bank layer (Bank) for blocking the flow of the quantum dot ink, and then inject the quantum dot ink into the receiving hole formed in the Bank layer. However, due to process limitations, the thickness of the Bank layer (Bank) is relatively thin, which results in failure to prepare a quantum dot layer having a large thickness, limiting the performance of the OD-OLED.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to an array substrate, a method for manufacturing the same, a display panel and a display device, so as to increase the thickness of a quantum dot layer.

In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:

according to a first aspect of the present disclosure, there is provided an array substrate including:

a substrate base plate;

the pixel electrode layer is arranged on one side of the substrate base plate; the pixel electrode layer comprises a plurality of pixel electrodes arranged in an array, and any one pixel electrode is provided with at least one light-emitting region;

the pixel defining layer is arranged on one side of the pixel electrode layer, which is far away from the substrate base plate, and exposes each light-emitting region; the thickness of the pixel defining layer is greater than 1.5 microns;

the organic light-emitting layer is arranged on one side of the pixel electrode layer, which is far away from the substrate, and covers the light-emitting areas of the pixel electrodes;

the common electrode layer is arranged on one side of the organic light-emitting layer, which is far away from the substrate and covers the organic light-emitting layer;

the dam layer is arranged on one side of the common electrode layer, which is far away from the substrate base plate; an orthographic projection of the dam layer on the substrate base plate is positioned in an orthographic projection of the pixel defining layer on the substrate base plate;

a quantum dot layer covering the common electrode layer at least partially exposed by the bank layer.

In an exemplary embodiment of the present disclosure, the pixel defining layer has a thickness greater than 3.5 micrometers.

In an exemplary embodiment of the present disclosure, the thickness of the dam layer is not greater than 6 micrometers.

In an exemplary embodiment of the present disclosure, the quantum dot layer has a thickness greater than 8 microns.

In an exemplary embodiment of the present disclosure, a distance between any point in an orthogonal projection of any one of the light emitting regions on the base substrate and any point in an orthogonal projection of the bank layer on the base substrate is not less than 3 μm.

In an exemplary embodiment of the present disclosure, the pixel defining layer includes:

the first pixel defining layer is arranged on one side, far away from the substrate, of the pixel electrode layer and exposes each light-emitting region;

the second pixel defining layer is arranged on the surface, away from the substrate base plate, of the first pixel defining layer and exposes at least part of the first pixel defining layer;

an orthogonal projection of the bank layer on the base substrate is located within an orthogonal projection of the second pixel defining layer on the base substrate.

According to a second aspect of the present disclosure, there is provided a method for manufacturing an array substrate, including:

providing a substrate base plate;

forming a pixel electrode layer on one side of the substrate, wherein the pixel electrode layer comprises a plurality of pixel electrodes arranged in an array, and each pixel electrode is provided with at least one light-emitting region;

forming a pixel defining layer on one side of the pixel electrode layer far away from the substrate, wherein the pixel defining layer exposes each light-emitting region and the thickness of the pixel defining layer is more than 1.5 microns;

forming an organic light-emitting layer on one side of the pixel electrode layer far away from the substrate, wherein the organic light-emitting layer covers the light-emitting region of each pixel electrode;

forming a common electrode layer on one side of the organic light-emitting layer far away from the substrate, wherein the common electrode layer covers the organic light-emitting layer;

forming a dam layer on one side of the common electrode layer far away from the substrate base plate, wherein the orthographic projection of the dam layer on the substrate base plate is positioned in the orthographic projection of the pixel defining layer on the substrate base plate;

forming a quantum dot layer covering the common electrode layer at least partially exposed by the bank layer.

According to a third aspect of the present disclosure, there is provided an array substrate including:

a substrate base plate;

a planarization layer disposed on one side of the substrate base plate; the planarization layer is provided with a plurality of grooves distributed in an array manner;

the pixel electrode layer is arranged on one side, far away from the substrate, of the planarization layer; the pixel electrode layer comprises a plurality of pixel electrodes which are arranged in one-to-one correspondence to the grooves, and any one pixel electrode is provided with a light emitting area; the orthographic projection of a light-emitting area of any one pixel electrode on the substrate base plate is positioned in the orthographic projection of the groove bottom of the corresponding groove on the substrate base plate;

the pixel defining layer is arranged on one side of the pixel electrode layer, which is far away from the substrate base plate, and exposes each light-emitting region;

the dam layer is arranged on one side of the common electrode layer, which is far away from the substrate base plate; the orthographic projection of the dam layer on the substrate base plate is completely not coincident with the orthographic projection of each groove on the substrate base plate;

In an exemplary embodiment of the present disclosure, a dimension of the groove in a direction perpendicular to a plane of the substrate base plate is greater than 2 micrometers.

According to a fourth aspect of the present disclosure, there is provided a method for manufacturing an array substrate, including:

providing a substrate base plate;

forming a planarization layer on one side of the substrate, wherein the planarization layer is provided with a plurality of grooves distributed in an array manner;

forming a pixel electrode layer on one side of the planarization layer, which is far away from the substrate, wherein the pixel electrode layer comprises a plurality of pixel electrodes which are arranged in one-to-one correspondence with the grooves, and any one pixel electrode is provided with a light emitting region; the orthographic projection of a light-emitting area of any one pixel electrode on the substrate base plate is positioned in the orthographic projection of the groove bottom of the corresponding groove on the substrate base plate;

forming a pixel defining layer on a side of the pixel electrode layer away from the substrate, the pixel defining layer exposing each of the light emitting regions;

forming a dam layer on one side of the common electrode layer, which is far away from the substrate base plate, wherein the orthographic projection of the dam layer on the substrate base plate is completely not overlapped with the orthographic projection of each groove on the substrate base plate;

According to a fifth aspect of the present disclosure, a display panel is provided, which includes the array substrate.

According to a sixth aspect of the present disclosure, there is provided a display device including the display panel described above.

The array substrate, the preparation method thereof, the display panel and the display device provided by the disclosure can improve the depth of the accommodating groove on the premise of not remarkably increasing the thickness of the dam layer, so that the thickness of the quantum dot layer can be improved, the conversion efficiency of the quantum dot layer is improved, and the performance of the array substrate is improved.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional structural diagram of a pixel electrode and a pixel defining layer according to an embodiment of the disclosure.

Fig. 3 is a schematic cross-sectional structure diagram of a pixel slot according to an embodiment of the present disclosure.

Fig. 4 is a schematic cross-sectional structure view of an accommodating groove according to an embodiment of the disclosure.

Fig. 5 is a schematic plan view of the light-emitting region of the pixel electrode, the pixel defining layer, and the bank layer in cooperation with each other according to one embodiment of the present disclosure.

Fig. 6 is a schematic flow chart illustrating a process of manufacturing an array substrate according to an embodiment of the present disclosure.

Fig. 7 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 8 is a schematic cross-sectional structural view of a planarization layer according to an embodiment of the present disclosure.

Fig. 9 is a schematic cross-sectional structural view of a pixel electrode and a pixel defining layer according to an embodiment of the present disclosure.

Fig. 10 is a schematic cross-sectional structure diagram of a pixel slot according to an embodiment of the present disclosure.

Fig. 11 is a schematic cross-sectional structure view of an accommodating groove according to an embodiment of the disclosure.

Fig. 12 is a schematic top view showing the arrangement of the planarization layer, the light-emitting region of the pixel electrode, and the bank layer in cooperation with each other according to one embodiment of the present disclosure.

Fig. 13 is a schematic flow chart illustrating a process of manufacturing an array substrate according to an embodiment of the present disclosure.

The reference numerals of the main elements in the figures are explained as follows:

100. a substrate base plate; 210. a pixel electrode; 220. a light emitting region; 221. a light emitting region of a pixel electrode of the blue sub-pixel; 222. a light emitting region of a pixel electrode of the red sub-pixel; 223. a light emitting region of the pixel electrode of the green sub-pixel; 300. a pixel defining layer; 310. an exposure hole; 301. a first pixel defining layer; 302. a second pixel defining layer; 400. an organic light emitting layer; 500. a common electrode layer; 510. a pixel groove; 600. a dam layer; 610. a housing hole; 710. a containing groove; 701. a quantum dot unit; 810. a shielding layer; 820. a buffer layer; 830. an oxide semiconductor layer; 840. a gate insulating layer; 850. a gate layer; 860. an interlayer dielectric layer; 870. a source drain metal layer; 880. a passivation layer; 890. a planarization layer; 891. and (4) a groove.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.

In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the primary technical ideas of the disclosure.

When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.

In the related art, the conversion efficiency of a quantum dot layer (QD) has a correlation with the thickness of the quantum dot layer. Through a large number of experiments and tests, the applicant finds that increasing the thickness of the quantum dot layer is helpful for improving the conversion efficiency of the quantum dot layer, and further improving the performance of the QD-OLED device.

The quantum dot layer may be prepared by ink jet printing techniques. When preparing the quantum dot layer, it is necessary to prepare a Bank layer (Bank) in which a receiving hole exposing an OLED (organic electroluminescent device) is formed; and then quantum dot ink containing quantum dots is injected into the containing hole, and the dam layer is used for blocking the quantum dot ink so as to avoid color crosstalk between pixels caused by the overflow of the quantum dot ink. However, due to the manufacturing process and materials, when the thickness of the dam layer is large, not only the deviation (Bias) of the patterning (usually, etching process) is large, but also other film layers are adversely affected during the patterning. This makes it difficult to accurately prepare a bank layer having a large thickness without affecting other film layers, and limits the thickness of the quantum dot layer, thereby limiting the conversion efficiency of the quantum dot layer.

The first embodiment,

In the disclosed embodiment, there is provided an array substrate, as shown in fig. 1, which includes a substrate 100, a pixel electrode layer, a pixel defining layer 300, an organic light emitting layer 400, a common electrode layer 500, a bank layer 600, and a quantum dot layer, wherein,

the pixel electrode layer is arranged on one side of the substrate 100, the pixel electrode layer comprises a plurality of pixel electrodes 210 arranged in an array, and any one pixel electrode 210 is provided with at least one light-emitting region 220; the pixel defining layer 300 is disposed on a side of the pixel electrode layer away from the substrate 100, and as shown in fig. 2, the pixel defining layer 300 exposes each light emitting region 220, and the thickness of the pixel defining layer 300 is greater than 1.5 μm; the organic light emitting layer 400 is disposed on a side of the pixel electrode layer away from the substrate 100, and the organic light emitting layer 400 covers the light emitting regions 220 of the pixel electrodes 210; the common electrode layer 500 is disposed on a side of the organic light emitting layer 400 away from the substrate 100, and the common electrode layer 500 covers the organic light emitting layer 400; the bank layer 600 is disposed on a side of the common electrode layer 500 away from the substrate 100; the orthographic projection of the bank layer 600 on the base substrate 100 is located within the orthographic projection of the pixel defining layer 300 on the base substrate 100; the quantum dot layer covers the common electrode layer 500 at least partially exposed by the bank layer 600.

In the array substrate provided by the embodiment of the present disclosure, as shown in fig. 4, the dam layer 600 is formed with a receiving hole 610 exposing the common electrode layer 500, and the receiving hole 610 and the exposed common electrode layer 500 together form a receiving groove 710 for receiving quantum dot ink. After the quantum dot ink contained in the containing groove 710 is cured, a quantum dot layer of the array substrate can be formed. The larger the depth of the accommodating groove 710 is, the larger the depth of the quantum dot ink that can be accommodated therein is, the larger the thickness of the formed quantum dot layer is, and the higher the conversion efficiency of the quantum dot layer is.

In the prior art, the thickness of the pixel defining layer 300 is generally about 1 μm. In the array substrate provided by the embodiment of the present disclosure, the thickness of the pixel defining layer 300 is greater than 1.5 μm, and compared with the thickness increase of the pixel defining layer 300 in the prior art, the distance between the pixel electrode 210 and the surface of the dam layer 600 far away from the substrate 100 can be increased, so that the depth of the accommodating groove 710 is increased, the thickness of the quantum dot layer is increased, and the conversion efficiency of the quantum dot layer is improved.

Each component of the array substrate provided by the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings:

the base substrate 100 may be an inorganic base substrate 100 or an organic base substrate 100. For example, in one embodiment of the present disclosure, the material of the substrate 100 may be a glass material such as soda-lime glass (soda-lime glass), quartz glass, or sapphire glass, or may be a metal material such as stainless steel, aluminum, or nickel. In another embodiment of the present disclosure, the material of the substrate 100 may be polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate 100 may also be a flexible substrate 100, for example, the material of the substrate 100 may be Polyimide (PI).

As shown in fig. 1, the pixel electrode layer may include a plurality of pixel electrodes 210 arranged in an array, and any one of the pixel electrodes 210 is provided with at least one light emitting region 220. Alternatively, one pixel electrode 210 is provided with one light emitting region 220. Alternatively, the light emitting region 220 of the pixel electrode 210 may be rectangular, diamond-shaped, rectangular with a notch, or other feasible shapes, which is not limited by the present disclosure.

Alternatively, the shape and size of the light emitting region 220 of each pixel electrode 210 may be the same or different. For example, in one embodiment of the present disclosure, as shown in fig. 5, the light emitting region 222 of the pixel electrode of the red sub-pixel and the light emitting region 223 of the pixel electrode of the green sub-pixel may be rectangular with a notch; the light emitting region 221 of the pixel electrode of the blue sub-pixel may have a rectangular shape and an area smaller than the light emitting region 222 of the pixel electrode of the red sub-pixel and the light emitting region 223 of the pixel electrode of the green sub-pixel.

Optionally, in an embodiment of the present disclosure, as shown in fig. 5, the first direction and the second direction are perpendicular, and all the pixel electrodes 210 located on the same straight line along the first direction are the same type of pixel electrode 210, for example, the pixel electrodes 210 that are all red sub-pixels, or the pixel electrodes 210 that are all green sub-pixels, or the pixel electrodes 210 that are all blue sub-pixels. All the pixel electrodes 210 located on the same line along the second direction are different types of pixel electrodes 210 that are periodically arranged, and may be periodically arranged along the second direction as follows, for example: a pixel electrode 210 of a red sub-pixel, a pixel electrode 210 of a blue sub-pixel, a pixel electrode 210 of a green sub-pixel, and a pixel electrode 210 of a blue sub-pixel.

In one embodiment, the pixel electrode may serve as an anode of the light emitting device. The pixel electrode 210 may select a material having a large work function so that holes can be smoothly injected into the organic light emitting layer 400. The pixel electrode 210 may be one or more anode materials, wherein the anode material may be selected from metals, metal oxides, conductive polymers, or other anode materials. Wherein the metal includes, but is not limited to, vanadium, chromium, copper, zinc, gold, and alloys of any of the foregoing; metal oxides include, but are not limited to, zinc oxide, Indium Tin Oxide (ITO), and Indium Zinc Oxide (IZO); conductive polymers include, but are not limited to, poly (3-methylthiophene), poly [3,4- (ethylene-1, 2-dioxy) thiophene ] (PEDOT), polypyrrole, polyaniline. For example, the material of the pixel electrode 210 may be ITO.

The pixel defining layer 300 exposes each light emitting region 220 so that the light emitting region 220 of each pixel can be in direct surface connection with the organic light emitting layer 400. Alternatively, portions of the respective pixel electrodes 210 other than the light emitting regions 220 may be covered by the pixel defining layer 300, so that the pixel defining layer 300 may define the light emitting regions of the organic light emitting layer 400. In other words, as shown in fig. 2, the pixel defining layer 300 forms a plurality of exposure holes 310 corresponding to the light emitting regions 220 one to one, and an orthogonal projection of any one of the exposure holes 310 on the substrate base 100 near the edge of the substrate base 100 completely coincides with an orthogonal projection of the corresponding light emitting region 220 on the substrate base 100.

In the embodiment of the present disclosure, the thickness of the pixel defining layer 300 is increased compared to the prior art, which may increase the depth of the receiving groove 710. The required depth of the receiving groove 710 may be determined according to the required thickness of the quantum dot layer, and thus the required thickness of the pixel defining layer 300 may be determined. The pixel defining layer 300 is easier to manufacture with a thicker thickness and has less adverse effects on other film layers during the manufacturing process, compared to the bank layer 600. Thus, the depth of the receiving groove 710 can be increased by increasing the thickness of the pixel defining layer 300 without increasing the thickness of the bank layer 600. This has not only avoided adopting more complicated technology to prepare thicker dyke layer 600, can improve the accurate degree of dyke layer 600 pattern moreover, and reduces the adverse effect of dyke layer 600 preparation process to other retes, and then reaches the effect that reduces array substrate's preparation cost, improves array substrate's performance.

In one embodiment of the present disclosure, the thickness of the pixel defining layer 300 is greater than 3.5 microns. Thus, the pixel defining layer 300 is at least 2 microns thicker than the prior art, and the depth of the accommodating groove 710 can be increased by at least 2 microns under the condition of maintaining the thickness of the dam layer 600 unchanged, or the dam layer 600 can be 2 microns thinner under the condition of maintaining the depth of the accommodating groove 710 unchanged, or the depth of the accommodating groove 710 can be increased and the dam layer 600 can be thinned at the same time.

Of course, the pixel defining layer 300 may have other thicknesses, such as 3 microns, 3.5 microns, etc., according to the required depth of the receiving groove 710, which is not limited in this disclosure.

The pixel defining layer 300 may also be partially or entirely of a stepped structure so as to reduce the slope between the surface of the pixel defining layer 300 away from the substrate base plate 100 and the light emitting region 220 of the pixel electrode 210. For example, as shown in fig. 1, fig. 2 and fig. 5, the pixel defining layer 300 includes a first pixel defining layer 301 and a second pixel defining layer 302, wherein the first pixel defining layer 301 is disposed on a side of the pixel electrode layer away from the substrate 100 and exposes each light emitting region 220; the second pixel defining layer 302 is disposed on the surface of the first pixel defining layer 301 away from the substrate 100, and exposes at least a portion of the first pixel defining layer 301; an orthogonal projection of the bank layer 600 on the base substrate 100 is located within an orthogonal projection of the second pixel defining layer 302 on the base substrate 100. In one embodiment of the present disclosure, the thicknesses of the first pixel defining layer 301 and the second pixel defining layer 302 may be the same. In another embodiment of the present disclosure, the thickness of the first pixel defining layer 301 may be 1 to 1.5 μm, and the rest may be the second pixel defining layer 302.

Further, when the pixel defining layer 300 includes the first pixel defining layer 301 and the second pixel defining layer 302, any one of the exposing holes 310 includes a first pixel defining layer 301 portion and a second pixel defining layer 302 portion, wherein the first pixel defining layer 301 portion of the exposing hole 310 is close to an orthographic projection of the edge of the substrate base plate 100 on the substrate base plate 100, and coincides with an edge of the orthographic projection of the corresponding light emitting region 220 on the substrate base plate 100. The second pixel defining layer 302 partially exposing the hole 310 is orthographically projected on the substrate base plate 100, and the first pixel defining layer 301 partially covering the exposing hole 310 is orthographically projected on the substrate base plate 100.

Alternatively, the first pixel defining layer 301 and the second pixel defining layer 302 may be formed by a gray scale mask (a Halftone process). By way of example, the pixel defining layer 300 may be prepared by the following process:

step S110, forming a pixel defining material layer on a side of the pixel electrode layer away from the substrate 100;

in step S120, the pixel defining material layer is exposed by a Halftone process. Wherein the light-emitting region 220 covering the pixel electrode 210 has the largest exposure amount, for example, a full exposure is adopted; the exposure of the position corresponding to the second pixel defining layer 302 is minimum, for example, no exposure is performed at all; the portion of the first pixel defining layer 301 not covered by the second pixel defining layer 302, i.e., the stepped portion, is partially exposed, for example, by half exposure.

In step S130, the pixel definition layer 300 is patterned by development.

The organic light emitting layer 400 is used to receive carriers provided by the pixel electrode 210 and the common electrode layer 500, and electroluminescence is realized by recombination of the carriers.

Alternatively, the organic light emitting layer 400 may be prepared by an evaporation method, such that the thicknesses of the organic light emitting layers 400 at different positions are consistent, so that the organic light emitting layer 400 does not have a planarization effect, and the organic light emitting layer 400 is prevented from reducing the depth of the accommodating groove 710.

Alternatively, the organic light emitting layer 400 may be a unitary structure, i.e., the organic light emitting layer 400 covers all of the exposed pixel electrodes 210 and the entire pixel defining layer 300 at the same time. Thus, alignment is not required in the preparation of the organic light emitting layer 400, which can save a mask plate and reduce the preparation cost.

Alternatively, the organic light emitting layer 400 may emit blue light when performing electroluminescence. The blue light can be directly emitted from the array substrate, and can also be converted into other colors through the quantum dot layer to be emitted.

As shown in fig. 1, the common electrode layer 500 is disposed on a surface of the organic light emitting layer 400 away from the substrate 100, and may be made of a conductive transparent material, such as a magnesium-silver alloy. Alternatively, the common electrode layer 500 is a unitary structure, i.e., the common electrode layer 500 covers the entire organic light emitting layer 400 at the same time.

Optionally, the common electrode layer 500 may be formed by a sputtering or evaporation method, so that the thicknesses of the common electrode layers 500 at different positions are consistent, the common electrode layer 500 does not have a planarization effect, and the common electrode layer 500 is prevented from reducing the depth of the accommodating groove 710.

As shown in fig. 2 and 3, since the pixel defining layer 300 has a structure with the exposure holes 310 distributed in an array, the surface of the common electrode layer 500 away from the substrate base plate 100 is not a planar structure, but has a structure with the pixel grooves 510 distributed in an array. Wherein, each pixel groove 510 is disposed opposite to each exposure hole 310, that is, each pixel groove 510 is disposed opposite to each light-emitting region 220 of each pixel electrode 210; in other words, an orthogonal projection of the light emitting region 220 of any one of the pixel electrodes 210 on the substrate 100 at least partially overlaps an orthogonal projection of the corresponding pixel groove 510 on the substrate 100.

As shown in fig. 4, the bank layer 600 is formed on a side of the common electrode layer 500 away from the substrate 100, and may be formed with a plurality of accommodating holes 610 distributed in an array, wherein the plurality of accommodating holes 610 are disposed in one-to-one correspondence with the plurality of pixel slots 510. In other words, the orthographic projection of any pixel slot 510 on the substrate base plate 100 is located within the orthographic projection of the corresponding accommodating hole 610 on the substrate base plate 100.

Optionally, in order to avoid the difficulty in manufacturing, the reduction in pattern precision, and the adverse effect on other film layers caused by the excessively thick dam layer 600, the thickness of the dam layer 600 is not greater than 6 μm.

Alternatively, in order to reduce color crosstalk between pixels caused by light of different colors passing through the dam layer 600, the dam layer 600 may be made of an opaque material, for example, a black material.

Alternatively, in order to reduce the blocking of the light emitted from the quantum dot layer by the bank layer 600, as shown in fig. 5, the distance between any one point in the orthographic projection of any one of the light emitting regions 220 on the substrate 100 and any one point in the orthographic projection of the bank layer 600 on the substrate 100 is not less than 3 μm. Thus, the orthographic projection of the edge of the light-emitting region 220 on the substrate base plate 100 is located in the orthographic projection of the edge of the accommodating hole 610 on the substrate base plate 100, and the gap between the two is at least 3 micrometers.

Further, when the pixel defining layer 300 includes the first pixel defining layer 301 and the second pixel defining layer 302, the distance between the orthographic projection of any point on the edge of the second pixel defining layer 302 of any exposing hole 310, which is partially far from the substrate base plate 100, on the substrate base plate 100 and the orthographic projection of any point on the edge of the corresponding accommodating hole 610, which is close to the substrate base plate 100, on the substrate base plate 100 is not less than 3 micrometers. In other words, in the orthographic projection of the substrate 100, there is at least a gap of 3 μm between the inner edge of the accommodating hole 610 and the outer edge of the corresponding exposing hole 310.

As shown in fig. 4, the pixel slots 510 and the corresponding receiving holes 610 together form a receiving slot 710 for receiving quantum dot ink. After the quantum dot ink is injected into the receiving groove 710 through inkjet printing or other methods, the quantum dot units 701 can be formed by curing, and each quantum dot unit 701 constitutes a quantum dot layer of the array substrate.

The quantum dot units 701 are used for converting light emitted from the organic light emitting layer 400 into light of other colors, and the quantum dot layer may include one type of quantum dot unit 701 or may include a plurality of different types of quantum dot units 701. For example, the quantum dot layer may include two types of quantum dot units 701, a first type of quantum dot unit 701 may convert blue light into red light, and a second type of quantum dot unit 701 may convert blue light into green light.

Thus, the array substrate is formed with sub-pixels distributed in an array. The first type sub-pixels may be included in the sub-pixels of the array substrate, and the second type sub-pixels may be included or excluded. The first-type sub-pixel may include a pixel electrode 210, an organic light emitting layer 400 portion disposed on a surface of the light emitting region 220 of the pixel electrode 210, a common electrode layer 500 portion facing the light emitting region 220 of the pixel electrode 210, and a quantum dot unit 701 in the accommodating groove 710 corresponding to the light emitting region 220 of the pixel electrode 210. The second type sub-pixel may include a pixel electrode 210, an organic light emitting layer 400 portion disposed on the surface of the light emitting region 220 of the pixel electrode 210, and a common electrode layer 500 portion facing the light emitting region 220 of the pixel electrode 210, wherein the quantum dot unit 701 is not disposed in the accommodating groove 710 corresponding to the light emitting region 220 of the pixel electrode 210.

Alternatively, the quantum dot layer may have a thickness greater than 8 μm in order to improve the light conversion efficiency of the quantum dot layer. Further, the quantum dot layer may have a thickness greater than 10 microns.

In the embodiments of the present disclosure, the thickness refers to a dimension of the film layer in a direction perpendicular to a plane of the array substrate. For example, the thickness of the quantum dot layer refers to the dimension of the quantum dot layer in the direction perpendicular to the plane of the array substrate.

Optionally, the array substrate may further include a driving circuit layer to drive each sub-pixel, and particularly, to provide a driving current to each pixel electrode 210. In one embodiment of the present disclosure, a driving circuit layer may be disposed between the substrate 100 and the pixel electrode layer.

The driving circuit layer may include a pixel driving circuit for driving the respective sub-pixels, and any one of the pixel driving circuits may include a thin film transistor and a capacitor. Alternatively, the thin film transistor in the driving circuit layer may be an oxide transistor.

Hereinafter, a specific implementation of the array substrate is exemplarily provided in order to further explain and explain the structure, principle and effect of the array substrate of the present disclosure.

In the present exemplary embodiment, as shown in fig. 1, the array substrate includes:

a substrate 100, the substrate 100 being a glass substrate;

a shield layer (shield)810 provided on one side of the base substrate 100;

the buffer layer 820 is arranged on one side of the shielding layer 810 far away from the substrate base plate 100;

an oxide semiconductor layer 830 provided on a side of the buffer layer 820 away from the substrate 100; wherein, the orthographic projection of the oxide semiconductor layer 830 on the substrate 100 is at least partially located in the orthographic projection of the shielding layer 810 on the substrate 100; the oxide semiconductor layer 830 may be formed with an active layer of a thin film transistor.

A gate insulating layer 840 provided on a side of the oxide semiconductor layer 830 away from the base substrate 100 and covering a portion of the oxide semiconductor layer 830;

a gate layer 850 disposed on a side of the gate insulating layer 840 away from the substrate 100; an orthogonal projection of the gate layer 850 on the substrate base plate 100 overlaps with an orthogonal projection of the oxide semiconductor layer 830 on the substrate base plate 100, and the gate layer 850 is isolated from the oxide semiconductor layer 830 by a gate insulating layer 840. In this manner, the gate layer 850 can be formed with a gate of a thin film transistor.

An interlayer dielectric layer 860 arranged on one side of the gate layer 850 far away from the substrate 100;

and the source-drain metal layer 870 is disposed on a side of the interlayer dielectric layer 860 away from the substrate 100, and is electrically connected to the oxide semiconductor layer 830 through a via hole. In this manner, the source-drain metal layer 870 is formed with a source and a drain of the thin film transistor.

A passivation layer 880 disposed on a side of the source-drain metal layer 870 away from the substrate 100;

and a planarization layer 890 disposed on a surface of the passivation layer 880 away from the substrate 100 to provide a flat surface for the pixel electrode 210.

The pixel electrode layer is disposed on the surface of the planarization layer 890 away from the substrate 100, and includes a plurality of pixel electrodes 210. Any pixel electrode 210 is electrically connected to the source-drain metal layer 870 through a metalized via, and more particularly to the drain of the thin film transistor through a metalized via. Any one of the pixel electrodes 210 is provided with a light emitting region 220.

The pixel defining layer 300 is disposed on the surface of the pixel electrode layer away from the substrate 100, and covers the region other than the light emitting region 220. The pixel defining layer 300 may include a first pixel defining layer 301 and a second pixel defining layer 302, wherein the second pixel defining layer 302 is disposed on a surface of the first pixel defining layer 301 away from the substrate 100, and an orthogonal projection of the second pixel defining layer 302 on the substrate 100 is located within an orthogonal projection of the first pixel defining layer 301 on the substrate 100. The thickness of the pixel defining layer 300 is not less than 3.5 micrometers.

The organic light emitting layer 400 is disposed on a side of the pixel defining layer 300 away from the substrate 100, and covers the pixel defining layer 300 and the exposed light emitting regions 220 of the respective pixel electrodes 210.

The common electrode layer 500 is disposed on the surface of the organic light emitting layer 400 away from the substrate 100, and covers the organic light emitting layer 400. The common electrode layer 500 is formed with pixel grooves 510 distributed in an array and disposed in one-to-one correspondence with the plurality of light emitting regions 220.

A bank layer 600 provided on a side of the common electrode layer 500 away from the base substrate 100; an orthogonal projection of the bank layer 600 on the base substrate 100 is located within an orthogonal projection of the second pixel defining layer 302 on the base substrate 100. The thickness of the dam layer 600 is not more than 6 micrometers. The bank layer 600 is formed with the receiving holes 610 distributed in an array and disposed in one-to-one correspondence with the plurality of pixel grooves 510; the orthographic projection of any pixel slot 510 on the substrate base plate 100 is located within the range of the orthographic projection of the corresponding accommodating hole 610 on the substrate base plate 100. Any one of the pixel slots 510 and the corresponding receiving hole 610 together form a receiving slot 710 for receiving the quantum dot unit 701.

The quantum dot layer includes a plurality of quantum dot units 701 distributed in an array, and one quantum dot unit 701 is accommodated in one accommodation groove 710. Wherein, the thickness of the quantum dot unit 701 is not less than 8 microns. It can be understood that one quantum dot unit 701 may be accommodated in each accommodating groove 710, or the quantum dot unit 701 may not be arranged in part of the accommodating grooves 710.

In an embodiment of the present disclosure, there is also provided a method for manufacturing an array substrate, as shown in fig. 6, the method including:

step S210, providing a substrate 100;

step S220, forming a pixel electrode layer on one side of the substrate 100, where the pixel electrode layer includes a plurality of pixel electrodes 210 arranged in an array, and any one of the pixel electrodes 210 has at least one light-emitting region 220;

step S230, as shown in fig. 2, forming a pixel defining layer 300 on a side of the pixel electrode layer away from the substrate 100, wherein the pixel defining layer 300 exposes each light emitting region 220, and the thickness of the pixel defining layer 300 is greater than 1.5 μm;

step S240, as shown in fig. 3, forming an organic light emitting layer 400 on a side of the pixel electrode layer away from the substrate 100, the organic light emitting layer 400 covering the light emitting regions 220 of the pixel electrodes 210;

step S250, as shown in fig. 3, forming a common electrode layer 500 on a side of the organic light emitting layer 400 away from the substrate 100, the common electrode layer 500 covering the organic light emitting layer 400;

step S260, as shown in fig. 4, forming a dam layer 600 on a side of the common electrode layer 500 away from the substrate 100, wherein an orthogonal projection of the dam layer 600 on the substrate 100 is located within an orthogonal projection of the pixel defining layer 300 on the substrate 100;

in step S270, as shown in fig. 1, a quantum dot layer is formed covering at least a portion of the common electrode layer 500 exposed by the bank layer 600.

The array substrate manufacturing method of the present disclosure can manufacture any one of the array substrates described in the above array substrate embodiments. The details, principles and advantages of the preparation method are described in detail in the above embodiment of the array substrate, and the disclosure is not repeated herein.

It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc., are all considered part of this disclosure.

Example two

In the embodiment of the present disclosure, there is provided an array substrate, as shown in fig. 7, including a substrate 100, a planarization layer 890, a pixel electrode layer, a pixel defining layer 300, an organic light emitting layer 400, a common electrode layer 500, a bank layer 600, and a quantum dot layer, wherein,

the planarization layer 890 is provided on one side of the substrate base 100, as shown in fig. 8, the planarization layer 890 is provided with a plurality of grooves 891 distributed in an array; the pixel electrode layer is arranged on one side of the planarization layer 890 away from the substrate 100; the pixel electrode layer includes a plurality of pixel electrodes 210 disposed in one-to-one correspondence with the plurality of grooves 891, and any one of the pixel electrodes 210 is provided with a light emitting region 220; the orthographic projection of the light-emitting region 220 of any pixel electrode 210 on the substrate 100 is positioned in the orthographic projection of the groove bottom of the corresponding groove 891 on the substrate 100; the pixel defining layer 300 is disposed on a side of the pixel electrode layer away from the substrate base plate 100, and exposes each light emitting region 220; the organic light emitting layer 400 is disposed on a side of the pixel electrode layer away from the substrate 100, and covers the light emitting regions 220 of the pixel electrodes 210; the common electrode layer 500 is disposed on a side of the organic light emitting layer 400 away from the substrate 100 and covers the organic light emitting layer 400; the bank layer 600 is disposed on a side of the common electrode layer 500 away from the substrate 100; the orthographic projection of the dam layer 600 on the base substrate 100 is completely misaligned with the orthographic projection of each groove 891 on the base substrate 100; the quantum dot layer covers the common electrode layer 500 at least partially exposed by the bank layer 600.

In the array substrate provided by the embodiment of the present disclosure, as shown in fig. 11, the dam layer 600 is formed with a receiving hole 610 exposing the common electrode layer 500, and the receiving hole 610 and the exposed common electrode layer 500 together form a receiving groove 710 for receiving quantum dot ink. After the quantum dot ink contained in the containing groove 710 is cured, a quantum dot layer of the array substrate can be formed. The larger the depth of the accommodating groove 710 is, the larger the depth of the quantum dot ink that can be accommodated therein is, the larger the thickness of the formed quantum dot layer is, and the higher the conversion efficiency of the quantum dot layer is.

In the prior art, the planarization layer 890 has a planar structure, and in the array substrate according to the embodiment of the disclosure, as shown in fig. 8, the planarization layer 890 is provided with a groove 891, and as shown in fig. 9, the light emitting region 220 of the pixel electrode 210 is located at the bottom of the groove 891. In this way, a predetermined height difference exists between the light emitting region 220 of the pixel electrode 210 and the surface of the planarization layer 890 away from the substrate 100. In this way, when the pixel defining layer 300, the organic light emitting layer 400, the common electrode layer 500 and the bank layer 600 are sequentially formed, the predetermined height difference is not eliminated, so that the depth of the receiving groove 710 formed by the bank layer 600 and the common electrode layer 500 can be increased, thereby increasing the thickness of the quantum dot layer. In this way, in the array substrate according to the embodiment of the present disclosure, the thickness of the quantum dot layer can be increased without increasing the thickness of the bank layer 600, thereby improving the performance of the array substrate.

As shown in fig. 8, the planarization layer 890 is disposed on one side of the substrate 100 and is provided with a plurality of grooves 891 distributed in an array. Alternatively, the planarization layer 890 may be formed by a photolithography process. For example, the planarization layer 890 may be formed by:

step S310, forming a planarization material layer on one side of the substrate base plate 100;

step S320, exposing and developing the planarization material layer to form grooves 891 distributed in an array on the planarization material layer; the remaining planarization material layer forms the planarization layer 890 of the array substrate of this embodiment.

Optionally, the depth of the groove 891 is greater than 2 microns, so that the depth of the receiving groove 710 is increased by at least 2 microns. Since the thickness of the pixel electrode 210 is typically several nanometers or more than ten nanometers, the depth of the groove 891 is not significantly affected by the pixel electrode 210 disposed on the bottom of the groove 891. In the embodiments of the present disclosure, the thickness refers to a dimension of the film layer in a direction perpendicular to a plane of the array substrate, and the depth refers to a dimension of the hole or the groove in the direction perpendicular to the plane of the array substrate. For example, the depth of the groove 891 refers to the dimension of the groove 891 in the direction perpendicular to the plane of the array substrate.

Thus, the depth of the receiving groove 710 can be increased by at least 2 micrometers under the condition that the dam layer 600 is maintained unchanged, or the dam layer 600 can be thinned by 2 micrometers under the condition that the depth of the receiving groove 710 is maintained unchanged, or the depth of the receiving groove 710 can be increased and the dam layer 600 can be thinned at the same time.

In the array substrate of the embodiment of the present disclosure, the planarization layer 890 is provided with the groove 891 for receiving the light emitting region 220 of the pixel electrode 210, which may increase the depth of the receiving groove 710. The depth of the receiving groove 710 and thus the depth of the groove 891 may be determined according to the thickness of the quantum dot layer. Compared to thickening the bank layer 600, it is easier to prepare the groove 891 on the planarization layer 890, and the adverse effect of the process of preparing the groove 891 on other film layers is less. Thus, the depth of the receiving groove 710 can be increased by the depth of the groove 891 without increasing the thickness of the bank layer 600. This not only has avoided adopting more complicated technology to prepare thicker dyke layer 600, can improve the accurate degree of dyke layer 600 pattern moreover, and reduce the adverse effect of dyke layer 600 preparation process to other retes, and then reach the effect that reduces array substrate's preparation cost, improves array substrate's performance.

The pixel electrode layer may include a plurality of pixel electrodes 210 arranged in an array, and any one of the pixel electrodes 210 is provided with at least one light emitting region 220. Alternatively, one pixel electrode 210 is provided with one light emitting region 220. Alternatively, the light emitting region 220 of the pixel electrode 210 may be rectangular, diamond-shaped, rectangular with a notch, or other feasible shapes, which is not limited by the present disclosure.

Alternatively, any one of the pixel electrodes 210 is located at the bottom of the corresponding groove 891.

Alternatively, as shown in fig. 9 and 12, a gap exists between the light emitting region 220 of any one of the pixel electrodes 210 at the edge of the orthographic projection of the substrate base plate 100 and the corresponding groove 891 at the inner edge of the orthographic projection of the substrate base plate 100, so that the pixel defining layer 300 can define the light emitting region 220 more precisely. Further, the gap may be at least 0.5 microns. Alternatively, the gap may be greater than 3 microns. Here, the gap refers to a minimum value of a distance between any point of the light emitting region 220 of the pixel electrode 210 on the edge of the orthogonal projection of the substrate base 100 and any point of the corresponding groove 891 on the inner edge of the orthogonal projection of the substrate base 100.

Alternatively, the shape and size of the light emitting region 220 of each pixel electrode 210 may be the same or different. For example, in one embodiment of the present disclosure, as shown in fig. 12, the light emitting region 222 of the pixel electrode of the red sub-pixel and the light emitting region 223 of the pixel electrode of the green sub-pixel may be rectangular with a notch; the light emitting region 221 of the pixel electrode of the blue sub-pixel may have a rectangular shape and an area smaller than the light emitting region 222 of the pixel electrode of the red sub-pixel and the light emitting region 223 of the pixel electrode of the green sub-pixel.

Optionally, in an embodiment of the present disclosure, as shown in fig. 12, the first direction and the second direction are perpendicular, and all the pixel electrodes 210 located on the same straight line along the first direction are the same type of pixel electrode 210, for example, the pixel electrodes 210 that are all red sub-pixels, or the pixel electrodes 210 that are all green sub-pixels, or the pixel electrodes 210 that are all blue sub-pixels. All the pixel electrodes 210 located on the same line along the second direction are different types of pixel electrodes 210 that are periodically arranged, and may be periodically arranged along the second direction as follows, for example: a pixel electrode 210 of a red sub-pixel, a pixel electrode 210 of a blue sub-pixel, a pixel electrode 210 of a green sub-pixel, and a pixel electrode 210 of a blue sub-pixel.

In one embodiment, the pixel electrode 210 may serve as an anode of the light emitting device. The pixel electrode 210 may select a material having a large work function so that holes can be smoothly injected into the organic light emitting layer 400. The pixel electrode 210 may be one or more anode materials, wherein the anode material may be selected from metals, metal oxides, conductive polymers, or other anode materials. Wherein the metal includes, but is not limited to, vanadium, chromium, copper, zinc, gold, and alloys of any of the foregoing; metal oxides include, but are not limited to, zinc oxide, Indium Tin Oxide (ITO), and Indium Zinc Oxide (IZO); conductive polymers include, but are not limited to, poly (3-methylthiophene), poly [3,4- (ethylene-1, 2-dioxy) thiophene ] (PEDOT), polypyrrole, polyaniline. For example, the material of the pixel electrode 210 may be ITO.

The pixel defining layer 300 exposes each light emitting region 220 so that the light emitting region 220 of each pixel can be in direct surface connection with the organic light emitting layer 400. Alternatively, as shown in fig. 9, a portion of each pixel electrode 210 other than the light emitting region 220 may be covered by the pixel defining layer 300, so that the pixel defining layer 300 may define the light emitting region 220 of the organic light emitting layer 400. In other words, the pixel defining layer 300 forms a plurality of exposure holes 310 in one-to-one correspondence with the respective light emitting regions 220, and an orthogonal projection of any one of the exposure holes 310 on the substrate base plate 100 near the edge of the substrate base plate 100 completely coincides with an orthogonal projection of the corresponding light emitting region 220 on the substrate base plate 100. It is understood that the respective exposure holes 310 are disposed in one-to-one correspondence with the respective grooves 891.

In one embodiment of the present disclosure, the thickness of the pixel defining layer 300 is 0.8 to 1.5 μm. Further, the thickness of the pixel defining layer 300 may be 1 to 1.5 μm.

In another embodiment of the present disclosure, the thickness of the pixel defining layer 300 is greater than 1.5 micrometers, and particularly may be greater than 3.5 micrometers, so that the thickness of the pixel defining layer 300 is further increased compared to the prior art, the depth of the receiving groove 710 may be further increased, and the thickness of the quantum dot layer is further increased.

As shown in fig. 7, the common electrode layer 500 is disposed on a surface of the organic light emitting layer 400 away from the substrate 100, and may be made of a conductive transparent material, such as a magnesium-silver alloy. Alternatively, the common electrode layer 500 is a unitary structure, i.e., the common electrode layer 500 covers the entire organic light emitting layer 400 at the same time.

As shown in fig. 9 and 10, since the planarization layer 890 is provided with the grooves 891 distributed in an array, and the pixel defining layer 300 is provided with the exposure holes 310 arranged in one-to-one correspondence with the respective grooves 891, the surface of the common electrode layer 500 away from the substrate base plate 100 is not a planar structure, but assumes a structure having pixel grooves 510 distributed in an array. Wherein, each pixel groove 510 is disposed opposite to each exposure hole 310, that is, each pixel groove 510 is disposed opposite to each light-emitting region 220 of each pixel electrode 210; in other words, an orthogonal projection of the light emitting region 220 of any one of the pixel electrodes 210 on the substrate 100 at least partially overlaps an orthogonal projection of the corresponding pixel groove 510 on the substrate 100.

As shown in fig. 11, the bank layer 600 is formed on a side of the common electrode layer 500 away from the substrate 100, and may be formed with a plurality of accommodating holes 610 distributed in an array, wherein the plurality of accommodating holes 610 are disposed in one-to-one correspondence with the plurality of pixel slots 510. In other words, the orthographic projection of any pixel slot 510 on the substrate base plate 100 is located within the orthographic projection of the corresponding accommodating hole 610 on the substrate base plate 100. Accordingly, the respective receiving holes 610 are provided in one-to-one correspondence with the respective grooves 891 and the respective exposing holes 310.

Alternatively, as shown in fig. 11, the outer edge of the orthographic projection of the accommodation hole 610 on the base substrate 100 is located in the orthographic projection of the pixel defining layer 300 on the base substrate 100, and as shown in fig. 12, while being located outside the orthographic projection of the base substrate 100 by the corresponding recess 891. In this way, the dam layer 600 may be sequentially supported by the pixel defining layer 300 and portions of the planarization layer 890 other than the groove 891, ensuring the depth of the receiving groove 710.

Optionally, in order to reduce the blocking of the quantum dot layer by the bank layer 600, the distance between any point in the orthographic projection of any light-emitting region 220 on the substrate 100 and any point in the orthographic projection of the bank layer 600 on the substrate 100 is not less than 3 μm. Thus, the orthographic projection of the edge of the light-emitting region 220 on the substrate base plate 100 is located in the orthographic projection of the edge of the corresponding containing hole 610 on the substrate base plate 100, and the gap between the two is at least 3 micrometers.

As shown in fig. 11, the pixel slots 510 and the corresponding receiving holes 610 together form a receiving slot 710 for receiving quantum dot ink. After the quantum dot ink is injected into the receiving groove 710 through inkjet printing or other methods, the quantum dot units 701 can be formed by curing, and each quantum dot unit 701 constitutes a quantum dot layer of the array substrate.

Optionally, the array substrate may further include a driving circuit layer to drive each sub-pixel, and particularly, to provide a driving current to each pixel electrode 210. In one embodiment of the present disclosure, a driving circuit layer may be disposed between the substrate 100 and the planarization layer 890.

In the following, a specific implementation of the array substrate is exemplarily provided in order to further explain and explain the structure, the principle and the effect of the array substrate of the present disclosure.

In the present exemplary embodiment, as shown in fig. 7, the array substrate includes:

a substrate 100, the substrate 100 being a glass substrate;

a shield layer (shield)810 provided on one side of the base substrate 100;

a planarization layer 890 is disposed on the surface of the passivation layer 880 away from the substrate 100, and the planarization layer 890 is provided with a plurality of grooves 891 distributed in an array. The depth of the groove 891 may be greater than 2 microns.

The pixel electrode layer is disposed on the surface of the planarization layer 890 away from the substrate 100, and includes a plurality of pixel electrodes 210. Any pixel electrode 210 is electrically connected to the source-drain metal layer 870 through a metalized via, and more particularly to the drain of the thin film transistor through a metalized via. Any one of the pixel electrodes 210 is provided with a light emitting region 220. The orthogonal projection of the light emitting region 220 of any one of the pixel electrodes 210 on the substrate base 100 is located such that the groove bottom of the corresponding groove 891 is within the orthogonal projection of the substrate base 100.

The pixel defining layer 300 is disposed on the surface of the pixel electrode layer away from the substrate 100, and covers the region other than the light emitting region 220. Wherein the pixel defining layer 300 covers the planarization layer 890 except for the groove 891.

A bank layer 600 provided on a side of the common electrode layer 500 away from the base substrate 100; the orthographic projection of the dam layer 600 on the base substrate 100 and the orthographic projection of each of the grooves 891 on the base substrate 100 do not coincide at all.

The bank layer 600 is formed with the accommodation holes 610 distributed in an array and disposed in one-to-one correspondence with the plurality of pixel grooves 510 and the plurality of grooves 891; the orthographic projection of any pixel slot 510 on the substrate base plate 100 is located within the range of the orthographic projection of the corresponding accommodating hole 610 on the substrate base plate 100. The orthographic projection of any one of the recesses 891 on the substrate base plate 100 is located within the range of the orthographic projection of the corresponding accommodating hole 610 on the substrate base plate 100. Any one of the pixel slots 510 and the corresponding receiving hole 610 together form a receiving slot 710 for receiving the quantum dot unit 701.

In an embodiment of the present disclosure, there is also provided a method for manufacturing an array substrate, as shown in fig. 13, the method including:

step S410, providing a substrate base plate 100;

step S420, forming a planarization layer 890 on one side of the substrate 100, wherein the planarization layer 890 is provided with a plurality of grooves 891 distributed in an array;

step S430, forming a pixel electrode layer on a side of the planarization layer 890 away from the substrate 100, where the pixel electrode layer includes a plurality of pixel electrodes 210 corresponding to the plurality of grooves 891, and any one of the pixel electrodes 210 has a light emitting region 220; the orthographic projection of the light-emitting region 220 of any pixel electrode 210 on the substrate base plate 100 is that the groove bottom of the corresponding groove 891 is in the orthographic projection of the substrate base plate 100;

step S440, forming a pixel defining layer 300 on a side of the pixel electrode layer away from the substrate 100, the pixel defining layer 300 exposing each light emitting region 220;

step S450, forming an organic light emitting layer 400 on a side of the pixel electrode layer away from the substrate 100, wherein the organic light emitting layer 400 covers the light emitting regions 220 of the pixel electrodes 210;

step S460, forming a common electrode layer 500 on a side of the organic light emitting layer 400 away from the substrate 100, wherein the common electrode layer 500 covers the organic light emitting layer 400;

step S470, forming a dam layer 600 on the side of the common electrode layer 500 away from the substrate 100, wherein the orthographic projection of the dam layer 600 on the substrate 100 is completely misaligned with the orthographic projection of each groove 891 on the substrate 100;

step S480, a quantum dot layer is formed, which covers at least a portion of the common electrode layer 500 exposed by the bank layer 600.

EXAMPLE III

The display panel includes any one of the array substrates described in the first embodiment or the second embodiment. The display panel may be a rigid display panel, a flexible display panel, or other type of display panel. Since the display panel has any one of the array substrates described in the first embodiment or the second embodiment, the same advantages are obtained, and details are not repeated in this disclosure.

Embodiments of the present disclosure also provide a display device including any one of the display panels described in the above display panel embodiments. The display device may be a cell phone screen, a computer screen, a television screen, electronic paper, an electronic painted screen, a dashboard, or other type of display device. Since the display device has any one of the display panels described in the above display panel embodiments, the same advantages are achieved, and the details of the disclosure are not repeated herein.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims

1. An array substrate, comprising:

a substrate base plate;

2. The array substrate of claim 1, wherein the pixel definition layer has a thickness greater than 3.5 microns.

3. The array substrate of claim 2, wherein the thickness of the dam layer is not greater than 6 microns.

4. The array substrate of claim 1, wherein the quantum dot layer has a thickness greater than 8 microns.

5. The array substrate of claim 1, wherein the distance between any point in the orthographic projection of any one of the light-emitting regions on the substrate and any point in the orthographic projection of the dam layer on the substrate is not less than 3 μm.

6. The array substrate of claim 1, wherein the pixel defining layer comprises:

7. A preparation method of an array substrate is characterized by comprising the following steps:

providing a substrate base plate;

8. An array substrate, comprising:

a substrate base plate;

9. The array substrate of claim 8, wherein the size of the groove is greater than 2 microns in a direction perpendicular to the plane of the substrate base plate.

10. The array substrate of claim 8, wherein the thickness of the dam layer is not greater than 6 microns.

11. The array substrate of claim 8, wherein the quantum dot layer has a thickness greater than 8 microns.

12. The array substrate of claim 8, wherein the distance between any point in the orthographic projection of any one of the light-emitting regions on the substrate and any point in the orthographic projection of the dam layer on the substrate is not less than 3 μm.

13. A preparation method of an array substrate is characterized by comprising the following steps:

providing a substrate base plate;

14. A display panel comprising the array substrate according to any one of claims 1 to 6, or comprising the array substrate according to any one of claims 8 to 12.

15. A display device characterized by comprising the display panel according to claim 14.