CN110828524B - Driving backboard, manufacturing method of driving backboard, display panel and repairing method of display panel - Google Patents
Driving backboard, manufacturing method of driving backboard, display panel and repairing method of display panel Download PDFInfo
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- CN110828524B CN110828524B CN201911135101.9A CN201911135101A CN110828524B CN 110828524 B CN110828524 B CN 110828524B CN 201911135101 A CN201911135101 A CN 201911135101A CN 110828524 B CN110828524 B CN 110828524B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
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Abstract
The embodiment of the invention provides a driving back plate and a preparation method thereof, a display panel and a repair method thereof, which can avoid bad bright point display of the display panel caused by over-etching in the process of forming a through hole by etching. The pixel driving circuit comprises a substrate and a pixel driving circuit arranged on the substrate and positioned in a sub-pixel; the pixel driving circuit includes a driving transistor; the driving transistor comprises a semiconductor active pattern, a first pole, a second pole and a grid electrode, wherein the first pole is connected with the semiconductor active pattern through a first through hole, and the second pole is connected with the semiconductor active pattern through a second through hole; the driving back plate further comprises a first metal shading pattern arranged on one side, close to the substrate, of the driving transistor, the first metal shading pattern comprises first hollow parts, and the first hollow parts correspond to the first through holes and/or the second through holes one to one; the orthographic projection of the first via hole on the first metal shading pattern is located in the first hollow part, and the orthographic projection of the second via hole on the first metal shading pattern is located in the first hollow part.
Description
Technical Field
The invention relates to the technical field of display, in particular to a driving back plate and a preparation method thereof, a display panel and a repair method thereof.
Background
Self-luminous display panels such as Organic Light-Emitting Diode (OLED) display panels have the advantages of self-luminescence, lightness, thinness, low power consumption, good color rendition, sensitive response, wide viewing angle, etc., and have been widely applied to display devices such as mobile phones, notebook computers, televisions, etc., and become the mainstream of the current market.
Disclosure of Invention
The embodiment of the invention provides a driving back plate and a preparation method thereof, a display panel and a repair method thereof, which can avoid bad bright point display of the display panel caused by over-etching in the process of forming via holes by etching.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in one aspect, a driving back plate is provided, including: the pixel driving circuit comprises a substrate and a pixel driving circuit which is arranged on the substrate and positioned in a sub-pixel.
The pixel driving circuit includes a driving transistor; the driving transistor comprises a semiconductor active pattern, a first pole, a second pole and a grid electrode, wherein the first pole is connected with the semiconductor active pattern through a first through hole, and the second pole is connected with the semiconductor active pattern through a second through hole.
The driving back plate further comprises a first metal shading pattern arranged on one side, close to the substrate, of the driving transistor, the first metal shading pattern comprises first hollow parts, and the first hollow parts correspond to the first through holes and/or the second through holes one to one.
For the first hollow-out part corresponding to the first via hole, the orthographic projection of the first via hole on the first metal shading pattern is positioned in the first hollow-out part; for the first hollow-out part corresponding to the second via hole, the orthographic projection of the second via hole on the first metal shading pattern is located in the first hollow-out part.
Optionally, the second pole is connected to the first metal light shielding pattern through a third via hole; the first hollow parts correspond to the first through holes one by one.
The driving back plate further comprises a second metal shading pattern.
The second metal shading pattern and the first metal shading pattern are arranged on the same layer, and the second metal shading pattern is located in the first hollow-out part and connected with the first metal shading pattern.
Optionally, the pixel driving circuit further includes a storage capacitor, and the storage capacitor includes a first storage electrode.
The first storage electrode and the semiconductor active pattern are arranged on the same layer, and the first storage electrode is obtained by conducting a conductor on a semiconductor.
The first storage electrode is electrically connected with the grid electrode through a connecting electrode, and the connecting electrode is arranged in the same layer with the first pole and the second pole; and the connecting electrode is connected with the first storage electrode through a fourth through hole.
The first metal shading pattern further comprises a second hollow-out part; the orthographic projection of the fourth via hole on the first metal shading pattern is located in the second hollow-out part.
Optionally, the driving backplane further includes a third metal light shielding pattern.
The third metal shading pattern and the first metal shading pattern are arranged on the same layer, and the third metal shading pattern is located in the second hollow-out part and connected with the first metal shading pattern.
Optionally, the first metal light shielding pattern overlaps with a projection of the first storage electrode on the substrate, and a portion of the first metal light shielding pattern overlapping with the first storage electrode serves as a second storage electrode of the storage capacitor.
Optionally, the storage capacitor further includes a second storage electrode, and the second storage electrode includes a first storage sub-electrode and a second storage sub-electrode.
The first storage sub-electrode and the second storage sub-electrode are respectively positioned at two sides of the first storage electrode, and the first storage sub-electrode and the second storage sub-electrode are electrically connected.
The first metal light shielding pattern is overlapped with a projection of the first storage electrode on the substrate, wherein a part of the first metal light shielding pattern, which is overlapped with the first storage electrode, is used as the first storage sub-electrode.
In another aspect, an embodiment of the invention provides a display panel, which includes the driving backplane and a light emitting device disposed in a sub-pixel.
The light emitting device includes a first electrode and a second electrode, the first electrode being closer to the substrate than the second electrode.
The first electrode is electrically connected with the pixel driving circuit.
Optionally, the first electrode also serves as a second storage sub-electrode.
In the driving backplane provided by the embodiment of the invention, in the process of forming the first via hole and the second via hole by etching, over-etching is easily caused, and the semiconductor active pattern is thin and easily causes the semiconductor active pattern to be missing or etched away, so that the first via hole for connecting the first pole and the semiconductor active pattern can be caused, and/or the second via hole for connecting the second pole and the semiconductor active pattern can be caused, and the buffer can also penetrate through, so that the first pole and/or the second pole are/is connected with the first metal light shielding pattern. If a path is formed between the first electrode and the second electrode, the corresponding sub-pixel may emit light abnormally when the display panel is operated, and the bright point of the display panel may be displayed poorly. In the driving back plate provided by the embodiment of the invention, the first hollow parts are arranged on the first metal shading patterns, and the first hollow parts correspond to the first through holes and/or the second through holes one to one. Therefore, even if the first via hole and/or the second via hole penetrates through the buffer layer due to the fact that the first via hole and/or the second via hole is/are etched when the first via hole and/or the second via hole are/is formed in the etching process, the first pole and the second pole are/is not short-circuited due to the fact that the first pole is in contact with the first metal light shielding pattern through the first via hole and/or the second pole is in contact with the first metal light shielding pattern through the second via hole, and therefore corresponding sub-image light emission is caused when voltage is applied to the first pole, and bright point display is poor.
In another aspect, an embodiment of the present invention provides a method for manufacturing a driving backplane, in which a first metal light shielding pattern and a second metal light shielding pattern are synchronously formed on a substrate and in sub-pixels; the first metal shading pattern comprises a first hollow-out part, and the second metal shading pattern is positioned in the first hollow-out part and connected with the first metal shading pattern.
Forming a pixel driving circuit on the substrate and in the sub-pixels; the pixel driving circuit includes a driving transistor; the driving transistor comprises a semiconductor active pattern, a first pole, a second pole and a grid electrode, wherein the first pole is connected with the semiconductor active pattern through a first through hole, and the second pole is connected with the semiconductor active pattern through a second through hole; the first through holes and/or the second through holes correspond to the first hollow parts one by one; for the first hollow-out part corresponding to the first via hole, the orthographic projection of the first via hole on the first metal shading pattern is positioned in the first hollow-out part; for the first hollow-out part corresponding to the second via hole, the orthographic projection of the second via hole on the first metal shading pattern is located in the first hollow-out part.
When the first pole is connected with the first metal shading pattern through the first via hole, so that the first pole and the second pole are short-circuited, the connection between the second metal shading pattern and the first metal shading pattern in the first hollow part corresponding to the first via hole is cut off.
When the second pole is connected with the first metal shading pattern through the second via hole, so that the second pole is short-circuited with the first pole, the connection between the second metal shading pattern and the first metal shading pattern in the first hollow part corresponding to the second via hole is cut off.
Optionally, the first metal light shielding pattern further includes a second hollow portion.
When the first metal shading pattern and the second metal shading pattern are formed, a third metal shading pattern is also synchronously formed; the third metal shading pattern is positioned in the second hollow-out part and is connected with the first metal shading pattern.
The pixel driving circuit further includes a storage capacitor including a first storage electrode formed in synchronization with the semiconductor active pattern, and the first storage electrode is obtained by semiconducting the semiconductor.
The first storage electrode and the gate electrode are electrically connected by a connection electrode, and the connection electrode is formed in synchronization with the first pole and the second pole; the connecting electrode is connected with the first storage electrode through a fourth through hole; the orthographic projection of the fourth via hole on the first metal shading pattern is located in the second hollow-out part.
The preparation method of the driving back plate further comprises the following steps: and when the first storage electrode is connected with the first metal shading pattern through the fourth via hole, cutting off the connection between the third metal shading pattern and the first metal shading pattern.
According to the manufacturing method of the driving back plate provided by the embodiment of the invention, the first metal shading pattern and the second metal shading pattern are synchronously formed; the first metal shading pattern comprises a first hollow-out part, the second metal shading pattern is positioned in the first hollow-out part and connected with the first metal shading pattern, and the first hollow-out part is in one-to-one correspondence with the first via hole and/or the second via hole. Therefore, if the first via hole and/or the second via hole are/is etched to form a short circuit when the first via hole and/or the second via hole are/is etched to form the first via hole and/or the second via hole and the first metal light shielding pattern are/is contacted to form a short circuit when the first pole is contacted to the first metal light shielding pattern through the first via hole, the first pole can be prevented from being contacted to form a short circuit when the first pole is contacted to the first metal light shielding pattern through the first via hole and/or the second pole is contacted to form a short circuit when the second metal light shielding pattern is contacted to the first metal light shielding pattern through the second via hole by cutting off the connection between the second metal light shielding pattern and the first metal light shielding pattern, and the corresponding sub-pixel can emit light when voltage is applied to the first pole, so that the bright spot display is poor.
In another aspect, an embodiment of the present invention provides a method for repairing the display panel, including:
if the first pole is connected with the first metal shading pattern through the first via hole, so that the first pole and the second pole are short-circuited, the connection between the second metal shading pattern and the first metal shading pattern in the first hollow part corresponding to the first via hole is cut off.
If the second pole is connected with the first metal shading pattern through the second via hole, so that the second pole is short-circuited with the first pole, the connection between the second metal shading pattern and the first metal shading pattern in the first hollow part corresponding to the second via hole is cut off.
On this basis, optionally, whether the first pole is short-circuited with the first metal shading pattern through the first via hole is judged: the method comprises the following steps: the first pole 201 of the drive transistor is supplied with a detection voltage.
It is determined whether the sub-pixel P emits light, and if so, it is determined that the first electrode 201 is short-circuited with the first metal light shielding pattern 300 through the first via 2011.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a sub-pixel P according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a driving backplate according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view along AA' of FIG. 3 according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another driving backplate according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view taken along line BB' of FIG. 5 according to an embodiment of the present invention;
FIG. 7 is a cross-sectional view taken along line CC' of FIG. 3 according to an embodiment of the present invention;
FIG. 8a is a schematic diagram of a driving backplate provided in the prior art;
FIG. 8b is a schematic diagram of a driving back plate provided in the prior art;
FIG. 9 is a schematic view of another driving plate according to an embodiment of the present invention;
FIG. 10 is a cross-sectional view in the direction DD' in FIG. 9 according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view taken along direction HH' of FIG. 9 in accordance with an embodiment of the present invention;
fig. 12 is a schematic view of a first metal light shielding pattern according to an embodiment of the invention;
fig. 13 is a schematic view of another first metal light shielding pattern according to an embodiment of the invention;
fig. 14 is a schematic structural diagram of another driving backplate according to an embodiment of the present invention;
FIG. 15 is a cross-sectional view taken in direction EE' of FIG. 14 according to an embodiment of the present invention;
fig. 16 is a schematic view of another first metal light-shielding pattern according to an embodiment of the invention;
fig. 17 is a schematic view of another first metal light shielding pattern according to an embodiment of the invention;
FIG. 18 is a schematic structural diagram of another driving plate according to an embodiment of the present invention;
FIG. 19 is a cross-sectional view taken along direction FF' of FIG. 18 according to an embodiment of the invention;
FIG. 20 is a schematic structural diagram of another driving plate according to an embodiment of the present invention;
FIG. 21 is a cross-sectional view taken along GG' of FIG. 20 according to an embodiment of the present invention;
fig. 22 is a schematic flow chart illustrating a manufacturing method of a driving back plate according to an embodiment of the present invention;
fig. 23 is a schematic flow chart of another method for manufacturing a driving back plate according to an embodiment of the present invention.
Reference numerals:
1-a pixel drive circuit; 20-an interlayer insulating layer; 30-a buffer layer; 121-a first electrode; 122-a second electrode; 123-a light-emitting functional layer; 200-semiconductor active pattern; 201-a first pole; 202-second pole; 203-grid electrode; 204-a gate insulation pattern; 300-a first metal light blocking pattern; 301-a first hollowed-out portion; 302-a second hollowed-out; 400-a second metal light blocking pattern; 501-a first storage electrode; 502-a fourth via; 503-a second storage electrode; 2011-a first via; 2022-a second via; 3001-a third via; 5011-connecting electrodes; 5031-a first storage sub-electrode; 5032-a second storage sub-electrode; 5045-a fifth via; a P-subpixel; t1-drive transistor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the invention provides a display panel, as shown in fig. 1, the display panel includes a display area (AA area for short) and a peripheral area S, and the peripheral area S is disposed around the AA area for example. The AA area includes sub-pixels P of a plurality of colors. The multi-color sub-pixels P include at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, the first color, the second color, and the third color being three primary colors (e.g., red, green, and blue). In fig. 1, the plurality of sub-pixels P are illustrated in an array arrangement.
As shown in fig. 2, the display panel may include a driving backplane that provides the same structure of the pixel driving circuit 1 in each sub-pixel. In addition, the display panel further includes a light emitting device 120 disposed on the driving backplane and located in each sub-pixel.
The light emitting device 120 includes a first electrode 121 and a second electrode 122, and a light emitting function layer 123 between the first electrode 121 and the second electrode 122, wherein the first electrode 121 is closer to the substrate than the second electrode 122. The first electrode 121 is electrically connected to the pixel driving circuit 1 through a via hole. Here, a specific structure of the pixel driving circuit 1 is not illustrated in fig. 2, and the structure of the pixel driving circuit 1 is not limited in the present invention.
Optionally, the first electrode 121 is an anode, and the second electrode 122 is a cathode.
On this basis, the light emitting function layer 123 may include, for example, a light emitting layer, a hole transport layer between the light emitting layer and the first electrode 121, and an electron transport layer between the light emitting layer and the second electrode 122. Of course, in some embodiments, a hole injection layer may be disposed between the hole transport layer and the first electrode 121, and an electron injection layer may be disposed between the electron transport layer and the second electrode 122, as desired.
The driving back plate provided by the embodiment of the invention comprises: the pixel driving circuit comprises a substrate and a pixel driving circuit which is arranged on the substrate and positioned in the sub-pixel P.
As shown in fig. 3 and 4, the pixel driving circuit includes a driving transistor T1; the driving transistor T1 includes a semiconductor active pattern 200, a first pole 201 and a second pole 202, and a gate electrode 203, the first pole 201 being connected to the semiconductor active pattern 200 through a first via 2011, and the second pole 202 being connected to the semiconductor active pattern 200 through a second via 2022.
On this basis, the driving backplane further includes a first metal light shielding pattern 300 disposed on a side of the driving transistor T1 close to the substrate 10, where the first metal light shielding pattern 300 includes a first hollow portion 301, and the first hollow portion 301 corresponds to the first via 2011 and/or the second via 2022.
The first hollow portion 301 corresponds to the first via 2011 and/or the second via 2022 one to one, and there are three conditions as follows: in the first case, as shown in fig. 3 and 4, the first hollow parts 301 correspond to the first vias 2011 only one to one. In the second case, as shown in fig. 5 and fig. 6, the first hollow portions 301 correspond to the first vias 2011, and the first hollow portions 301 correspond to the second vias 2022, i.e., the number of the first hollow portions 301 is the sum of the numbers of the first vias 2011 and the second vias 2022. In the third case, the first hollow portions 301 correspond to the second vias 2022 one to one.
As shown in fig. 3, for the first hollow portion 301 corresponding to the first via 2011, an orthogonal projection of the first via 2011 on the first metal light shielding pattern 300 is located in the first hollow portion 301. As shown in fig. 5, for the first hollow portion 301 corresponding to the second via 2022, an orthogonal projection of the second via 2022 on the first metal light shielding pattern 300 is located in the first hollow portion 301.
That is, for the first case, the orthographic projection of the first via 2011 on the first metal light shielding pattern 300 is located in the first hollow portion 301. For the second case, for the first hollow portion 301 corresponding to the first via 2011, the orthographic projection of the first via 2011 on the first metal light shielding pattern 300 is located in the first hollow portion 301, and for the first hollow portion 301 corresponding to the second via 2022, the orthographic projection of the second via 2022 on the first metal light shielding pattern 300 is located in the first hollow portion 301. For the third case, the orthographic projection of the second via 2022 on the first metal light shielding pattern 300 is located in the first hollow portion 301.
Optionally, the first pole 201 is a drain of the driving transistor T1, and the second pole 202 is a source of the driving transistor T1.
In fig. 3 to 6, the driving transistor T1 is exemplified as a top gate thin film transistor, and in this case, as shown in fig. 4 and 6, the semiconductor active pattern 200 is disposed on the side of the gate electrode 203 close to the substrate 10, the semiconductor active pattern 200 is isolated from the gate electrode 203 by the gate insulating pattern 204, and the first electrode 201, the second electrode 202 and the gate electrode 203 are isolated from each other by the interlayer insulating layer 20. As shown in fig. 4 and 6, the gate insulating pattern 204 is formed in synchronization with the gate electrode 203, and the first via 2011 and the second via 2022 penetrate through the interlayer insulating layer 20.
In this case, the first via 2011 and the second via 2022 penetrate the interlayer insulating layer 20 and the gate insulating layer.
On the basis of the above, since the performance of the driving transistor T1 is important for the pixel driving circuit, and when external light is incident on the semiconductor active pattern 200, the semiconductor active pattern 200 is affected, so that the projection of the semiconductor active pattern 200 on the substrate 10 is located in the projection region of the first metal light-shielding pattern 300 on the substrate 10, thereby avoiding the influence of light on the driving transistor T1.
As shown in fig. 8a and 8b, in the process of forming the first via 201 and the second via 202 by etching, over-etching is easily caused, and the semiconductor active pattern 200 is thinner, which easily causes the semiconductor active pattern 200 to be missing or etched away, thereby resulting in a first via 2011 for connecting the first pole 201 and the semiconductor active pattern 200, and/or a second via 2022 for connecting the second pole 202 and the semiconductor active pattern 200, and further penetrating the buffer layer 30, thereby resulting in the first pole 201 and/or the second pole 202 being connected to the first metal light shielding pattern 300. If a path is formed between the first electrode 201 and the second electrode 202, the corresponding sub-pixel may emit abnormal light during the operation of the display panel, which may result in poor bright point display of the display panel. In the driving backplane according to the embodiment of the present invention, the first hollow-out portion 301 is disposed on the first metal light-shielding pattern 300, and the first hollow-out portion 301 corresponds to the first via 2011 and/or the second via 2022. Thus, even if the first via 2011 and/or the second via 2022 penetrates the buffer layer 30 due to over-etching when the first via 2011 and/or the second via 2011 are/is formed by etching, the first pole 201 is not brought into contact with the first metal light shielding pattern 300 through the first via 2011 and/or the second pole 202 is brought into contact with the first metal light shielding pattern 300 through the second via 2022, so that the first pole 201 and the second pole 202 are short-circuited, and the corresponding sub-pixel P emits light when a voltage is applied to the first pole 201, thereby causing poor display of a bright point.
Considering that in some pixel driving circuits, both the second pole 202 and the first metal light blocking pattern 300 need to be electrically connected through a via hole, there is no problem for the second pole 202 even if the via hole for connecting the second pole 202 and the semiconductor active pattern 200 is over-etched. However, for the first pole 201, if the via hole for connecting the first pole 201 and the semiconductor active pattern 200 is over-etched, the first pole 201 and the first metal light shielding pattern 300 are shorted, and a via may be formed between the first pole 201 and the second pole 202.
Based on this, as shown in fig. 3 and 4, the first hollow portions 301 correspond to the first vias 2011 only one to one. The second electrode 202 is connected to the first metal light shielding pattern 300 through the third via 3001.
Alternatively, as shown in fig. 9 to 12, 14 and 16, the driving back plate further includes a second metal light blocking pattern 400.
The second metal light shielding pattern 400 is disposed on the same layer as the first metal light shielding pattern 300, and the second metal light shielding pattern 400 is located in the first hollow portion 301 and connected to the first metal light shielding pattern 300.
The second metal light shielding pattern 400 and the first metal light shielding pattern 300 are disposed on the same layer and connected to the first metal light shielding pattern 300, that is, the second metal light shielding pattern 400 and the first metal light shielding pattern 300 are formed by the same patterning process and are integrated (as shown in fig. 12).
By disposing the second metal light-shielding pattern 400 in the first hollow portion 301, the first metal light-shielding pattern 300 and the second metal light-shielding pattern 400 can shield light incident from the outside to the semiconductor active pattern 200, thereby improving the light-shielding effect. In addition, when the first via 2011 and/or the second via 2022 are formed by etching, and the first via 2011 and/or the second via 2022 penetrate through the buffer layer 30 to be in contact with the second metal pattern 400, the first pole 201 and/or the second pole 202 may be prevented from being short-circuited with the first metal light shielding pattern 300 by cutting off the connection between the first metal light shielding pattern 300 and the second metal light shielding pattern 400.
Optionally, as shown in fig. 3, 5, 7, 9, 14, 15, 18 and 19, the pixel driving circuit further includes a storage capacitor, and the storage capacitor includes the first storage electrode 501.
The first storage electrode 501 is provided in the same layer as the semiconductor active pattern 200, and the first storage electrode 501 is obtained by semiconducting a semiconductor. That is, the first storage electrode 501 is formed in synchronization with the semiconductor active pattern 200.
The first storage electrode 501 and the gate electrode 203 are electrically connected by a connection electrode 5011, and the connection electrode 5011 is provided in the same layer as the first electrode 201 and the second electrode 202; the connection electrode 5011 and the first storage electrode 501 are connected by a fourth via 502. The connection electrode 5011 is disposed in the same layer as the first and second poles 201 and 202, that is, the connection electrode 5011 is formed by the same patterning process as the first and second poles 201 and 202.
On this basis, the first metal light shielding pattern 300 further includes a second hollow portion 302; the orthographic projection of the fourth via 502 on the first metal light shielding pattern 300 is located in the second hollow portion 302.
By making the first metal light shielding pattern 300 include the second hollow portion 302, the orthographic projection of the fourth via 502 on the first metal light shielding pattern 300 is located in the second hollow portion 302, so that even if the fourth via 502 is over-etched during the etching process, the fourth via still penetrates through the buffer layer 30, the connection electrode 5011 will not contact the first metal light shielding pattern 300 through the fourth via 502 to form a short circuit, and the gate 203 is electrically connected to the first metal light shielding pattern 300.
Optionally, as shown in fig. 14 to 16, the driving back plate further includes a third metal light blocking pattern 600.
The third metal light shielding pattern 600 is disposed on the same layer as the first metal light shielding pattern 300, and the third metal light shielding pattern 600 is located in the second hollow portion 302 and connected to the first metal light shielding pattern 301. The third metal light shielding pattern 600 and the first metal light shielding pattern 300 are disposed on the same layer and connected to the first metal light shielding pattern 301, that is, the third metal light shielding pattern 600 and the first metal light shielding pattern 300 are formed by the same patterning process and are integrated (as shown in fig. 15).
Alternatively, as shown in fig. 3, 5, 7, 9, 14, 15, 18 and 19, the first metal light shielding pattern 300 overlaps the projection of the first storage electrode 501 on the substrate 10, wherein a portion of the first metal light shielding pattern 300 overlapping the first storage electrode 501 serves as the second storage electrode 503 of the storage capacitor.
Optionally, as shown in fig. 18-fig. 21, the storage capacitor further includes a second storage electrode 503, and the second storage electrode 503 includes a first storage sub-electrode 5031 and a second storage sub-electrode 5032.
The first storage sub-electrode 5031 and the second storage sub-electrode 5032 are respectively located at two sides of the first storage electrode 501, the first storage sub-electrode 5031 is connected to the second connection electrode 504 and the second storage sub-electrode 5032 through a fifth via 5045, and the second connection electrode 504 and the second electrode 202 are integrated. Based on this, the first memory sub-electrode 5031 is electrically connected to the second memory sub-electrode 5032.
The first metal light-shielding pattern 300 overlaps the projection of the first storage electrode 501 on the substrate 10, wherein a portion of the first metal light-shielding pattern 300 overlapping the first storage electrode 501 serves as a first storage sub-electrode 5031.
By making the second storage electrode 503 include the first storage sub-electrode 5031 and the second storage sub-electrode 5032, the first storage sub-electrode 5031 and the first storage electrode 501, and the second storage sub-electrode 5032 and the first storage electrode 501 together form a storage capacitor, thereby enhancing the charging capability of the storage capacitor in the pixel driving circuit.
Alternatively, as shown in fig. 18 to 21, the first electrode 121 also serves as the second storage sub-electrode 5032.
In another aspect, as shown in fig. 22, an embodiment of the present invention provides a method for manufacturing a driving back plate, including:
s10, as shown in fig. 12, forming a first metal light shielding pattern 300 and a second metal light shielding pattern 400 on the substrate 10 and in the sub-pixel P simultaneously; the first metal light shielding pattern 300 includes a first hollow portion 301, and the second metal light shielding pattern 400 is located in the first hollow portion 301 and connected to the first metal light shielding pattern 300.
S20, forming a pixel driving circuit on the substrate 10 and in the sub-pixel P; as shown in fig. 9, the pixel drive circuit includes a drive transistor T1; the driving transistor T1 includes a semiconductor active pattern 200, a first pole 201, a second pole 201, and a gate electrode 203, the first pole 201 being connected to the semiconductor active pattern 200 through a first via 2011, the second pole 202 being connected to the semiconductor active pattern 200 through a second via 2022; the first via 2011 and/or the second via 2022 correspond to the first hollow portions 301 one to one; for the first hollow portion 301 corresponding to the first via 2011, an orthographic projection of the first via 2011 on the first metal light shielding pattern 300 is located in the first hollow portion 301; for the first hollow portion 301 corresponding to the second via 2022, the orthographic projection of the second via 2022 on the first metal light shielding pattern 300 is located in the first hollow portion 301.
S30, when the first pole 201 is connected to the first metal light shielding pattern 300 through the first via 2011, such that the first pole 201 is short-circuited with the second pole 202, the connection between the second metal light shielding pattern 400 and the first metal light shielding pattern 300 in the first hollow 301 corresponding to the first via 2011 is cut off (as shown in fig. 13).
S40, when the second pole 202 is connected to the first metal light shielding pattern 300 through the second via 2022, such that the second pole 202 is short-circuited with the first pole 201, the connection between the second metal light shielding pattern 400 and the first metal light shielding pattern 300 in the first hollow 301 corresponding to the second via 2022 is cut off (as shown in fig. 17).
In the manufacturing method of the driving backplane provided by the embodiment of the invention, the first metal shading pattern 300 and the second metal shading pattern 400 are synchronously formed; the first metal light shielding pattern 300 includes a first hollow portion 301, and the second metal light shielding pattern 400 is located in the first hollow portion 301 and connected to the first metal light shielding pattern 300, such that the first hollow portion 301 corresponds to the first via 2011 and/or the second via 2022. Thus, if the first via 2011 and/or the second via 2022 are over-etched during the etching process to form the first via 2011 and/or the second via 2022, the first via 2011 and the first metal light shielding pattern 300 contact each other to form a short circuit, and/or the second pole 202 and the first metal light shielding pattern 300 contact each other to form a short circuit, the connection between the second metal light shielding pattern 400 and the first metal light shielding pattern 300 may be cut off, so as to prevent the first pole 201 and the first metal light shielding pattern 300 from contacting each other to form a short circuit through the first via 2011 and/or the second pole 202 and the first metal light shielding pattern 300 from contacting each other to form a short circuit through the second via 2022 and the first metal light shielding pattern 300, which may cause the corresponding sub-pixel P to emit light when a voltage is applied to the first pole 201, thereby causing poor bright spot display.
Optionally, as shown in fig. 12 and 14, the first metal light shielding pattern 300 further includes a second hollow portion 302.
While forming the first metal light shielding pattern 300 and the second metal light shielding pattern 400, a third metal light shielding pattern 600 is also simultaneously formed; the third metal light shielding pattern 600 is located in the second hollow portion 302 and connected to the first metal light shielding pattern 300.
The pixel driving circuit further includes a storage capacitor including a first storage electrode 501, the first storage electrode 501 is formed in synchronization with the semiconductor active pattern 200, and the first storage electrode 501 is obtained by semiconducting the semiconductor.
The first storage electrode 501 and the gate electrode 203 are electrically connected by a connection electrode 5011, and the connection electrode 5011 is formed in synchronization with the first pole 201 and the second pole 202; the connection electrode 5011 is connected to the first storage electrode 501 through a fourth via 502, and an orthogonal projection of the fourth via 502 on the first metal light shielding pattern 300 is located in the second hollow portion 302.
As shown in fig. 23, the method for preparing the driving back plate further includes:
s50, when the first storage electrode 501 is connected to the first metal light blocking pattern 300 through the fourth via hole 502, the connection of the third metal light blocking pattern 600 to the first metal light blocking pattern 300 is cut off (as shown in fig. 14).
By also forming the third light shielding pattern 600 simultaneously when the first and second metal light shielding patterns 300 and 400 are formed; the third metal light shielding pattern 600 is located in the second hollow portion 302 and connected to the first metal light shielding pattern 300, such that the orthographic projection of the fourth via 502 on the first metal light shielding pattern 300 is located in the second hollow portion 302, and thus, if the fourth via 502 is formed by etching, the fourth via 502 still penetrates through the buffer layer 30, and a short circuit between the first storage electrode 501 and the first metal light shielding pattern 300 can be avoided by cutting off the connection between the third metal light shielding pattern 600 and the first metal light shielding pattern 300. If the fourth via hole 502 is not etched, the third metal light-shielding pattern 600 may also form a part of the storage capacitor, so as to ensure the charging capability of the storage capacitor in the pixel driving circuit.
The embodiment of the invention provides a method for repairing a display panel, which comprises the following steps:
if the first pole 201 is connected to the first metal light shielding pattern 300 through the first via 2011, such that the first pole 201 and the second pole 202 are short-circuited, the connection between the second metal light shielding pattern 400 and the first metal light shielding pattern 300 in the first hollow portion 301 corresponding to the first via 2011 is cut off.
If the second pole 202 is connected to the first metal light shielding pattern 300 through the second via 2022, such that the second pole 202 is short-circuited with the first pole 201, the connection between the second metal light shielding pattern 400 and the first metal light shielding pattern 300 in the first hollow portion 301 corresponding to the second via 2022 is cut off.
Considering that in some pixel driving circuits, the second electrode 202 and the first metallic light-shielding layer 300 both need to be electrically connected through a via hole, there is no problem for the second electrode 202 even if the via hole for connecting the second electrode 202 and the semiconductor active pattern 200 is over-etched. However, for the first pole 201, if the via hole for connecting the first pole 201 and the semiconductor active pattern 200 is over-etched, the first pole 201 and the first metal light shielding pattern 300 are shorted, and a via may be formed between the first pole 201 and the second pole 202.
On this basis, optionally, it is determined whether the first pole 201 is short-circuited with the first metal light shielding pattern 300 through the first via 2011:
the method comprises the following steps: the detection voltage is supplied to the first pole 201 of the driving transistor T1.
It is determined whether the sub-pixel P emits light, and if so, it is determined that the first electrode 201 is short-circuited with the first metal light shielding pattern 300 through the first via 2011.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A drive backplate, comprising: the pixel driving circuit is arranged on the substrate and positioned in the sub-pixels;
the pixel driving circuit comprises a driving transistor and a storage capacitor; the driving transistor comprises a semiconductor active pattern, a first pole, a second pole and a grid electrode, wherein the first pole is connected with the semiconductor active pattern through a first through hole, and the second pole is connected with the semiconductor active pattern through a second through hole; the storage capacitor comprises a first storage electrode, the first storage electrode and the semiconductor active pattern are arranged on the same layer, and the first storage electrode is obtained by conducting semiconductorization on a semiconductor; the first storage electrode is electrically connected with the grid electrode through a connecting electrode, and the connecting electrode is arranged in the same layer with the first pole and the second pole; the connecting electrode is connected with the first storage electrode through a fourth through hole;
the driving back plate further comprises a first metal shading pattern arranged on one side, close to the substrate, of the driving transistor, the first metal shading pattern comprises first hollow parts, and the first hollow parts correspond to the first through holes and/or the second through holes one to one;
for the first hollow-out part corresponding to the first via hole, the orthographic projection of the first via hole on the first metal shading pattern is positioned in the first hollow-out part; for the first hollow-out part corresponding to the second via hole, the orthographic projection of the second via hole on the first metal shading pattern is positioned in the first hollow-out part;
the first metal shading pattern further comprises a second hollow-out part; the orthographic projection of the fourth via hole on the first metal shading pattern is located in the second hollow-out part.
2. The driving backplane according to claim 1, wherein the second pole is connected to the first metal light shielding pattern through a third via;
the first hollow parts correspond to the first through holes one by one.
3. The driving backplate of claim 1, further comprising a second metal light blocking pattern;
the second metal shading pattern and the first metal shading pattern are arranged on the same layer, and the second metal shading pattern is located in the first hollow-out part and connected with the first metal shading pattern.
4. The driving backplate of claim 1, further comprising a third metal light blocking pattern;
the third metal shading pattern and the first metal shading pattern are arranged on the same layer, and the third metal shading pattern is located in the second hollow-out part and connected with the first metal shading pattern.
5. The driving backplate of claim 1, wherein the first metal light blocking pattern overlaps the projection of the first storage electrode on the substrate, and wherein the portion of the first metal light blocking pattern overlapping the first storage electrode serves as the second storage electrode of the storage capacitor.
6. The driving backplane of claim 1, wherein the storage capacitor further comprises a second storage electrode comprising a first storage sub-electrode and a second storage sub-electrode;
the first storage sub-electrode and the second storage sub-electrode are respectively positioned at two sides of the first storage electrode, and the first storage sub-electrode and the second storage sub-electrode are electrically connected;
the first metal light shielding pattern is overlapped with a projection of the first storage electrode on the substrate, wherein a part of the first metal light shielding pattern, which is overlapped with the first storage electrode, is used as the first storage sub-electrode.
7. A display panel comprising the driving backplane of any one of claims 1 to 6, and a light emitting device disposed in a subpixel;
the light emitting device includes a first electrode and a second electrode, the first electrode being closer to the substrate than the second electrode;
the first electrode is electrically connected with the pixel driving circuit.
8. The display panel according to claim 7, wherein the first electrode also serves as a second storage sub-electrode.
9. A method for preparing a driving back plate is characterized by comprising the following steps:
synchronously forming a first metal shading pattern and a second metal shading pattern on the substrate and in the sub-pixels; the first metal shading pattern comprises a first hollow part and a second hollow part, and the second metal shading pattern is positioned in the first hollow part and is connected with the first metal shading pattern;
forming a pixel driving circuit on the substrate and in the sub-pixels; the pixel driving circuit comprises a driving transistor and a storage capacitor; the driving transistor comprises a semiconductor active pattern, a first pole, a second pole and a grid electrode, wherein the first pole is connected with the semiconductor active pattern through a first through hole, and the second pole is connected with the semiconductor active pattern through a second through hole; the storage capacitor includes a first storage electrode formed in synchronization with the semiconductor active pattern, and the first storage electrode is obtained by semiconducting a semiconductor; the first storage electrode and the grid electrode are electrically connected through a connecting electrode, the connecting electrode is synchronously formed with the first pole and the second pole, and the connecting electrode is connected with the first storage electrode through a fourth through hole; the first through holes and/or the second through holes correspond to the first hollow parts one by one; for the first hollow-out part corresponding to the first via hole, the orthographic projection of the first via hole on the first metal shading pattern is positioned in the first hollow-out part; for the first hollow-out part corresponding to the second via hole, the orthographic projection of the second via hole on the first metal shading pattern is positioned in the first hollow-out part; the orthographic projection of the fourth via hole on the first metal shading pattern is positioned in the second hollow part;
when the first pole is connected with the first metal shading pattern through the first via hole, so that the first pole and the second pole are short-circuited, the connection between the second metal shading pattern and the first metal shading pattern in the first hollow part corresponding to the first via hole is cut off;
when the second pole is connected with the first metal shading pattern through the second via hole, so that the second pole is short-circuited with the first pole, the connection between the second metal shading pattern and the first metal shading pattern in the first hollow part corresponding to the second via hole is cut off.
10. The method of manufacturing a driving back plate according to claim 9,
when the first metal shading pattern and the second metal shading pattern are formed, a third metal shading pattern is also synchronously formed; the third metal shading pattern is positioned in the second hollow part and is connected with the first metal shading pattern;
the preparation method of the driving back plate further comprises the following steps: and when the first storage electrode is connected with the first metal shading pattern through the fourth via hole, cutting off the connection between the third metal shading pattern and the first metal shading pattern.
11. A repair method for repairing the display panel according to claim 7 or 8, in a case where the display panel includes the driving backplane according to claim 3, comprising:
if the first pole is connected with the first metal shading pattern through the first via hole, so that the first pole and the second pole are short-circuited, cutting off the connection between the second metal shading pattern and the first metal shading pattern in the first hollow part corresponding to the first via hole;
if the second pole is connected with the first metal shading pattern through the second via hole, so that the second pole is short-circuited with the first pole, the connection between the second metal shading pattern and the first metal shading pattern in the first hollow part corresponding to the second via hole is cut off.
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| CN104733499A (en) * | 2013-12-23 | 2015-06-24 | 乐金显示有限公司 | Organic Light Emitting Diode Display Device And Method Of Fabricating The Same |
| KR20150075512A (en) * | 2013-12-26 | 2015-07-06 | 엘지디스플레이 주식회사 | Thin film transistor array substrate and method for fabricating the same |
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