CN110828484A - Display panel, manufacturing method thereof and display device - Google Patents
Display panel, manufacturing method thereof and display device Download PDFInfo
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- CN110828484A CN110828484A CN201911135494.3A CN201911135494A CN110828484A CN 110828484 A CN110828484 A CN 110828484A CN 201911135494 A CN201911135494 A CN 201911135494A CN 110828484 A CN110828484 A CN 110828484A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
Abstract
The invention discloses a display panel, a manufacturing method thereof and a display device, wherein the display panel comprises: the pixel structure comprises a substrate base plate, a driving circuit, a flat layer and a pixel defining layer, wherein the driving circuit is positioned on the substrate base plate; the flat layer is provided with a groove at one side far away from the substrate, and part of the pixel defining layer is positioned in the groove; the orthographic projection of the groove on the substrate base plate is positioned in the range of the orthographic projection of the pattern of the pixel defining layer on the substrate base plate. In the display panel provided by the embodiment of the invention, the groove is arranged on one side of the flat layer, which is far away from the substrate, and part of the pixel defining layer is positioned in the groove, so that the contact area between the pixel defining layer and the flat layer is increased, and the pixel defining layer is prevented from falling off.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, and a display device.
Background
Since an Organic Light-Emitting Diode (OLED) has the advantages of self-luminescence, high contrast, fast response speed, flexible display, simple process, and the like, the OLED is gradually becoming the mainstream of display industry development. At present, an organic electroluminescent layer in an OLED display has two manufacturing methods, namely an evaporation method and an ink-jet printing method, wherein the ink-jet printing method is suitable for macromolecular luminescent materials and micromolecular luminescent materials, the material utilization rate is high, the equipment cost is low, the high yield is realized, and the large-scale and large-size product production is easier.
However, in order to achieve a good display effect, it is necessary to form a light emitting layer having a uniform thickness in a pixel region, which requires a very good flatness of the pixel region. The flat layer is generally made of an organic siloxane resin material with high polarity, in addition, a pixel defining layer is also arranged above the flat layer for defining a pixel area and preventing ink from overflowing to the periphery, the material of the pixel defining layer is generally a fluorine-containing material with low polarity, and the adhesion between the pixel defining layer and the flat layer is insufficient due to the large polarity difference between the pixel defining layer and the flat layer, so that the pixel defining layer is easy to fall off, and the display quality is influenced.
Disclosure of Invention
The embodiment of the invention provides a display panel, a manufacturing method thereof and a display device, which are used for solving the problem that a pixel defining layer is easy to fall off due to insufficient adhesion between the pixel defining layer and a flat layer in the prior art.
In a first aspect, an embodiment of the present invention provides a display panel, including: the pixel structure comprises a substrate, a driving circuit, a flat layer and a pixel definition layer, wherein the driving circuit is positioned on the substrate, the flat layer is positioned on one side, away from the substrate, of the driving circuit, and the pixel definition layer is positioned on one side, away from the substrate, of the flat layer;
the flat layer is provided with a groove on one side facing away from the substrate base plate, and part of the pixel defining layer is positioned in the groove;
the orthographic projection of the groove on the substrate base plate is positioned in the range of the orthographic projection of the pattern of the pixel defining layer on the substrate base plate.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the display panel further includes: a plurality of first electrodes between the planarization layer and the pixel defining layer;
the orthographic projection of the groove on the substrate base plate and the orthographic projection of the first electrode on the substrate base plate are not overlapped.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, an orthogonal projection of the groove on the substrate base surrounds an orthogonal projection of the first electrode on the substrate base.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, at least two grooves are disposed around the same first electrode.
In a possible implementation manner, in the display panel provided by the embodiment of the present invention, each of the first electrodes is surrounded by the groove.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the display panel further includes: a passivation layer between the driving circuit and the planarization layer, and a plurality of via holes penetrating the planarization layer and the passivation layer;
the first electrode is electrically connected with the driving circuit through the through hole;
the orthographic projection of the through hole on the substrate base plate and the orthographic projection of the groove on the substrate base plate are not overlapped.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing the display panel, including:
forming each film layer in the driving circuit on the substrate;
forming a flat layer on the driving circuit, and patterning the flat layer to form a groove on one side of the flat layer, which is far away from the substrate;
a pattern of pixel definition layers is formed over the planarization layer.
In a possible implementation manner, in the above manufacturing method provided in an embodiment of the present invention, before forming a planarization layer over the driving circuit, the method further includes:
forming a passivation layer over the driving circuit;
the patterning the planarization layer includes:
and forming the groove and a through hole penetrating through the flat layer and the passivation layer by adopting the same composition process.
In a possible implementation manner, in the above manufacturing method provided in an embodiment of the present invention, before forming a planarization layer over the driving circuit, the method further includes:
forming a passivation layer over the driving circuit;
the patterning the planarization layer includes:
forming a photoresist layer over the planarization layer;
exposing the photoresist layer by using a half-tone mask to form a first via hole and a first pit; the first via hole corresponds to a position of a through hole penetrating through the flat layer and the passivation layer to be formed, and the first pit corresponds to a position of a groove in the flat layer to be formed;
etching the flat layer and the passivation layer to form a second pit penetrating through the flat layer and part of the passivation layer;
ashing the photoresist layer to form a second through hole at the position of the first pit;
and etching the flat layer to form the groove and etching the passivation layer to form a through hole penetrating through the flat layer and the passivation layer by adopting the same composition process.
In a third aspect, an embodiment of the present invention further provides a display device, including: the display panel is provided.
The invention has the following beneficial effects:
the display panel, the manufacturing method thereof and the display device provided by the embodiment of the invention comprise the following steps: the pixel structure comprises a substrate base plate, a driving circuit, a flat layer and a pixel defining layer, wherein the driving circuit is positioned on the substrate base plate; the flat layer is provided with a groove at one side far away from the substrate, and part of the pixel defining layer is positioned in the groove; the orthographic projection of the groove on the substrate base plate is positioned in the range of the orthographic projection of the pattern of the pixel defining layer on the substrate base plate. In the display panel provided by the embodiment of the invention, the groove is arranged on one side of the flat layer, which is far away from the substrate, and part of the pixel defining layer is positioned in the groove, so that the contact area between the pixel defining layer and the flat layer is increased, and the pixel defining layer is prevented from falling off.
Drawings
Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view taken along dashed line L in FIG. 1;
FIGS. 3 to 7 are schematic top views of display panels before forming a pixel defining layer;
fig. 8 is a flowchart illustrating a method for manufacturing the display panel according to an embodiment of the present invention;
fig. 9a to 9d are schematic structural diagrams of steps in the above-described manufacturing method according to an embodiment of the present invention;
fig. 10 is a second flowchart of a method for manufacturing the display panel according to the embodiment of the invention;
fig. 11a to 11d are schematic structural diagrams of steps in the above-described manufacturing method according to an embodiment of the present invention.
Detailed Description
Aiming at the problem that the pixel defining layer is easy to fall off due to insufficient adhesion between the pixel defining layer and the flat layer in the prior art, the embodiment of the invention provides a display panel, a manufacturing method thereof and a display device.
Embodiments of a display panel, a method for manufacturing the same, and a display device according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The thicknesses and shapes of the various film layers in the drawings are not to be considered true proportions, but are merely intended to illustrate the present invention.
In a first aspect, an embodiment of the present invention provides a display panel, fig. 1 is a schematic top view structure diagram of the display panel provided in the embodiment of the present invention, and fig. 2 is a schematic cross-sectional diagram of a dotted line L in fig. 1, as shown in fig. 1 and fig. 2, including: a substrate base plate 101, a driving circuit 102 positioned on the substrate base plate 101, a flat layer 103 positioned on one side of the driving circuit 102, which is far away from the substrate base plate 101, and a pixel defining layer 104 positioned on one side of the flat layer 103, which is far away from the substrate base plate 101;
the flat layer 103 has a groove U on a side away from the substrate base plate 101, and a part of the pixel defining layer 104 is located in the groove U;
the orthographic projection of the groove U on the substrate base plate 101 is within the range of the orthographic projection of the pattern of the pixel defining layer 104 on the substrate base plate 101.
In the display panel provided by the embodiment of the invention, the groove is arranged on one side of the flat layer, which is far away from the substrate, and part of the pixel defining layer is positioned in the groove, so that the contact area between the pixel defining layer and the flat layer is increased, and the pixel defining layer is prevented from falling off.
The display panel provided by the embodiment of the invention can be an organic electroluminescence (OLED) display panel, so that the display panel provided by the embodiment of the invention can realize a flexible, bendable or foldable display panel besides a conventional display function.
The display panel may include a plurality of pixel units, each of the drawings in the embodiment of the present invention is only illustrated by taking a complete pixel unit as an example, and when the display panel is implemented in detail, the number of the pixel units may be set according to actual requirements, which is not limited herein.
In order to realize the screen display, the display panel may further include: a plurality of first electrodes 105 disposed between the planarization layer 103 and the pixel defining layer 104, a second electrode (not shown) disposed on a side of the pixel defining layer 104 away from the substrate 101, and an organic electroluminescent layer (not shown) disposed between the first electrodes 105 and the second electrode. In the embodiment of the present invention, the first electrode is taken as an anode, and the second electrode is taken as a cathode, but in practical application, the first electrode may be taken as a cathode, and the second electrode may be taken as an anode.
The pixel defining layer 104 may define an opening region of the pixel unit, and specifically, the pixel defining layer 104 includes a plurality of openings T penetrating through the pixel defining layer 104, and the pixel defining layer 104 needs to have a certain thickness so as to accommodate the organic electroluminescent layer in the openings T. The first electrode 105 may be in a block shape, each pixel corresponds to one first electrode and one opening T, the second electrode may be disposed in a whole layer, and in a specific implementation, by applying an electrical signal to the first electrode 105 and the second electrode, under the action of an electric field, holes generated by the first electrode and electrons generated by the second electrode move, so that the holes and the electrons move into the organic electroluminescent layer to meet each other, and light is emitted.
Referring to fig. 1 and 2, a driving circuit 102 is disposed on a substrate 101, the driving circuit 102 may include a thin film transistor, a data line, a gate line, and the like, the thin film transistor includes an active layer, a gate electrode, a source electrode, a drain electrode, and the like, and a first electrode 105 in a pixel unit may be electrically connected to the driving circuit 102 by being electrically connected to the drain electrode, so that a driving signal may be provided to the first electrode 105 by the driving circuit 102 to control each pixel unit to emit light, respectively, thereby implementing image display.
The flat layer 103 is arranged on the side, away from the substrate base plate 101, of the driving circuit 102, so that the driving circuit 102 can be flattened, and a light-emitting layer with uniform thickness can be formed in the subsequent process of manufacturing the organic electroluminescent layer. The surface of the flat layer 103, which is away from the substrate 101, is provided with the plurality of grooves U, and part of the pixel defining layer 104 is positioned in the grooves U, so that the contact area between the flat layer 103 and the pixel defining layer 104 is increased, the bonding force between the flat layer 103 and the pixel defining layer 104 is increased, the pixel defining layer 104 is prevented from falling off, and the display panel is ensured to have a better display effect.
In addition, the orthographic projection of the groove U in the planarization layer 103 on the substrate base plate 101 should be within the range of the orthographic projection of the pattern of the pixel defining layer 104 on the substrate base plate 101, so as to avoid the exposure of the groove U in the planarization layer 103 at the opening T of the pixel defining layer 104 and the influence on the planarization of the organic electroluminescent layer formed in the opening T. In specific implementation, the size of the opening U may be set to be slightly smaller than the internal size, so that the pixel defining layer 104 formed subsequently is clamped into the planar layer 103, and the bonding force between the planar layer 103 and the pixel defining layer 104 is further increased.
The groove U is arranged on the side, away from the substrate base plate 101, of the flat layer 103, so that the bonding force between the flat layer 103 and the pixel defining layer 104 is increased, and therefore, even if the polarity difference between the flat layer 103 and the pixel defining layer 104 is large, the pixel defining layer 104 is not easy to fall off, and therefore, in specific implementation, the flat layer 103 can be made of organic siloxane resin materials with high polarity, so that the flat layer 103 has good flat performance. The pixel defining layer 104 may be made of a lyophobic material with low polarity, for example, a material containing fluorine, and in the process of fabricating the organic electroluminescent layer by an inkjet printing process, the phenomenon that ink is easily spread on the pattern of the pixel defining layer 104 to contaminate the adjacent pixel units can be avoided, thereby avoiding color cross-talk.
In specific implementation, as shown in fig. 1 and fig. 2, the display panel provided in the embodiment of the present invention may further include: a plurality of first electrodes 105 located between the planarization layer 103 and the pixel defining layer 104;
the orthographic projection of the groove U on the substrate base plate 101 and the orthographic projection of the first electrode 105 on the substrate base plate 101 do not overlap.
As shown in fig. 1, the orthographic projection of the opening T in the pixel defining layer 104 on the substrate is located within the range of the orthographic projection of the first electrode 105 on the substrate, so that the position of the groove U is kept away from the position of the first electrode 105, the position of the groove U is kept away from the position of the opening T in the pixel defining layer 104, and the groove U is prevented from being formed in the opening area of the pixel unit, so as to ensure that the groove U does not affect the flatness of the organic electroluminescent layer, and ensure that the display panel has a good display effect.
In order to more clearly illustrate the position and shape of the groove U, fig. 3 to 7 show schematic top-view structures of the display panel before forming the pixel defining layer, and the shape of the pattern of the pixel defining layer can refer to the schematic top-view structure of the display panel shown in fig. 1.
In practical applications, as shown in fig. 3, in the display panel provided by the embodiment of the present invention, an orthographic projection of the groove U on the substrate base surrounds an orthographic projection of the first electrode 105 on the substrate base.
The groove U is in a ring structure around the first electrode 105, so that the contact area between the pixel defining layer and the flat layer 103 is increased around the first electrode 105, and the bonding force between the pixel defining layer and the flat layer 103 is large, so that the pixel defining layer is not easy to fall off.
Further, in the display panel provided in the embodiment of the present invention, as shown in fig. 4, at least two grooves U are disposed around the same first electrode 105.
By arranging at least two circles of grooves U around the first electrode 105, the contact area between the pixel defining layer and the flat layer 103 can be further increased, the bonding force between the pixel defining layer and the flat layer 103 is further increased, and the pixel defining layer is less prone to falling off. In fig. 4, only two circles of the grooves U are illustrated as an example, and three or more circles of the grooves U may be provided around the first electrode 105 if the space allows, and the number of the grooves U is not limited herein.
In practical implementation, in the display panel provided in the embodiment of the present invention, each of the first electrodes is surrounded by the groove. The grooves are arranged around each first electrode, so that the contact area between the pixel defining layer and the flat layer can be further increased, the bonding force between the pixel defining layer and the flat layer can be further increased, the grooves can be uniformly distributed in the display panel, the bonding force between the pixel defining layer and the flat layer is uniformly distributed, and the pixel defining layer is less prone to falling off.
In practical application, the number of turns of the grooves arranged around each first electrode is the same, or the number of turns of the grooves arranged around the first electrode in the region where the first electrode is easy to fall off is large, the number of the grooves can be arranged according to practical requirements, and the number and distribution of the grooves are not limited.
In addition, the orthographic projection of the groove on the substrate may be set to half surround the orthographic projection of the first electrode on the substrate, as shown in fig. 5, the groove U may be set to surround the first electrode 105 on the upper, lower and left sides, or, as shown in fig. 6, the groove U may be set to surround the first electrode 105 only on the two sides and be "L" shaped, and fig. 5 and 6 illustrate two cases where the groove half surrounds the first electrode only, and in the specific implementation, the shape of the groove may be set according to the actual situation and the size of the space, and is not limited herein.
In addition, as shown in fig. 7, the groove U may also be a strip structure located on one side of the first electrode 105, and the length of the groove may be set according to practical situations and space sizes, which is not limited herein.
In fig. 3 to fig. 7, the grooves are illustrated as being located at the edge of the first electrode, and in practical applications, the first electrode and the grooves may have a certain distance therebetween, which is not limited herein.
Specifically, in order to guarantee that the groove can effectively increase the binding force between the pixel defining layer and the flat layer, the width of the groove can be set to be within the range of 0.5-5 um, and the depth can be set to be within the range of 0.1-4 um.
In practical applications, as shown in fig. 1 and fig. 2, the display panel provided in the embodiment of the present invention may further include: a passivation layer 106 between the driving circuit 102 and the planarization layer 103, and a plurality of via holes V penetrating the planarization layer 103 and the passivation layer 106;
the first electrode 105 is electrically connected to the driving circuit 102 through a via hole V;
the orthographic projection of the through hole V on the substrate base plate 101 and the orthographic projection of the groove U on the substrate base plate 101 do not overlap.
The first electrode 105 may be electrically connected to the driving circuit 102 through the through hole V, and specifically, the first electrode 105 may be electrically connected to the drain of the thin film transistor through the through hole V, so that the driving circuit 102 may provide a driving signal to the first electrode 105 to control each pixel unit to emit light, thereby implementing image display.
The groove U is set to avoid the position of the through hole V, so that the through hole V can be prevented from affecting the contact between the pixel defining layer and the planarization layer, and the groove U can be prevented from affecting the electrical connection between the first electrode 105 and the driving circuit 102.
In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a manufacturing method of the display panel. Because the principle of the manufacturing method for solving the problems is similar to that of the display panel, the implementation of the manufacturing method can be referred to that of the display panel, and repeated details are not repeated.
As shown in fig. 8, the method for manufacturing the display panel according to the embodiment of the present invention includes:
s201, forming each film layer in a driving circuit on a substrate;
s202, forming a flat layer on the driving circuit, and patterning the flat layer to form a groove on one side of the flat layer, which is far away from the substrate;
s203, forming a pattern of a pixel defining layer on the flat layer.
According to the manufacturing method of the display panel, provided by the embodiment of the invention, the flat layer is patterned to form the groove on the side, away from the substrate, of the flat layer, so that part of the pixel defining layer formed subsequently can be embedded into the groove, the contact area between the pixel defining layer and the flat layer is increased, the bonding force between the pixel defining layer and the flat layer is increased, and the pixel defining layer is effectively prevented from falling off.
In step S201, referring to fig. 9a, each film layer in the driving circuit 102 is formed on the substrate 101, the driving circuit generally includes a plurality of thin film transistors and a plurality of signal lines, and in order to avoid the mutual influence between the signal lines, an insulating layer is further included between the adjacent signal lines, so the manufacturing process of the driving circuit includes the patterning of a plurality of metal layers and the formation of a plurality of insulating layers.
Specifically, in the manufacturing method provided by the embodiment of the present invention, before the step S202, the manufacturing method may further include:
referring to fig. 9a, a passivation layer 106 is formed over the driving circuit 102;
the above step S202 can have various implementations, and two specific implementations are described as examples below.
The implementation mode is as follows:
in step S202, the patterning of the planarization layer includes:
and forming a groove and a through hole penetrating through the flat layer and the passivation layer by adopting the same patterning process. The grooves and the through holes are manufactured by the same composition process, so that a mask can be saved, and a manufacturing process can be saved, thereby saving the manufacturing cost.
Specifically, as shown in fig. 9b, a photoresist layer 107 is coated on the planarization layer 103, and after the photoresist layer 107 is subjected to an exposure and development process, via holes corresponding to the grooves and the through holes are formed in the photoresist layer 107, as shown in fig. 9c, the planarization layer 103 and the passivation layer 106 are etched by a dry etching process to form through holes V penetrating through the planarization layer 103 and the passivation layer 106 and grooves U on the surface of the planarization layer 103, and the photoresist layer is stripped to obtain the structure shown in fig. 9 c.
As shown in fig. 9d, after the step S202 and before the step S203, the method may further include: a plurality of first electrodes 105 are formed on the planarization layer 103, and specifically, a metal layer may be deposited first, and then a patterning process is used to form a plurality of first electrodes 105, so that each first electrode 105 is electrically connected to the driving circuit 102 through the via hole V.
The implementation mode two is as follows:
as shown in fig. 10, in step S202, the patterning of the planarization layer includes:
s301, referring to fig. 11a, forming a photoresist layer 107 over the planarization layer 103;
s302, referring to fig. 11b, exposing the photoresist layer 107 with a half-tone mask (half tone mask) to form a first via hole W1 and a first pit R1; the first via hole W1 corresponds to a position of a through hole V to be formed through the planarization layer 103 and the passivation layer 106, and the first pit R1 corresponds to a position of a groove U in the planarization layer 103 to be formed;
by using the halftone mask, it is possible to set the transmittance of the regions corresponding to the through-holes V and the grooves U to be different, and thus, when the photoresist layer 107 is exposed using ultraviolet light, the exposure degree of the photoresist layer 107 in the regions corresponding to the through-holes V and the grooves U can be made different, so that the first via holes W1 can be formed at the positions corresponding to the through-holes V, and the first recesses R1 can be formed at the positions corresponding to the grooves U.
S303, referring to fig. 11c, etching the planar layer 103 and the passivation layer 106 to form a second recess R2 penetrating through the planar layer 103 and a portion of the passivation layer 106; that is, in step S303, the passivation layer 106 is not etched through, but a part of the passivation layer is protected, so that the pattern of the driving circuit 102 is protected in the subsequent step, and the pattern of the driving circuit 102 is prevented from being damaged in the subsequent step.
Only the planarization layer 103 and a portion of the passivation layer 106 at the first via W1 are etched in step S303, so that the depth of the formed second recess R2 can be adjusted by adjusting the parameters of the etching process in step S303.
In the actual process, the dry etching gas ratio and the dry etching time of the dry etching process in step S303 need to be controlled to ensure that the photoresist layer 107 at the position of the first pit R1 is not damaged and etched through, so as to ensure that only the planarization layer 103 and part of the passivation layer 106 at the position of the first via W1 are etched in step S303.
S304, referring to fig. 11d, performing an ashing process on the photoresist layer 107 to form a second via W2 at the position of the first pit R1; specifically, the photoresist layer 107 may be subjected to an ashing process using a dry etching apparatus to thin the photoresist layer 107 as a whole, thereby forming the second via hole W2 at the position of the first recess R1, and the photoresist layer 107 may be subjected to an ashing process using oxygen during an actual process. Since the passivation layer 106 is not etched through at the position corresponding to the first via hole W1, the driving circuit 102 under the passivation layer 106 is not damaged during the ashing process.
S305, etching the flat layer 103 to form a groove, etching the passivation layer 106 to form a through hole V penetrating through the flat layer 103 and the passivation layer 106 by adopting the same patterning process, and removing the photoresist layer to obtain the structure shown in FIG. 9 c.
In the second implementation, the first via W1 corresponding to the via V to be formed is first formed by exposure in step S302, so that the planarization layer 103 and part of the passivation layer 106 are first etched at the position of the first via W1 in step S303, and then, in step S304, the second via W2 corresponding to the groove U to be formed is formed, so that the via V and the groove U are formed using the same process in step S305, and the via V is formed by using two etching processes, so that the depth of the second pit R2 can be adjusted by adjusting the parameters of the etching process in step S303, thereby indirectly adjusting the depth of the groove U.
In step S203, a pixel defining layer is formed on the planarization layer, and a portion of the pixel defining layer is embedded into the groove on the surface of the planarization layer, so as to increase the bonding force between the pixel defining layer and the planarization layer, a layer of photoresist is formed on the pixel defining layer, and after the photoresist is exposed, the pixel defining layer is etched to obtain a plurality of openings in the pixel defining layer, and the orthogonal projection of the openings in the pixel defining layer on the substrate and the orthogonal projection of the groove on the planarization layer on the substrate are not overlapped with each other, so as to obtain the structure shown in fig. 2.
In a third aspect, based on the same inventive concept, an embodiment of the present invention provides a display device, including the above display panel, where the display device may be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Since the principle of the display device to solve the problem is similar to that of the display panel, the display device can be implemented by the display panel, and repeated descriptions are omitted.
In the display panel, the manufacturing method thereof and the display device provided by the embodiment of the invention, the groove is arranged on one side of the flat layer, which is far away from the substrate, and part of the pixel defining layer is positioned in the groove, so that the contact area between the pixel defining layer and the flat layer is increased, and the pixel defining layer is prevented from falling off.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A display panel, comprising: the pixel structure comprises a substrate, a driving circuit, a flat layer and a pixel definition layer, wherein the driving circuit is positioned on the substrate, the flat layer is positioned on one side, away from the substrate, of the driving circuit, and the pixel definition layer is positioned on one side, away from the substrate, of the flat layer;
the flat layer is provided with a groove on one side facing away from the substrate base plate, and part of the pixel defining layer is positioned in the groove;
the orthographic projection of the groove on the substrate base plate is positioned in the range of the orthographic projection of the pattern of the pixel defining layer on the substrate base plate.
2. The display panel of claim 1, further comprising: a plurality of first electrodes between the planarization layer and the pixel defining layer;
the orthographic projection of the groove on the substrate base plate and the orthographic projection of the first electrode on the substrate base plate are not overlapped.
3. The display panel according to claim 2, wherein an orthographic projection of the groove on the substrate base plate surrounds an orthographic projection of the first electrode on the substrate base plate.
4. A display panel as claimed in claim 3 characterized in that at least two of the recesses are provided around the same first electrode.
5. The display panel according to claim 3, wherein each of the first electrodes is surrounded by the groove.
6. The display panel of claim 2, further comprising: a passivation layer between the driving circuit and the planarization layer, and a plurality of via holes penetrating the planarization layer and the passivation layer;
the first electrode is electrically connected with the driving circuit through the through hole;
the orthographic projection of the through hole on the substrate base plate and the orthographic projection of the groove on the substrate base plate are not overlapped.
7. A method for manufacturing the display panel according to any one of claims 1 to 6, comprising:
forming each film layer in the driving circuit on the substrate;
forming a flat layer on the driving circuit, and patterning the flat layer to form a groove on one side of the flat layer, which is far away from the substrate;
a pattern of pixel definition layers is formed over the planarization layer.
8. The method of manufacturing of claim 7, further comprising, prior to said forming a planar layer over said driver circuit:
forming a passivation layer over the driving circuit;
the patterning the planarization layer includes:
and forming the groove and a through hole penetrating through the flat layer and the passivation layer by adopting the same composition process.
9. The method of manufacturing of claim 7, further comprising, prior to said forming a planar layer over said driver circuit:
forming a passivation layer over the driving circuit;
the patterning the planarization layer includes:
forming a photoresist layer over the planarization layer;
exposing the photoresist layer by using a half-tone mask to form a first via hole and a first pit; the first via hole corresponds to a position of a through hole penetrating through the flat layer and the passivation layer to be formed, and the first pit corresponds to a position of a groove in the flat layer to be formed;
etching the flat layer and the passivation layer to form a second pit penetrating through the flat layer and part of the passivation layer;
ashing the photoresist layer to form a second through hole at the position of the first pit;
and etching the flat layer to form the groove and etching the passivation layer to form a through hole penetrating through the flat layer and the passivation layer by adopting the same composition process.
10. A display device, comprising: a display panel according to any one of claims 1 to 6.
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