CN110828174A - Method for manufacturing electronic component and method for forming conductor layer - Google Patents

Method for manufacturing electronic component and method for forming conductor layer Download PDF

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Publication number
CN110828174A
CN110828174A CN201910729660.6A CN201910729660A CN110828174A CN 110828174 A CN110828174 A CN 110828174A CN 201910729660 A CN201910729660 A CN 201910729660A CN 110828174 A CN110828174 A CN 110828174A
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CN
China
Prior art keywords
paste
face
electrode layer
chip
main surface
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Pending
Application number
CN201910729660.6A
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Chinese (zh)
Inventor
小野寺伸也
田村健寿
森田健
广田大辅
栗本哲
涩江成晃
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TDK Corp
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TDK Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1236—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates
    • H01G4/1245—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates containing also titanates

Abstract

The invention provides a method for manufacturing an electronic component, which prepares a chip provided with an element body. A jig is prepared. The clamp has: a pair of faces having a step, a step face located between the pair of faces. A paste containing a conductive material is applied to the step surface of the jig. The chip is brought close to the jig so that the main surface and the step surface face each other and the end surface and one of the pair of surfaces face each other, and the paste is applied to the main surface, the end surface, and the side surface. The paste provided on the main surface, the end surface, and the side surface is processed to form a conductor layer.

Description

Method for manufacturing electronic component and method for forming conductor layer
Technical Field
The invention relates to a method for manufacturing an electronic component and a method for forming a conductor layer.
Background
The known electronic component includes: an element body having a main surface, an end surface, and a side surface adjacent to each other, and a conductor layer disposed over the main surface, the end surface, and the side surface. As a method for producing such an electronic component, a production method described in japanese unexamined patent application, first publication No. 2004-103927 is known. In this manufacturing method, a rectangular parallelepiped electronic component is prepared, a jig having a tapered space portion extending upward is prepared, a paste containing a conductive material is applied to the inner surface of the tapered space portion, and the corner portion of the end surface on which the external electrode is to be formed is brought into contact with the paste applied to the inner surface of the tapered space portion, so that the paste adheres to the corner portion.
Disclosure of Invention
In the above-mentioned production method, the paste is less likely to wrap around the side face of the element body. Therefore, the paste is difficult to adhere to the side surface, and the conductor layer may be improperly formed on the side surface.
An object of one embodiment of the present invention is to provide a method for manufacturing an electronic component, in which a paste containing a conductive material is appropriately applied to a side surface of an element body, and a conductor layer is appropriately formed.
Another object of the present invention is to provide a method for forming a conductor layer, in which a paste containing a conductive material is appropriately applied to a side surface of an element body to appropriately form a conductor layer.
A method of manufacturing an electronic component according to one embodiment is a method of manufacturing an electronic component including an element body having a principal surface, an end surface, and a side surface adjacent to each other; the conductor layer is disposed over the principal surface, the end surface, and the side surface. One mode of the manufacturing method includes the following processes. A chip having an element body is prepared. A jig is prepared. The clamp has: a pair of faces having a step, a step face located between the pair of faces. A paste containing a conductive material is applied to the stepped surface of a jig. The chip is brought close to the jig in such a manner that the main surface and the step surface face each other and the end surface and one of the pair of surfaces face each other, and the paste is applied to the main surface, the end surface, and the side surface. The paste applied to the main surface, the end surface, and the side surface is processed to form a conductor layer.
In the above-described one aspect, the chip is brought close to the jig so that the main surface and the step surface face each other and the end surface and one of the pair of surfaces face each other, and the paste is applied to the main surface, the end surface, and the side surface. On the step surface, the turndown is sufficient to impart the desired amount of paste compared to the inner side surface of the clip used in the background art described above. Therefore, in the above-described one embodiment, the paste is easily wound around the side face of the element body. As a result, the paste is easily provided with the side surfaces, and the conductor layer is formed not only on the main surface and the end surfaces but also on the side surfaces as appropriate.
The shape and size of the conductive layer can be adjusted according to the shape of the step. Therefore, the conductor layer having a desired shape and size can be easily formed. The shape of the step is, for example, the width of a step surface in the height direction of the step.
In the above aspect, the chip may further include a sintered metal layer disposed on the end face. When the paste is applied to the main surface, the end surface, and the side surface, the paste may be applied to the end surface indirectly by directly applying the paste to the sintered metal layer, and may be applied directly to the main surface and the side surface. In this case, the paste is applied so as to cover the edge of the sintered metal layer. Therefore, the conductor layer is formed so as to cover the edge of the sintered metal layer.
In the above aspect, when viewed from a direction parallel to the main surface and the end surface in a state where the chip is brought close to the jig, a distance from one of the pair of surfaces to an end edge of the sintered metal layer in a direction along the height direction of the step may be smaller than a width of the step surface in the height direction of the step. In this case, the paste is reliably applied so as to cover the edge of the sintered metal layer. Therefore, the conductor layer is formed so as to reliably cover the edge of the sintered metal layer.
In the above aspect, when the paste is applied over the main surface, the end surfaces, and the side surfaces, the chip may be brought close to the jig until the chip abuts against the step surface. In this case, the positional relationship between the jig and the chip when the paste is applied to the chip is not easily changed for each chip. Therefore, the state of application of the paste is not likely to vary from chip to chip. As a result, variations in the shape and size of the conductor layer formed on each chip can be suppressed.
In the above-described one embodiment, the element body may further have another end face opposed to the end face and adjacent to the main face and the side face. The electronic component may further include another conductor layer disposed over the principal surface, the side surface, and the other end surface. The jig may further include: another pair of faces opposite to the pair of faces and having another step, another step face located between the other pair of faces. The paste may be applied to the other step surface of the jig, the paste may be applied to the main surface, the side surface, and the other end surface so that the main surface and the other step surface face each other and the other end surface and one of the other end surfaces face each other, and the paste applied to the main surface, the side surface, and the other end surface may be processed to form the other conductor layer.
In this case, the chip approaches the jig so that the main surface and the other step surface face each other and the other end surface and one of the other opposite surfaces face each other, and the paste is applied to the main surface, the side surfaces, and the other end surface. On the other step surface, a desired amount of paste can be appropriately provided as compared with the inner surface of the jig used in the above-described background art. In the present structure, the paste is also easily wound around the side faces of the element body, and the paste is easily applied to the side faces. Therefore, the other conductor layer is formed not only on the main surface and the other end surface but also on the side surface as appropriate.
The shape and size of the other conductive layer can be adjusted according to the shape of the other step. Therefore, another conductive layer having a desired shape and size can be easily formed. The shape of the other step is, for example, the width of the other step surface in the height direction of the other step.
In the above-described one aspect, the chip may further include another sintered metal layer formed on the other end surface. When the paste is applied to the main surface, the side surface, and the other end surface, the paste may be applied to the other end surface indirectly by directly applying the paste to the other sintered metal layer, and may be applied directly to the main surface and the side surface. In this case, the paste is applied so as to cover the edge of the other sintered metal layer. Therefore, the other conductive layer is formed so as to cover the edge of the other sintered metal layer.
In the above-described one aspect, when viewed from a direction parallel to the main surface and the other end surface in a state where the chip is brought close to the jig, a distance from one surface of the other opposing surface to an end edge of the other sintered metal layer in a direction along the height direction of the other step may be smaller than a width of the other step surface in the height direction of the other step. In this case, the paste is reliably applied so as to cover the edge of the other sintered metal layer. Therefore, the other conductive layer is formed to reliably cover the edge of the other sintered metal layer.
In the above aspect, when the paste is applied over the main surface, the side surface, and the other end surface, the chip may be brought close to the jig until the chip abuts against the other step surface. In this case, the positional relationship between the jig and the chip when the paste is applied to the chip is not easily changed for each chip. Therefore, the state of application of the paste is not likely to vary from chip to chip. As a result, variations in the shape and size of the other conductor layer formed on each chip can be suppressed.
In the above aspect, the distance between one of the pair of surfaces and one of the other surface may be larger than the length of the chip in the direction in which the end surface and the other end surface face each other, and the distance between the other of the pair of surfaces and the other of the other surface may be smaller than the length of the chip. The paste for imparting a stepped surface may be applied to the main surface, the end surface, and the side surface, and the paste for imparting another stepped surface may be applied to the main surface, the side surface, and the other end surface. In this case, the paste is simultaneously given to a portion of the chip near the end face and a portion of the chip near the other end face in one process. Thus, the manufacturing process is simplified.
In the above-described one embodiment, the element body may further have another main surface opposed to the main surface. A holder having an adhesive surface may be prepared, and the adhesive surface may be brought into contact with the other main surface to hold the chip on the holder. In this case, the chip is simply held.
In the above aspect, the paste may be a conductive resin paste containing a conductive material and a resin. In this case, a conductive layer made of a conductive resin can be obtained. That is, the conductor layer constitutes the conductive resin layer. The conductive resin layer suppresses the occurrence of cracks in the element body.
Another method of forming a conductor layer includes the following steps. A chip is prepared, which includes an element body having a main surface, an end surface, and a side surface that are adjacent to each other. A jig is prepared. The clamp has: a pair of faces having a step, a step face located between the pair of faces. A paste containing a conductive material is applied to the step surface of the jig. The chip is brought close to the jig so that the main surface and the step surface face each other and the end surface and one of the pair of surfaces face each other, and the paste is applied to the main surface, the end surface, and the side surface. The paste applied to the main surface, the end surface, and the side surface is processed to form a conductor layer disposed over the main surface, the end surface, and the side surface.
In the above-described another aspect, as described above, a desired amount of paste is appropriately applied to the stepped surface as compared with the inner surface of the jig used in the above-described background art. The paste is easily wound around the side faces of the element body. Therefore, the paste is easily provided with the side surfaces, and the conductor layer is formed not only on the main surface and the end surfaces but also on the side surfaces as appropriate. The shape and size of the conductive layer can be adjusted according to the shape of the step. Therefore, the conductor layer having a desired shape and size can be easily formed. The shape of the step is, for example, the width of a step surface in the height direction of the step.
In the above-described another embodiment, the element body may further have another end face opposed to the end face and adjacent to the main face and the side face. The jig may further include: another pair of faces opposite to the pair of faces and having another step, another step face located between the other pair of faces. The paste may be applied to the other step surface of the jig, or the paste may be applied to the main surface, the side surface, and the other end surface so that the main surface and the other step surface face each other and the other end surface and one surface of the other opposite surface face each other, or the paste applied to the main surface, the side surface, and the other end surface may be processed to form another conductor layer disposed to the main surface, the side surface, and the other end surface.
In this case, as described above, a desired amount of paste can be appropriately applied to the other stepped surface as compared with the inner surface of the jig used in the above-described background art. The paste is easily wound around the side surfaces of the element, and the paste is appropriately applied to the side surfaces. Therefore, the other conductor layer is formed not only on the main surface and the other end surface but also on the side surface as appropriate. The shape and size of the other conductive layer can be adjusted according to the shape of the other step. Therefore, another conductive layer having a desired shape and size can be easily formed. The shape of the other step is, for example, the width of the other step surface in the height direction of the other step.
In the above-described another embodiment, the paste may be a conductive resin paste containing a conductive material and a resin. In this case, a conductive layer made of a conductive resin can be obtained. That is, the conductor layer constitutes the conductive resin layer. The conductive resin layer suppresses the occurrence of cracks in the element body.
The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit of the invention will become apparent to those skilled in the art. The invention has been derived from this detailed description.
Drawings
Fig. 1 is a perspective view of a multilayer capacitor according to an embodiment.
Fig. 2 is a side view of the multilayer capacitor of the present embodiment.
Fig. 3 is a diagram showing a cross-sectional structure of the multilayer capacitor according to the present embodiment.
Fig. 4 is a diagram showing a cross-sectional structure of the multilayer capacitor according to the present embodiment.
Fig. 5 is a diagram showing a cross-sectional structure of the multilayer capacitor according to the present embodiment.
Fig. 6 is a plan view showing the element body, the first electrode layer, and the second electrode layer.
Fig. 7 is a side view showing the element body, the first electrode layer, and the second electrode layer.
Fig. 8 is an end view showing the element body, the first electrode layer, and the second electrode layer.
Fig. 9 is a schematic diagram showing a manufacturing process of the multilayer capacitor according to the present embodiment.
Fig. 10 is a schematic diagram showing a manufacturing process of the multilayer capacitor according to the present embodiment.
Fig. 11 is a schematic diagram showing a manufacturing process of the multilayer capacitor according to the present embodiment.
Fig. 12 is a schematic diagram showing a manufacturing process of the multilayer capacitor according to the present embodiment.
Fig. 13 is a schematic diagram showing a manufacturing process of the multilayer capacitor according to the present embodiment.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the drawings. In the description, the same elements or elements having the same function are denoted by the same reference numerals, and redundant description thereof is omitted.
First, the structure of the multilayer capacitor C1 according to the present embodiment will be described with reference to fig. 1 to 8. Fig. 1 is a perspective view of a multilayer capacitor according to the present embodiment. Fig. 2 is a side view of the multilayer capacitor of the present embodiment. Fig. 3, 4, and 5 are views showing cross-sectional structures of the multilayer capacitor according to the present embodiment. Fig. 6 is a plan view showing the element body, the first electrode layer, and the second electrode layer. Fig. 7 is a side view showing the element body, the first electrode layer, and the second electrode layer. Fig. 8 is an end view showing the element body, the first electrode layer, and the second electrode layer. In the present embodiment, the electronic component is, for example, a multilayer capacitor C1.
As shown in fig. 1, the multilayer capacitor C1 includes an element body 3 having a rectangular parallelepiped shape and a pair of external electrodes 5. The pair of external electrodes 5 are disposed on the outer surface of the element body 3. The pair of external electrodes 5 are spaced apart from each other. The rectangular parallelepiped shape includes a rectangular parallelepiped shape in which corners and ridge portions are chamfered, and a rectangular parallelepiped shape in which corners and ridge portions are rounded.
The element body 3 has a pair of rectangular main surfaces 3a and 3b facing each other, a pair of rectangular side surfaces 3c facing each other, and a pair of end surfaces 3e facing each other. The direction in which the pair of main surfaces 3a and 3b face each other is the first direction D1. The direction in which the pair of side faces 3c oppose each other is the second direction D2. The opposing direction of the pair of end faces 3e is the third direction D3. The multilayer capacitor C1 is solder-mounted to the electronic device. The electronic device includes, for example, a circuit substrate or an electronic component. In the multilayer capacitor C1, the main surface 3a faces the electronic device. The main surface 3a is arranged to constitute a mounting surface. The principal surface 3a is a mounting surface.
The first direction D1 is a direction perpendicular to the main surfaces 3a and 3b, and is perpendicular to the second direction D2. The third direction D3 is a direction parallel to the main surfaces 3a and 3b and the side surfaces 3c, and is orthogonal to the first direction D1 and the second direction D2. The second direction D2 is a direction orthogonal to the side surfaces 3c, and the third direction D3 is a direction orthogonal to the end surfaces 3 e. In the present embodiment, the length of the element body 3 in the third direction D3 is greater than the length of the element body 3 in the first direction D1 and greater than the length of the element body 3 in the second direction D2. The third direction D3 is the longitudinal direction of the element body 3.
The pair of side surfaces 3c extend in the first direction D1 so as to connect the pair of main surfaces 3a and 3 b. The pair of side surfaces 3c also extends in the third direction D3. The pair of end faces 3e extend in the first direction D1 so as to connect the pair of main faces 3a and 3 b. The pair of end faces 3e also extend in the second direction D2.
The element body 3 has a pair of ridge line portions 3g, a pair of ridge line portions 3h, four ridge line portions 3i, a pair of ridge line portions 3j, and a pair of ridge line portions 3 k. The ridge portion 3g is located between the end face 3e and the main face 3 a. The ridge portion 3h is located between the end face 3e and the main face 3 b. The ridge line portion 3i is located between the end face 3e and the side face 3 c. The ridge line portion 3j is located between the main surface 3a and the side surface 3 c. The ridge line portion 3k is located between the main surface 3b and the side surface 3 c. In the present embodiment, the ridge portions 3g, 3h, 3i, 3j, 3k are rounded in a curved manner. The element body 3 is subjected to so-called reverse R-corner processing.
The end face 3e and the main face 3a are indirectly adjacent to each other via the ridge portion 3 g. The end face 3e and the main face 3b are indirectly adjacent to each other via the ridge portion 3 h. The end face 3e and the side face 3c are indirectly adjacent to each other via the ridge line portion 3 i. The main surface 3a and the side surface 3c are indirectly adjacent to each other via the ridge portion 3 j. The main surface 3b and the side surface 3c are indirectly adjacent to each other via the ridge portion 3 k.
The element body 3 is formed by laminating a plurality of dielectric layers in the second direction D2. The element body 3 has a plurality of dielectric layers laminated together. In the element body 3, the stacking direction of the plurality of dielectric layers coincides with the first direction D1. Each dielectric layer is composed of, for example, a sintered body of a ceramic green sheet containing a dielectric material. Dielectric materials including, for example, BaTiO3Series, Ba (Ti, Zr) O3Is of (Ba, Ca) TiO3And dielectric ceramics of the series. In the actual element body 3, the dielectric layers are integrated to such an extent that the boundary between the dielectric layers cannot be recognized. In the element body 3, the stacking direction of the plurality of dielectric layers may be aligned with the first direction D1.
As shown in fig. 3, 4, and 5, the multilayer capacitor C1 includes a plurality of internal electrodes 7 and a plurality of internal electrodes 9. Each of the inner electrodes 7 and 9 is an inner conductor disposed in the element body 3. The internal electrodes 7 and 9 are made of a conductive material that is generally used as an internal electrode of a laminated electronic component. The conductive material contains, for example, a base metal. The conductive material contains, for example, Ni or Cu. The internal electrodes 7 and 9 are formed as a sintered body of a conductive paste containing the conductive material. In the present embodiment, the internal electrodes 7 and 9 are made of Ni.
The internal electrodes 7 and the internal electrodes 9 are disposed at different positions (layers) in the second direction D2. In the element body 3, the internal electrodes 7 and the internal electrodes 9 are alternately arranged so as to face each other with a gap therebetween in the second direction D2. The polarities of the internal electrodes 7 and 9 are different from each other. When the stacking direction of the plurality of dielectric layers is the first direction D1, the internal electrodes 7 and the internal electrodes 9 are disposed at different positions (layers) in the first direction D1. The internal electrodes 7 and 9 have one ends exposed at the corresponding end surfaces 3 e.
The plurality of internal electrodes 7 and the plurality of internal electrodes 9 are alternately arranged in the second direction D2. The inner electrodes 7 and 9 are located in planes substantially perpendicular to the main surfaces 3a and 3 b. The internal electrodes 7 and 9 are opposed to each other in the second direction D2. The direction in which the internal electrodes 7 and 9 face each other (the second direction D2) is orthogonal to the direction perpendicular to the main surfaces 3a and 3b (the first direction D1). As shown in fig. 8, the interval Gc in the second direction D2 between the side surface 3c and the internal electrodes 7 and 9 closest to the side surface 3c is greater than the interval Ga in the first direction D1 between the main surface 3a and the internal electrodes 7 and 9, and is greater than the interval Gb in the first direction D1 between the main surface 3b and the internal electrodes 7 and 9.
As shown in fig. 2, the external electrodes 5 are disposed at both ends of the element body 3 in the third direction D3, respectively. Each external electrode 5 is disposed on the corresponding end face 3e side of the element body 3. As shown in fig. 3, 4, and 5, the external electrode 5 includes a plurality of electrode portions 5a, 5b, 5c, and 5 e. The electrode portion 5a is disposed on the principal surface 3a and on the ridge portion 3 g. The electrode portion 5b is disposed on the ridge portion 3 h. The electrode portions 5c are disposed on the side surfaces 3c and the ridge portions 3 i. The electrode portion 5e is disposed on the corresponding end face 3 e. The external electrode 5 also has an electrode portion disposed on the ridge line portion 3 j.
The external electrodes 5 are formed on four surfaces, i.e., one main surface 3a, one end surface 3e, and a pair of side surfaces 3c, and on the ridge line portions 3g, 3h, 3i, and 3 j. The electrode portions 5a, 5b, 5c, 5e adjacent to each other are connected to each other and electrically connected. In the present embodiment, the external electrode 5 is intentionally not formed on the main surface 3 b. The electrode portion 5e covers all of the ends exposed at the end faces 3e of the corresponding internal electrodes 7 and 9. The electrode portion 5e is directly connected to the corresponding inner electrodes 7 and 9. The external electrodes 5 are electrically connected to the corresponding internal electrodes 7, 9.
As shown in fig. 3, 4, and 5, the external electrode 5 includes a first electrode layer E1, a second electrode layer E2, a third electrode layer E3, and a fourth electrode layer E4. The fourth electrode layer E4 constitutes the outermost layer of the external electrode 5. Each of the electrode portions 5a, 5c, and 5E includes a first electrode layer E1, a second electrode layer E2, a third electrode layer E3, and a fourth electrode layer E4. The electrode portion 5b includes a first electrode layer E1, a third electrode layer E3, and a fourth electrode layer E4.
The first electrode layer E1 of the electrode portion 5a is disposed on the ridge portion 3g and not on the principal surface 3 a. The first electrode layer E1 of the electrode portion 5a is in contact with the entire ridge portion 3 g. The main surface 3a is not covered with the first electrode layer E1, but is exposed from the first electrode layer E1. The second electrode layer E2 of the electrode portion 5a is disposed on the first electrode layer E1 and on the main surface 3a, and the entire first electrode layer E1 is covered with the second electrode layer E2. In the electrode portion 5a, the second electrode layer E2 is in contact with a part of the main surface 3a (a part of the main surface 3a near the end surface 3E) and the whole of the first electrode layer E1. The electrode portion 5a has a four-layer structure on the ridge portion 3g and a three-layer structure on the main surface 3 a.
The second electrode layer E2 of the electrode portion 5a is formed so as to cover the entire ridge portion 3g and a part of the main surface 3a (a part of the main surface 3a near the end face 3E). The second electrode layer E2 of the electrode portion 5a indirectly covers the entire ridge portion 3g so that the first electrode layer E1 is positioned between the second electrode layer E2 and the ridge portion 3 g. The second electrode layer E2 of the electrode portion 5a directly covers a part of the principal surface 3 a. The second electrode layer E2 of the electrode portion 5a directly covers the entire first electrode layer E1 formed in the ridge portion 3 g.
As described above, when a certain element is described as covering another element, the certain element may directly cover the other element or indirectly cover the other element. When a certain element indirectly overlaps with another element, the element is present between the certain element and the other element. When a certain element is described as directly covering another element, the element does not exist between the certain element and the other element.
The first electrode layer E1 of the electrode portion 5b is disposed on the ridge portion 3h, but not on the main surface 3 b. The first electrode layer E1 of the electrode portion 5b is in contact with the entire ridge portion 3 h. The main surface 3b is not covered with the first electrode layer E1 and is exposed from the first electrode layer E1. The electrode portion 5b does not have the second electrode layer E2. The main surface 3b is not covered with the second electrode layer E2 but is exposed from the second electrode layer E2. The second electrode layer E2 is not formed on the main surface 3 b. The electrode portion 5b has a three-layer structure.
The first electrode layer E1 of the electrode portion 5c is disposed on the ridge line portion 3i, but not on the side surface 3 c. The first electrode layer E1 of the electrode portion 5c is in contact with the entire ridge portion 3 i. The side surface 3c is not covered with the first electrode layer E1 and is exposed from the first electrode layer E1. The second electrode layer E2 of the electrode portion 5c is disposed on the first electrode layer E1 and on the side surface 3c, and a part of the first electrode layer E1 is covered with the second electrode layer E2. In the electrode portion 5c, the second electrode layer E2 is in contact with a part of the side surface 3c and a part of the first electrode layer E1. The second electrode layer E2 of the electrode portion 5c has a portion located on the side surface 3 c.
The second electrode layer E2 of the electrode portion 5c is formed so as to cover a part of the ridge portion 3i (a part of the ridge portion 3i near the main surface 3 a) and a part of the side surface 3c (a corner region of the side surface 3c near the main surface 3a and the end surface 3E). The second electrode layer E2 of the electrode portion 5c indirectly covers a part of the ridge portion 3i so that the first electrode layer E1 is positioned between the second electrode layer E2 and the ridge portion 3 i. The second electrode layer E2 of the electrode portion 5c directly covers a part of the side surface 3 c. The second electrode layer E2 of the electrode portion 5c directly covers a part of the first electrode layer E1 formed in the ridge line portion 3 i.
The electrode portion 5c has a plurality of regions 5c1, 5c 2. Region 5c2Is located in the ratio area 5c1Closer to the main surface 3 a. In the present embodiment, the electrode portion 5c has only two regions 5c1, 5c 2. Region 5c1Has a first electrode layer E1, a third electrode layer E3, and a fourth electrode layer E4. Region 5c1The second electrode layer E2 is not present. Region 5c1Has a three-layer construction. Region 5c2Has a first electrode layer E1, a second electrode layer E2, a third electrode layer E3, and a fourth electrode layer E4. Region 5c2The ridge portion 3i has a four-layer structure, and the side surface 3c has a three-layer structure. Region 5c1The first electrode layer E1 is exposed from the second electrode layer E2. Region 5c2Is a region where the first electrode layer E1 is covered with the second electrode layer E2.
The first electrode layer E1 of the electrode portion 5E is disposed on the end face 3E, and the entire end face 3E is covered with the first electrode layer E1. The first electrode layer E1 of the electrode portion 5E is in contact with the entire end face 3E. The second electrode layer E2 of the electrode portion 5E is disposed on the first electrode layer E1, and a part of the first electrode layer E1 is covered with the second electrode layer E2. In the electrode portion 5E, the second electrode layer E2 is in contact with a part of the first electrode layer E1. The second electrode layer E2 of the electrode portion 5E is formed so as to cover a part of the end face 3E (a part of the end face 3E close to the main surface 3 a). The second electrode layer E2 of the electrode portion 5E indirectly covers a part of the end face 3E in such a manner that the first electrode layer E1 is located between the second electrode layer E2 and the end face 3E. The second electrode layer E2 of the electrode portion 5E directly covers a part of the first electrode layer E1 formed on the end face 3E. In the electrode portion 5E, the first electrode layer E1 is disposed on the end face 3E so as to be connected to one end of the corresponding internal electrode 7, 9.
The electrode portion 5e has a plurality of regions 5e1、5e2. Region 5e2Is located in a ratio area 5e1Closer to the main surface 3 a. In the present embodiment, the electrode portion 5e has only two regions 5e1、5e2. Region 5e1Has a first electrode layer E1, a third electrode layer E3, and a fourth electrode layer E4. Region 5e1The second electrode layer E2 is not present. Region 5e1Has a three-layer construction. Region 5e2Has a first electrode layer E1, a second electrode layer E2, a third electrode layer E3, and a fourth electrode layer E4. Region 5e2Has a four-layer construction. Region 5e1The first electrode layer E1 is exposed from the second electrode layer E2. Region 5e2Is a region where the first electrode layer E1 is covered with the second electrode layer E2.
The first electrode layer E1 is formed by sintering the electroconductive paste applied to the surface of the element body 3. The first electrode layer E1 is formed so as to cover the end face 3E and the ridge portions 3g, 3h, and 3 i. The first electrode layer E1 is formed by sintering a metal component (metal powder) contained in the conductive paste. The first electrode layer E1 is a sintered metal layer. The first electrode layer E1 is a sintered metal layer formed on the element body 3. The first electrode layer E1 is intentionally not formed on the pair of main surfaces 3a, 3b and the pair of side surfaces 3 c. For example, the first electrode layer E1 may be unintentionally formed on the main surfaces 3a and 3b and the side surface 3c due to manufacturing errors or the like.
In this embodiment, the first electrode layer E1 is a sintered metal layer made of Cu. The first electrode layer E1 may be a sintered metal layer made of Ni. Thus, the first electrode layer E1 contains a base metal. The conductive paste contains, for example, a powder composed of Cu or Ni, a glass component, an organic binder, and an organic solvent.
The second electrode layer E2 is formed by curing the conductive resin paste applied to the first electrode layer E1, the main surface 3a, and the pair of side surfaces 3 c. The second electrode layer E2 is formed on the first electrode layer E1 and on the element body 3. In this embodiment mode, the second electrode layer E2 covers a part of the first electrode layer E1 (the electrode portion 5a, the region 5c of the electrode portion 5 c)2And an area 5e of the electrode portion 5e2The corresponding region). The second electrode layer E2 directly covers a part of the ridge line portion 3j (a part of the ridge line portion 3j near the end face 3E). The second electrode layer E2 is in contact with a part of the ridge line portion 3 j. The first electrode layer E1 is a base metal layer for forming the second electrode layer E2. The second electrode layer E2 is a conductive resin layer formed on the first electrode layer E1. The second electrode layer E2 is a conductor layer.
The conductive resin paste contains a resin, a conductive material, and a solvent. The resin is, for example, a thermosetting resin. The conductive material is, for example, metal powder. The metal powder is, for example, Ag powder or Cu powder. The thermosetting resin is, for example, a phenol resin, an acrylic resin, a silicone resin, an epoxy resin, or a polyimide resin.
The third electrode layer E3 is formed over the second electrode layer E2 and over the first electrode layer E1 (the portion exposed from the second electrode layer E2) by an electroplating method. The third electrode layer E3 directly covers the second electrode layer E2 and the portion of the first electrode layer E1 exposed from the second electrode layer E2. In this embodiment mode, the third electrode layer E3 is formed on the first electrode layer E1 and on the second electrode layer E2 by Ni plating. The third electrode layer E3 is a Ni-plated layer. The third electrode layer E3 may be a Sn plated layer, a Cu plated layer, or an Au plated layer. The third electrode layer E3 contains Ni, Sn, Cu, or Au.
The fourth electrode layer E4 is formed on the third electrode layer E3 by an electroplating method. The fourth electrode layer E4 indirectly covers the second electrode layer E2 and the portion of the first electrode layer E1 exposed from the second electrode layer E2, so that the third electrode layer E3 is located between the fourth electrode layer E4 and the portions of the second electrode layer E2 and the first electrode layer E1 exposed from the second electrode layer E2. In this embodiment mode, the fourth electrode layer E4 is formed on the third electrode layer E3 by Sn plating. The fourth electrode layer E4 is a Sn plated layer. The fourth electrode layer E4 may also be a Cu-plated layer or an Au-plated layer. The fourth electrode layer E4 contains Sn, Cu, or Au. The third electrode layer E3 and the fourth electrode layer E4 constitute a plating layer formed on the second electrode layer E2. In this embodiment mode, the plating layer formed on the second electrode layer E2 has a two-layer structure.
The first electrode layers E1 included in the electrode portions 5a, 5b, 5c, and 5E are integrally formed. The second electrode layer E2 included in each of the electrode portions 5a, 5c, and 5E is integrally formed. The third electrode layers E3 included in the electrode portions 5a, 5b, 5c, and 5E are integrally formed. The fourth electrode layer E4 included in each of the electrode portions 5a, 5b, 5c, and 5E is integrally formed.
The first electrode layer E1 (the first electrode layer E1 of the electrode portion 5E) is formed on the end face 3E so as to be connected to the corresponding internal electrodes 7 and 9. The first electrode layer E1 covers the entire end face 3E, the entire ridge portion 3g, the entire ridge portion 3h, and the entire ridge portion 3 i. The second electrode layer E2 (the second electrode layer E2 of the electrode portions 5a, 5c, 5E) continuously covers a part of the principal surface 3a, a part of the end surface 3E, and a part of each of the pair of side surfaces 3 c. The second electrode layer E2 (the second electrode layer E2 of the electrode portions 5a, 5c, 5E) covers the entire ridge portion 3g, a part of the ridge portion 3i, and a part of the ridge portion 3 j. The second electrode layer E2 has portions corresponding to a part of the principal surface 3a, a part of the end surface 3E, parts of the pair of side surfaces 3c, the entirety of the ridge portion 3g, a part of the ridge portion 3i, and a part of the ridge portion 3 j. The first electrode layer E1 (the first electrode layer E1 of the electrode portion 5E) is directly connected to the corresponding internal electrodes 7, 9.
The first electrode layer E1 (the first electrode layer E1 of the electrode portions 5a, 5b, 5c, 5E) has a region covered with the second electrode layer E2 (the second electrode layer E2 of the electrode portions 5a, 5c, 5E) and a region not covered with the second electrode layer E2 (the second electrode layer E2 of the electrode portions 5a, 5c, 5E). The third electrode layer E3 and the fourth electrode layer E4 cover the region of the first electrode layer E1 not covered by the second electrode layer E2 and the second electrode layer E2.
As shown in fig. 6, when viewed from the first direction D1, the entire first electrode layer E1 (the first electrode layer E1 of the electrode portion 5a) is covered with the second electrode layer E2. When viewed from the first direction D1, the first electrode layer E1 (the first electrode layer E1 of the electrode portion 5a) is not exposed from the second electrode layer E2.
As shown in fig. 7, when viewed from the second direction D2, an end region (region 5 c) of the first electrode layer E1 near the main surface 3a2The first electrode layer E1) is covered with the second electrode layer E2, and the end edge E2E of the second electrode layer E2 intersects the end edge E1E of the first electrode layer E1. An end region (region 5 c) of the first electrode layer E1 near the main surface 3b when viewed from the second direction D21The first electrode layer E1 provided) is exposed from the second electrode layer E2. When viewed from the second direction D2, the area of the second electrode layer E2 located on the side surface 3c and the ridge portion 3i is larger than the area of the first electrode layer E1 located on the ridge portion 3 i. The second electrode layer E2 located on the side face 3c is opposed to the internal electrodes 7, 9 having a different polarity from the second electrode layer E2 in the second direction D2.
As shown in fig. 8, when viewed from the third direction D3, an end region (region 5E) of the first electrode layer E1 near the main surface 3a2Having the first electrode layer E1) is covered by the second electrode layer E2, and the end edge E2E of the second electrode layer E2 is located on the first electrode layer E1. An end region (region 5E) of the first electrode layer E1 close to the main surface 3b when viewed from the third direction D31The first electrode layer E1 provided) is exposed from the second electrode layer E2. When viewed from the third direction D3, the area of the second electrode layer E2 located on the end face 3E and the ridge portion 3g is smaller than the area of the first electrode layer E1 located on the end face 3E and the ridge portion 3 g. When viewed from the third direction D3, the height H2 of the second electrode layer E2 is half or less of the height H1 of the element body 3.
As shown in fig. 8, when viewed from the third direction D3, one end of each of the internal electrodes 7 and 9 has a region 7a or 9a overlapping with the second electrode layer E2 and a region 7b or 9b not overlapping with the second electrode layer E2. The regions 7a and 9a are located closer to the main surface 3a than the regions 7b and 9b in the first direction D1. Region 5e2The first electrode layer E1 is connected to the corresponding regions 7a and 9 a. Region 5e1The first electrode layer E1 is connected to the corresponding regions 7b and 9 b. When viewed from the third direction D3, the end edge E2E of the second electrode layer E2 intersects with one end of each of the internal electrodes 7 and 9. The length L in the first direction D1 of the regions 7a, 9aiaThan the length L in the first direction D1 of the regions 7b, 9bibIs small.
In the present embodiment, the second electrode layer E2 continuously covers only a part of the principal surface 3a, only a part of the end surface 3E, and only a part of each of the pair of side surfaces 3 c. The second electrode layer E2 covers the entire ridge portion 3g, only a part of the ridge portion 3i, and only a part of the ridge portion 3 j. A part of the first electrode layer E1 covering the ridge line part 3i (for example, the region 5 c)1The first electrode layer E1 provided) is exposed from the second electrode layer E2. The first electrode layer E1 is disposed on the end face 3E so as to be connected to the corresponding regions 7a and 9 a. In the present embodiment, the first electrode layer E1 is also disposed on the end face 3E so as to be connected to the corresponding regions 7b and 9 b.
As shown in fig. 2, the area 5c in the third direction D32The width of (a) becomes smaller as it becomes farther from the main surface 3a (electrode portion 5 a). Region 5c in first direction D12The width of (b) decreases as it goes away from the end face 3e (electrode portion 5 e). In the present embodiment, the region 5c is viewed from the second direction D22The end edge of (a) is substantially arc-shaped. When viewed from the second direction D2, the region 5c2Is substantially fan-shaped. In the present embodiment, as shown in fig. 7, the width of the second electrode layer E2 when viewed from the second direction D2 decreases as it goes away from the main surface 3 a. The length of the second electrode layer E2 in the first direction D1 is smaller as viewed from the second direction D2 as farther from the end face 3E in the third direction D3. The length of the portion of the second electrode layer E2 located on the side surface 3c in the first direction D1 is smaller as viewed in the second direction D2 as being farther from the end of the element body 3 in the third direction D3. As shown in fig. 7, the end edge E2E of the second electrode layer E2 has a substantially arc shape.
When the multilayer capacitor C1 is mounted by soldering to an electronic device, an external force acting on the multilayer capacitor C1 from the electronic device may act as a stress on the element body 3. External force acts on the element body 3 from a fillet (filet) formed at the time of solder mounting through the external electrode 5. In this case, cracks may occur in the element body 3. The external force tends to act on the element body 3 from the region of the end face 3e close to the main face 3 a. In the multilayer capacitor C1, the second electrode layer E2 (the second electrode layer E2 of the electrode portion 5E) covers a portion of the end face 3E close to the principal surface 3 a. Therefore, an external force acting on the multilayer capacitor C1 from the electronic device is less likely to act on the element body 3. As a result, the multilayer capacitor C1 suppresses the occurrence of cracks in the element assembly 3.
The region between the element body 3 and the second electrode layer E2 may serve as a path for moisture to permeate. When moisture penetrates from the region between the element body 3 and the second electrode layer E2, the durability of the multilayer capacitor C1 decreases. In the multilayer capacitor C1, since the second electrode layer E2 (the second electrode layer E2 of the electrode portion 5E) covers a part of the end face 3E close to the principal surface 3a, the end face 3E has a region not covered with the second electrode layer E2 when viewed from the third direction D3. Therefore, in the multilayer capacitor C1, the second electrode layer E2 has less moisture penetration route than the structure formed so as to cover the entire end face 3E. As a result, the moisture resistance reliability of the multilayer capacitor C1 is improved.
In the multilayer capacitor C1, the principal surface 3a is a mount surface, and the plurality of inner electrodes 7 and 9 face each other in the second direction D2. Therefore, in the multilayer capacitor C1, the current path formed in each of the internal electrodes 7 and 9 is short. As a result, the multilayer capacitor C1 has a low ESL.
In the multilayer capacitor C1, one end of each of the internal electrodes 7 and 9 has the regions 7a and 9a and the regions 7b and 9b when viewed from the third direction D3. In this case, the multilayer capacitor C1 has a small path for moisture to penetrate. Therefore, the moisture resistance reliability of the multilayer capacitor C1 is reliably improved.
In the multilayer capacitor C1, the length L in the first direction D1 of the regions 7a, 9aiaThan the length L in the first direction D1 of the regions 7b, 9bibIs small. In this case, the path of moisture penetration is further reduced. Therefore, the moisture resistance reliability of the multilayer capacitor C1 is further improved.
In the multilayer capacitor C1, the external electrode 5 has a first electrode layer E1 formed on the end face 3E so as to be connected to the regions 7b and 9 b. In this case, the external electrode 5 (first electrode layer E1) and the internal electrodes 7 and 9 corresponding to each other are in good contact. Therefore, the external electrodes 5 and the internal electrodes 7 and 9 corresponding to each other are reliably electrically connected. The resistance of the second electrode layer E2 is greater than that of the first electrode layer E1. In the case where the external electrode 5 has the first electrode layer E1 connected to the internal electrodes 7 and 9, the first electrode layer E1 is electrically connected to the electronic device without passing through the second electrode layer E2. Therefore, in the case where the external electrode 5 has the second electrode layer E2, the multilayer capacitor C1 suppresses an increase in ESR.
In the multilayer capacitor C1, the regions 7b of all the internal electrodes 7 and the regions 9b of all the internal electrodes 9 are connected to the corresponding first electrode layers E1. Therefore, the multilayer capacitor C1 further suppresses an increase in ESR.
In the multilayer capacitor C1, the external electrode 5 includes the third electrode layer E3 and the fourth electrode layer E4. The third electrode layer E3 and the fourth electrode layer E4 cover the second electrode layer E2 and the first electrode layer E1 (the region exposed from the second electrode layer E2). Since the external electrode 5 has the third electrode layer E3 and the fourth electrode layer E4, the multilayer capacitor C1 can be soldered to an electronic device. Since the first electrode layer E1 is electrically connected to the electronic device through the third electrode layer E3 and the fourth electrode layer E4, the multilayer capacitor C1 further suppresses an increase in ESR.
In the multilayer capacitor C1, the end edge E2E of the second electrode layer E2 intersects with one end of each of the internal electrodes 7 and 9 when viewed from the third direction D3. In this case, the moisture penetration path is also small. Therefore, the moisture resistance reliability of the multilayer capacitor C1 is reliably improved.
In the multilayer capacitor C1, the second electrode layer E2 also covers a portion of the principal surface 3a near the end face 3E. An external force applied from the electronic device to the multilayer capacitor C1 may act on the element body 3 from a region near the end face 3e of the main surface 3 a. Therefore, the multilayer capacitor C1 reliably suppresses the occurrence of cracks in the element body.
In the multilayer capacitor C1, the second electrode layer E2 also covers a portion of the side surface 3C near the end surface 3E. An external force applied from the electronic device to the multilayer capacitor C1 may act on the element body 3 from a region of the side surface 3C close to the end surface 3 e. Therefore, the multilayer capacitor C1 reliably suppresses the occurrence of cracks in the element body.
In the multilayer capacitor C1, the second electrode layer E2 located on the side face 3C is opposed to the internal electrodes 7, 9 having a different polarity from the second electrode layer E2 in the second direction D2. Therefore, a capacitance component is formed between the second electrode layer E2 located on the side surface 3c and the internal electrodes 7 and 9 opposed to the second electrode layer E2. As a result, the capacitance of the multilayer capacitor C1 increases.
In the multilayer capacitor C1, the second electrode layer E2 is not formed on the main surface 3 b. In the case where the multilayer capacitor C1 is mounted on the electronic apparatus with the principal surface 3a as the mounting surface, the principal surface 3b needs to be picked up by a nozzle of a mounter. In the multilayer capacitor C1, the shape of the external electrode 5 is different between the principal surface 3a and the principal surface 3b, and therefore the principal surface 3a and the principal surface 3b can be easily distinguished from each other. Therefore, the multilayer capacitor C1 is reliably mounted on the electronic device.
In the multilayer capacitor C1, the interval Gc is larger than the intervals Ga and Gb. Therefore, in the multilayer capacitor C1, even when cracks are generated from the side face 3C of the element body 3, the cracks hardly reach the internal electrodes 7 and 9.
Next, a process for manufacturing the multilayer capacitor C1 according to the present embodiment will be described with reference to fig. 9 to 13. Fig. 9 to 13 are schematic views showing a manufacturing process of the multilayer capacitor according to the present embodiment. The manufacturing process of this embodiment mode includes a process of forming the second electrode layer E2, which is a conductor layer.
First, a ceramic paste for forming dielectric layers and an internal electrode paste (conductive paste) for forming the internal electrodes 7 and 9 are prepared.
The ceramic paste contains, for example, the above-described raw material powder of the dielectric material and an organic vehicle (vehicle). The organic vehicle contains a binder and a solvent. The solvent is, for example, an organic solvent. The ceramic paste may contain a dispersant, a plasticizer, a dielectric, a glass frit, or an insulator. Ceramic pastes are known in the art and further detailed description is omitted.
The internal electrode paste contains, for example, the above-described powder of the conductive material and an organic vehicle. The powder of the conductive material of the internal electrode paste is, for example, metal powder. The powder is, for example, spherical or flaky. The organic vehicle contains a binder and a solvent. The solvent is, for example, an organic solvent. The internal electrode paste may also contain an inorganic compound. The internal electrode paste may also contain a plasticizer. The internal electrode paste is known in the art and further detailed description is omitted.
Next, a ceramic green sheet is formed using the above ceramic paste. In this process, for example, after the ceramic paste is applied to the carrier sheet in a sheet form, the ceramic paste in a sheet form is dried. Thereby, a ceramic green sheet was obtained. The carrier sheet is made of, for example, PET (polyethylene terephthalate). The ceramic paste is applied, for example, by knife coating.
Next, a plurality of internal electrode patterns are formed on the ceramic green sheets using the internal electrode paste. In this process, for example, an internal electrode paste is applied to the ceramic green sheet and patterned, and then the internal electrode paste is dried. Thereby, a plurality of internal electrode patterns are obtained. The internal electrode paste is applied by, for example, screen printing.
Next, a green laminate is formed from the ceramic green sheets on which the internal electrode patterns are formed. In this process, for example, after aligning the ceramic green sheets in a predetermined size, a predetermined number of ceramic green sheets are stacked. Thereafter, the stacked ceramic green sheets are pressed, for example, from the stacking direction. Thereby, a green laminate was obtained.
Next, a plurality of green chips are obtained from the green laminate. In this process, the green laminated body is cut into chip shapes by, for example, a dicing machine. Thereby, a plurality of green chips having a predetermined size are obtained.
Next, after the binder is removed from the green chip, the green chip is fired. The element 3 is obtained by this firing. Thereafter, the element body 3 is subjected to chamfering. The chamfering is, for example, barrel grinding. Removal of the binder, for example by use of a reducing atmosphereThe green chip is then heated. Reducing atmospheres, e.g. from air, or N2And H2The mixed gas of (1). Firing is performed, for example, by heating the green chip from which the binder is removed, for example, in a reducing atmosphere. The removal and firing of the binder are well known in the art, and further detailed description is omitted.
Next, the first electrode layer E1 is formed on the element body 3. In this process, as described above, the electroconductive paste is applied to a predetermined region on the surface of the element body 3, and the applied electroconductive paste is sintered to the element body 3 by heat treatment. Thereby, the first electrode layer E1 was obtained. The conductive paste is applied by, for example, a dipping method, a printing method, or a transfer method. The heat treatment of the electroconductive paste is known in the art, and further detailed description is omitted. In the present embodiment, the end face 3e and the ridge portions 3g, 3h, and 3i are provided with the conductive paste. The first electrode layer E1 can be formed by Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), for example.
Through the above procedure, the chip 11 including the element body 3 and the first electrode layer E1 is prepared (see fig. 11 and 12).
Next, a second electrode layer E2 is formed on the chip 11. The present process includes the following processes. This process includes a process of applying a paste to the chip 11 and processing the applied paste. The paste is, for example, a conductive resin paste 17.
First, as shown in fig. 9, the jig 13 is prepared. The jig 13 is made of, for example, a metal material or a non-metal material. The non-metallic material is, for example, ceramic, carbide, resin, or rubber.
A groove 15 is formed in the jig 13. The groove 15 is defined by a plurality of surfaces 13a, 13b, 13c, 13d, 13e, 13f, 13 g. In the present embodiment, the seven surfaces 13a, 13b, 13c, 13d, 13e, 13f, and 13g divide the surface. That is, the jig 13 includes seven surfaces 13a, 13b, 13c, 13d, 13e, 13f, 13 g. The face 13a and the face 13b have a step, and the face 13c is located between the face 13a and the face 13 b. The face 13c constitutes a stepped face. The face 13d and the face 13e have a step, and the face 13f is located between the face 13d and the face 13 e. The face 13f constitutes a step face. The surface 13g is located between the surfaces 13b and 13e, and constitutes the bottom surface of the groove 15.
For example, in the case where the surfaces 13a, 13b constitute one pair of surfaces, the surfaces 13d, 13e constitute the other pair of surfaces. For example, in the case where the face 13a constitutes one face of a pair of faces, the face 13b constitutes the other face. For example, in the case where the face 13d constitutes one face of a pair of faces, the face 13e constitutes the other face. For example, when the steps of the surface 13a and the surface 13b constitute one step, the steps of the surface 13d and the surface 13e constitute the other step. For example, when the surface 13c constitutes one stepped surface, the surface 13f constitutes the other stepped surface.
The surface 13c is orthogonal to the surfaces 13a and 13 b. The surface 13f is orthogonal to the surfaces 13d and 13 e. The surface 13g is orthogonal to the surfaces 13b and 13 e. The faces 13a, 13b, 13d, 13e are parallel. The faces 13c, 13f, 13g are parallel. The faces 13a and 13d are opposed to each other. The face 13b and the face 13e are opposed to each other. The height positions of the surface 13c and the surface 13f in the depth direction of the groove 15 are the same. The surface 13c and the surface 13f are included in the same imaginary plane.
The distance between the surfaces 13b and 13e is longer than the length L of the chip 11 in the third direction D311Is small. The distance between the surfaces 13b and 13e is the distance from the surface 13b to the surface 13e in the direction orthogonal to the surfaces 13b and 13 e. The surface 13a and the surface 13d are spaced apart by a distance greater than the length L11. The distance between the surfaces 13a and 13d is the distance from the surface 13a to the surface 13d in the direction orthogonal to the surfaces 13a and 13 d. In the present embodiment, the length L11Is smaller than the value obtained by subtracting the thickness of the conductive resin paste 17 applied to the surface 13a and the thickness of the conductive resin paste 17 applied to the surface 13d from the distance between the surfaces 13a and 13 d.
Next, as shown in fig. 9, conductive resin paste 17 is filled in groove 15 of jig 13. The groove 15 is filled with the conductive resin paste 17. The seven surfaces 13a, 13b, 13c, 13d, 13e, 13f, and 13g are all in contact with the conductive resin paste 17 and are covered with the conductive resin paste 17. In the state shown in fig. 9, the conductive resin paste 17 is filled in the groove 15 so as to protrude from an imaginary plane including the main surface 13h of the jig 13. As described above, the conductive resin paste 17 contains a resin, a conductive material, and a solvent. The conductive material is, for example, metal powder. The metal powder is, for example, Ag powder or Cu powder. The resin is, for example, a thermosetting resin. The thermosetting resin is, for example, a phenol resin, an acrylic resin, a silicone resin, an epoxy resin, or a polyimide resin. The solvent is, for example, an organic solvent. Conductive resin paste 17 is known in the art, and further detailed description is omitted.
Next, as shown in fig. 10, conductive resin paste 17 in groove 15 is removed. In this process, a squeegee 21 is prepared, and the conductive resin paste 17 in the groove 15 is scraped off by the squeegee 21. The scraper 21 has a removal portion 21a having a planar shape corresponding to the groove 15. The removed portion 21a has edges corresponding to the surfaces 13a, 13b, 13c, 13d, 13e, 13f, 13 g. The removed portion 21a is inserted in the groove 15. The blade 21 is made of, for example, a metal material or a non-metal material. The non-metallic material is, for example, ceramic, carbide, resin, or rubber.
In a state where the removed portion 21a is inserted in the groove 15, the blade 21 and the jig 13 are relatively moved in a direction in which the groove 15 extends. Therefore, the conductive resin paste 17 in the groove 15 is scraped off by a predetermined amount. In a state where the removed portion 21a is inserted in the groove 15, gaps are generated between the edges of the removed portion 21a and the surfaces 13a, 13b, 13c, 13d, 13e, 13f, 13 g. Therefore, when the conductive resin paste 17 in the groove 15 is scraped off by the squeegee 21, the conductive resin paste 17 remains along the surfaces 13a, 13b, 13c, 13d, 13e, 13f, and 13 g.
Therefore, conductive resin paste 17 is applied to surfaces 13a, 13b, 13c, 13d, 13e, 13f, and 13 g. The amount of the conductive resin paste 17 applied to the surfaces 13c and 13f can be adjusted by the height position of the squeegee 21 with respect to the groove 15 (jig 13). Conductive resin paste 17 is provided on surfaces 13c and 13 f. Conductive resin paste 17 may not be provided on surfaces 13b, 13e, and 13 g. Conductive resin paste 17 may not be applied to the entirety of surfaces 13a and 13 d. Conductive resin paste 17 may be provided on a portion of surface 13a close to surface 13c and on a portion of surface 13d close to surface 13 f.
Next, as shown in fig. 11 and 12, conductive resin paste 17 is applied to chip 11. In this process, the chip is held by the prepared holder 23.
The holder 23 has a base portion (not shown) and a holding portion 27. HoldingThe portion 27 has a surface 27a, and the surface 27a has adhesiveness. The holding portion 27 is fixed to the base portion. The base is composed of, for example, a metallic material or a non-metallic material. The holding portion 27 is made of a metal material or a non-metal material. The non-metallic material is, for example, ceramic, carbide, resin, or rubber. The chip 11 is held by the holding portion 27 (holder 23) by bringing the adhesive surface 27a and the main surface 3b into contact with each other. When the holding portion 27 is made of a material having adhesiveness, the surface of the holding portion 27 constitutes an adhesive surface 27 a. When the holding portion 27 is made of a material having no adhesiveness or low adhesiveness, the holding portion 27 may have a layer having high adhesiveness. The layer having high adhesiveness constitutes the face 27a having adhesiveness. The length of the holding portion 27 is longer than the length L of the chip 1111Is small. The width of the holding portion 27 is smaller than the width of the chip 11. Therefore, the face 27a is less likely to be contaminated. As shown in fig. 13, the length of the holding portion 27 may be longer than the length L of the chip 1111Is large. In this case, the length of the holding portion 27 is longer than the length L of the chip 1111The holding force of the holding portion 27 to the chip 11 is secured as compared with the case where it is small.
In this process, the chip 11 held by the holder 23 is arranged above the groove 15 so that the third direction D3 is parallel to the direction in which the surfaces 13a and 13D face each other. Thereafter, the jig 13 and the holder 23 are relatively moved in a direction orthogonal to the direction in which the surfaces 13a and 13d are opposed to each other, so that the chip 11 is inserted into the slot 15.
When the chip 11 is inserted into the slot 15, the chip 11 approaches the jig 13 in such a manner that the face 13c faces the main face 3a, the face 13a faces one end face 3e, the face 13f faces the main face 3a, and the face 13d faces the other end face 3 e. Since the first electrode layer E1 is disposed on each end face 3E, the first electrode layer E1 is located between the face 13a and one end face 3E, and the first electrode layer E1 is located between the face 13d and the other end face 3E. Therefore, the face 13a is indirectly opposed to the one end face 3e, and the face 13d is indirectly opposed to the other end face 3 e.
When the chip 11 approaches the jig 13 as described above, the chip 11 is brought into contact with the conductive resin paste 17 applied to the jig 13 as shown in fig. 11 and 12. The conductive resin paste 17 applied to the surfaces 13c and 13f is applied to the chip 11. In the present embodiment, the chip 11 approaches the jig 13 until the chip 11 abuts on the surfaces 13c and 13 f.
The conductive resin paste 17 applied to the surface 13c is applied to the main surface 3a, one end surface 3e, and the pair of side surfaces 3c of the chip 11. In the present embodiment, the first electrode layer E1 is disposed on the end face 3E. Therefore, the conductive resin paste 17 is directly applied to the first electrode layer E1, thereby being indirectly applied to the one end face 3E, and is directly applied to the main face 3a and the pair of side faces 3 c.
The conductive resin paste 17 applied to the surface 13f is applied to the main surface 3a, the other end surface 3e, and the pair of side surfaces 3c of the chip 11. In the present embodiment, the first electrode layer E1 is disposed on the end face 3E. Therefore, the conductive resin paste 17 is directly applied to the first electrode layer E1, thereby being indirectly applied to the other end face 3E, and is directly applied to the main face 3a and the pair of side faces 3 c. In the region of the main surface 3a which is in contact with the surfaces 13c and 13f, when the chip 11 is separated from the jig 13, the conductive resin paste 17 is also applied by the wraparound of the conductive resin paste 17.
As described above, the distance between the surfaces 13b and 13e is longer than the length L11Small and the height positions of the face 13c and the face 13f are the same. Therefore, the conductive resin paste 17 applied to the surface 13c is applied to the main surface 3a, the one end surface 3e, and the pair of side surfaces 3c of the chip 11, and the conductive resin paste 17 applied to the surface 13f is applied to the main surface 3a, the other end surface 3e, and the pair of side surfaces 3c of the chip 11.
The portion of conductive resin paste 17 on main surface 13h of imparting surface 13a is distant from chip 11, and conductive resin paste 17 is not imparted to chip 11. The portion of conductive resin paste 17 on main surface 13h of imparting surface 13a is distant from chip 11, and conductive resin paste 17 is not imparted to chip 11. Conductive resin paste 17 mainly adhering to surfaces 13c and 13f is applied to chip 11. Therefore, the conductive resin paste 17 is applied only to the region near the main surface 3a of the end surface 3e, the region near the main surface 3a and near the end surface 3e of the side surfaces 3c, and the region near the main surface 3a of the main surface 3 a. Conductive resin paste 17 is applied to chip 11 so as to cover only a part of first electrode layer E1.
As shown in fig. 12, in a state where the chip 11 is brought close to the jig 13, when viewed from a direction parallel to the main surface 3a and the end surface 3E, that is, when viewed from the second direction D2, a distance L from the surface 13a to the end edge E1E of the first electrode layer E1 in the direction along the height direction of the stepE1Is wider than the width W of the surface 13c in the height direction of the step13cIs small. When viewed from the second direction D2 in a state where the chip 11 is brought close to the jig 13, a distance L from the surface 13D to the end edge E1E of the first electrode layer E1 in the direction along the height direction of the stepE2Is wider than the width W of the surface 13f in the height direction of the step13fIs small. In the present embodiment, the width W13cAnd width W13fAre equivalent. The height direction of the step is the direction in which the face 13a and the face 13d oppose each other. The second direction D2 is a direction parallel to all of the seven faces 13a, 13b, 13c, 13D, 13e, 13f, 13 g. In fig. 12, the holder 23 and the conductive resin paste 17 are not shown.
In order to take out the chip 11 from the jig 13, the holder 23 (chip 11) and the jig 13 are relatively separated. Thereafter, the chip 11 is detached from the holder 23. Thus, the chip 11 to which the conductive resin paste 17 is applied is obtained.
Next, the conductive resin paste 17 applied to the chip 11 is treated to cure the conductive resin paste 17. That is, conductive resin paste 17 is cured. When conductive resin paste 17 contains, for example, a thermosetting resin, conductive resin paste 17 is heated. The heat treatment of the conductive resin paste 17 is, for example, to heat the conductive resin paste 17 at a temperature of about 100 to 250 ℃ for about 30 to 120 minutes. When conductive resin paste 17 contains, for example, a photocurable resin, conductive resin paste 17 is irradiated with light having a predetermined wavelength. The conductive resin paste 17 may be cured according to the type of the conductive resin paste 17.
Through the above process, the second electrode layer E2 is formed on the chip 11 (see fig. 7).
Next, the third electrode layer E3 and the fourth electrode layer E4 were formed on the chip 11 on which the first electrode layer E1 and the second electrode layer E2 were formed. In this process, as described above, the third electrode layer E3 and the fourth electrode layer E4 are formed by the plating method. The third electrode layer E3 is formed on the second electrode layer E2 and the portion of the first electrode layer E1 exposed from the second electrode layer E2. The fourth electrode layer E4 is formed on the third electrode layer E3. The plating method for forming the third electrode layer E3 and the fourth electrode layer E4 is, for example, an electrolytic plating method. The plating method for forming the third electrode layer E3 and the fourth electrode layer E4 is known in the art, and further detailed description is omitted.
Through the above-described procedure, the multilayer capacitor C1 is obtained.
As described above, in the above manufacturing process, chip 11 is brought close to jig 13 so that surface 13c faces main surface 3a and surface 13a faces one end surface 3e, and conductive resin paste 17 applied to surface 13c is applied to main surface 3a, one end surface 3e, and a pair of side surfaces 3 c. A desired amount of conductive resin paste 17 is appropriately applied to surface 13c as compared with the inner surface of the jig used in the above-described background art. Therefore, in the present embodiment, conductive resin paste 17 is easily wound around each side surface 3 c. As a result, the conductive resin paste 17 is easily applied to each side surface 3c, and the second electrode layer E2 is formed not only on the principal surface 3a and one end surface 3E but also on each side surface 3c as appropriate.
The shape and size of the second electrode layer E2 can be adjusted according to the shape of the steps of the surfaces 13a and 13 b. Therefore, the second electrode layer E2 having a desired shape and size is easily formed. The shape of the step of the surface 13a and the surface 13b is, for example, the width W of the surface 13c in the height direction of the step13cAnd the like.
The chip 11 includes a first electrode layer E1 disposed on one end surface 3E. In the above-described manufacturing process, when the conductive resin paste 17 is applied to the main surface 3a, the one end surface 3E, and the pair of side surfaces 3c, the conductive resin paste 17 is directly applied to the first electrode layer E1 to indirectly apply the conductive resin paste to the one end surface 3E, and is directly applied to the main surface 3a and the side surfaces 3 c. Therefore, the conductive resin paste 17 is provided so as to cover the edge of the first electrode layer E1. As a result, the second electrode layer E2 was formed so as to cover the edge of the first electrode layer E1.
When the chip 11 is brought close to the jig 13, the distance L is measured in a direction parallel to both the main surface 3a and the end surface 3eE1Less than width W13c. Therefore, the conductive resin paste 17 is reliably provided so as to cover the end edge of the first electrode layer E1. As a result, the second electrode layer E2 was formed so as to reliably cover the edge of the first electrode layer E1.
In the above-described manufacturing process, when conductive resin paste 17 is applied to main surface 3a, one end surface 3e, and the pair of side surfaces 3c, chip 11 is brought close to jig 13 until chip 11 and surface 13c come into contact. Since chip 11 is in contact with surface 13c, the positional relationship between jig 13 and chip 11 when conductive resin paste 17 is applied to chip 11 is less likely to change for each chip 11. Therefore, the applied state of the conductive resin paste 17 is not likely to vary from chip to chip 11. As a result, variations in the shape and size of the second electrode layer E2 formed on each chip 11 can be suppressed.
In the above manufacturing process, chip 11 is brought close to jig 13 so that surface 13f faces main surface 3a and surface 13d faces the other end surface 3e, and conductive resin paste 17 applied to surface 13f is applied to main surface 3a, the other end surface 3e, and the pair of side surfaces 3 c. A desired amount of conductive resin paste 17 is appropriately applied to surface 13f as compared with the inner surface of the jig used in the above-described background art. Therefore, in the present embodiment, conductive resin paste 17 is easily wound around each side surface 3 c. As a result, the conductive resin paste 17 is easily applied to each side surface 3c, and the second electrode layer E2 is formed not only on the main surface 3a and the other end surface 3E but also on each side surface 3c as appropriate.
The shape and size of the other second electrode layer E2 may be adjusted according to the shape of the steps of the face 13d and the face 13E. Therefore, the other second electrode layer E2 having a desired shape and size is easily formed. The shape of the step of the surface 13d and the surface 13e is, for example, the width W of the surface 13f in the height direction of the step13fAnd the like.
The chip 11 includes another first electrode layer E1 formed on the other end face 3E. In the above-described manufacturing process, when the conductive resin paste 17 is applied to the main surface 3a, the other end surface 3E, and the pair of side surfaces 3c, the conductive resin paste 17 is directly applied to the other first electrode layer E1, thereby indirectly applying the conductive resin paste 17 to the other end surface 3E, and directly applying the conductive resin paste 17 to the main surface 3a and the side surfaces 3 c. Therefore, the conductive resin paste 17 is provided so as to cover the end edge of the other first electrode layer E1. As a result, the second electrode layer E2 is formed so as to cover the edge of the first electrode layer E1.
When the chip 11 is brought close to the jig 13, the distance L is measured in a direction parallel to both the main surface 3a and the end surface 3eE2Less than width W13f. Therefore, the conductive resin paste 17 is reliably provided so as to cover the edge of the other first electrode layer E1. As a result, the second electrode layer E2 is formed so as to reliably cover the edge of the first electrode layer E1.
In the above-described manufacturing process, when conductive resin paste 17 is applied to main surface 3a, other end surface 3e, and pair of side surfaces 3c, chip 11 is brought close to jig 13 until chip 11 and surface 13f are brought into contact. Since chip 11 is in contact with surface 13f, the positional relationship between jig 13 and chip 11 when conductive resin paste 17 is applied to chip 11 is less likely to change for each chip 11. Therefore, the applied state of the conductive resin paste 17 is not likely to vary from chip to chip 11. As a result, variations in the shape and size of the second electrode layer E2 formed on each chip 11 can be suppressed.
The spacing between the surfaces 13a and 13d is greater than the length L of the chip 1111The distance between the surface 13b and the surface 13e is smaller than the length L11. In the above-described manufacturing process, the conductive resin paste 17 applied to the face 13c is applied to the main face 3a, the one end face 3e, and the pair of side faces 3c, and the conductive resin paste 17 applied to the face 13f is applied to the main face 3a, the other end face 3e, and the pair of side faces 3 c. Therefore, in one process, the conductive resin paste 17 is simultaneously applied to the portion of the chip 11 near the one end surface 3e and the portion of the chip 11 near the other end surface 3 e. Therefore, the manufacturing process of the multilayer capacitor C1 is simplified.
The element body 3 has a main surface 3b opposed to the main surface 3 a. In the above-described manufacturing process, the holder 23 having the adhesive surface 27a is prepared, and the chip 11 is held on the holder 23 by bringing the adhesive surface 27a into contact with the main surface 3 b. Therefore, the chip 11 is simply held on the holder 23.
The conductive resin paste 17 contains a conductive material and a resin. Therefore, each of the second electrode layers E2 constitutes a conductive resin layer. As a result, as described above, the second electrode layers E2 suppress the occurrence of cracks in the element body 3.
The embodiments of the present invention have been described above, but the present invention is not necessarily limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.
In the above-described manufacturing process, the conductive resin paste 17 is applied to the chip 11. The paste applied to the chip 11 is not limited to the conductive resin paste 17. The paste applied to the chip 11 may be a conductive paste containing a powder of a conductive material and an organic vehicle. In this case, the electroconductive paste is subjected to, for example, heat treatment.
The chip 11 to which the paste is applied includes the first electrode layer E1, but the chip 11 may not include the first electrode layer E1. In this case, the paste is directly applied to the main surface 3a, the end surface 3e, and the pair of side surfaces 3 c.
The paste-applied chip 11 may be provided with a film made of a conductive paste instead of the first electrode layer E1. In this case, the paste applied to the chip 11 may be the above-described conductive paste.
In the above-described manufacturing process, the application of the conductive resin paste 17 to the main surface 3a, the one end surface 3e, and the pair of side surfaces 3c, and the application of the conductive resin paste 17 to the main surface 3a, the other end surface 3e, and the pair of side surfaces 3c are performed simultaneously. The application of conductive resin paste 17 to main surface 3a, one end surface 3e, and pair of side surfaces 3c and the application of conductive resin paste 17 to main surface 3a, the other end surface 3e, and pair of side surfaces 3c may not be performed simultaneously. For example, after the conductive resin paste 17 is applied to the main surface 3a, the one end surface 3e, and the pair of side surfaces 3c, the conductive resin paste 17 may be applied to the main surface 3a, the other end surface 3e, and the pair of side surfaces 3 c. After the conductive resin paste 17 is applied to the main surface 3a, the other end surface 3e, and the pair of side surfaces 3c, the conductive resin paste 17 may be applied to the main surface 3a, the one end surface 3e, and the pair of side surfaces 3 c.
The jig 13 may be divided into a portion having the surfaces 13a, 13b, and 13c and a portion having the surfaces 13d, 13e, and 13 f. The portions having the faces 13a, 13b, 13c and the portions having the faces 13d, 13e, 13f may be separated.
When conductive resin paste 17 is applied to chip 11, chip 11 and surface 13f may not be in contact with each other. When the chip 11 is brought close to the jig 13 until the chip 11 and the surface 13f come into contact with each other, as described above, variations in the shape and size of the second electrode layer E2 formed on each chip 11 can be suppressed as compared with the case where the chip 11 and the surface 13f do not come into contact with each other.
In the above-described manufacturing process, the process of applying the conductive resin paste 17 to the chip 11 may be repeated a plurality of times. For example, after the conductive resin paste 17 is applied over the main surface 3a, the end surface 3e, and the pair of side surfaces 3c, the conductive resin paste 17 may be applied over the main surface 3a, the end surface 3e, and the pair of side surfaces 3c again. In this case, the thickness of the conductive resin paste 17 applied to the chip 11 can be adjusted.
The first electrode layer E1 may be formed on the main surface 3a so as to extend from the end surface 3E over the entire ridge portion 3g or a part thereof. The first electrode layer E1 may be formed on the main surface 3b so as to extend from the end surface 3E over the entire ridge portion 3h or a part thereof. The first electrode layer E1 may be formed on the side surface 3c so as to extend from the end surface 3E over the whole or part of the ridge portion 3 i.
In the present embodiment, the multilayer capacitor C1 is described as an example of an electronic component, but applicable electronic components are not limited to the multilayer capacitor. Applicable electronic components are, for example, laminated electronic components such as laminated inductors, laminated piezoresistors, laminated piezoelectric actuators, laminated thermistors, laminated composite elements, or other laminated electronic components, or electronic components other than laminated electronic components.

Claims (14)

1. A method for manufacturing an electronic component is characterized in that,
the electronic component includes:
an element body having a main surface, an end surface, and a side surface which are adjacent to each other; and
a conductor layer disposed over the main surface, the end surface, and the side surface,
the manufacturing method comprises the following steps:
preparing a chip comprising the element body,
preparing a jig having a pair of faces with a step and a step face between the pair of faces,
applying a paste containing a conductive material to the step surface of the jig,
bringing the chip close to the jig so that the main surface and the step surface face each other and the end surface and one of the pair of surfaces face each other, and applying the paste over the main surface, the end surface, and the side surface,
the paste applied to the main surface, the end surface, and the side surface is processed to form the conductor layer.
2. The manufacturing method according to claim 1,
the chip further includes a sintered metal layer disposed on the end face,
when the paste is applied over the main surface, the end surface, and the side surface, the paste is applied directly to the sintered metal layer, thereby indirectly applying the paste to the end surface, and the paste is applied directly to the main surface and the side surface.
3. The manufacturing method according to claim 2,
when viewed from a direction parallel to the main surface and the end surface in a state where the chip is brought close to the jig, a distance from the one surface of the pair of surfaces to an end edge of the sintered metal layer in a direction along a height direction of the step is smaller than a width of the step surface in the height direction of the step.
4. The production method according to any one of claims 1 to 3,
when the paste is applied over the main surface, the end surfaces, and the side surfaces, the chip is brought close to the jig until the chip abuts against the step surface.
5. The production method according to any one of claims 1 to 4,
the element body further has another end face opposed to the end face and adjacent to the main face and the side face,
the electronic component further includes another conductor layer disposed over the main surface, the side surface, and the other end surface,
the jig further has: another opposite surface opposite to the pair of surfaces and having another step, and another step surface between the another opposite surfaces,
the paste is given to the other step surface of the jig,
bringing the chip close to the jig so that the main surface and the other step surface face each other and one of the other end surface and the other opposite surface faces each other, and applying the paste over the main surface, the side surfaces, and the other end surface,
and processing the paste applied over the main surface, the side surface, and the other end surface to form the other conductor layer.
6. The manufacturing method according to claim 5,
the chip is further provided with another sintered metal layer formed on the other end face,
when the paste is applied over the main surface, the side surface, and the other end surface, the paste is indirectly applied to the other end surface by directly applying the paste to the other sintered metal layer, and the paste is directly applied to the main surface and the side surface.
7. The manufacturing method according to claim 6,
when viewed from a direction parallel to the main surface and the other end surface in a state where the chip is brought close to the jig, a distance from the one surface of the other opposing surface to an end edge of the other sintered metal layer in a direction along a height direction of the other step is smaller than a width of the other step surface in the height direction of the other step.
8. The production method according to any one of claims 5 to 7,
when the paste is applied over the main surface, the side surface, and the other end surface, the chip is brought close to the jig until the chip abuts against the other step surface.
9. The production method according to any one of claims 5 to 8,
the one face of the one pair of faces and the one face of the other pair of faces are spaced apart by a distance greater than a length of the chip in a direction in which the end face and the other end face oppose each other,
the other of the pair of faces and the other of the other pair of faces are spaced apart by a distance less than the length of the chip,
the paste to be applied to the step surface is applied to the main surface, the end surface, and the side surface, and the paste to be applied to the other step surface is applied to the main surface, the side surface, and the other end surface.
10. The production method according to any one of claims 1 to 9,
the element body further has another main surface opposite to the main surface,
preparing a holder having a surface having adhesiveness,
the chip is held by the holder by bringing the face having adhesiveness and the other main face into contact.
11. The production method according to any one of claims 1 to 10,
the paste is a conductive resin paste containing the conductive material and a resin.
12. A method for forming a conductive layer, wherein,
preparing a chip having an element body having a main surface, an end surface, and a side surface which are adjacent to each other,
preparing a jig having a pair of faces with a step and a step face between the pair of faces,
applying a paste containing a conductive material to the step surface of the jig,
bringing the chip close to the jig so that the main surface and the step surface face each other and the end surface and one of the pair of surfaces face each other, and applying the paste over the main surface, the end surface, and the side surface,
the paste applied to the main surface, the end surfaces, and the side surfaces is processed to form conductor layers disposed over the main surface, the end surfaces, and the side surfaces.
13. The forming method according to claim 12,
the element body further has another end face opposed to the end face and adjacent to the main face and the side face,
the jig further has: another opposite surface opposite to the pair of surfaces and having another step, and another step surface between the another opposite surfaces,
the paste is given to the other step surface of the jig,
bringing the chip close to the jig so that the main surface and the other step surface face each other and one of the other end surface and the other opposite surface faces each other, and applying the paste over the main surface, the side surfaces, and the other end surface,
and processing the paste applied over the main surface, the side surface, and the other end surface to form another conductor layer disposed over the main surface, the side surface, and the other end surface.
14. The forming method according to claim 12 or 13,
the paste is a conductive resin paste containing the conductive material and a resin.
CN201910729660.6A 2018-08-09 2019-08-08 Method for manufacturing electronic component and method for forming conductor layer Pending CN110828174A (en)

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Application publication date: 20200221