CN110827759B

CN110827759B - Display panel and display device

Info

Publication number: CN110827759B
Application number: CN201911133519.6A
Authority: CN
Inventors: 翟应腾
Original assignee: Shanghai Tianma AM OLED Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2019-11-19
Filing date: 2019-11-19
Publication date: 2021-03-05
Anticipated expiration: 2039-11-19
Also published as: CN110827759A

Abstract

The invention discloses a display panel and a display device, wherein when the display panel is in a second working state, a driving chip corresponding to a first sub-display area is started so as to enable the first sub-display area to display normally. And the driving chip corresponding to the second sub-display area is started so as to enable the second sub-display area to display normally. And when the display panel is in the first working state, the driving chip corresponding to the second sub-display area is started, so that the second sub-display area displays normally. And inputting a high-level signal to the signal transmission line in the first sub-display area through the control circuit through the electrically connected control voltage input end to enable the level of the grid electrodes of the driving transistors of all the pixel circuits in the first sub-display area to be high level so as to control the driving transistors to be turned off and enable the first sub-display area not to emit light. Not only can reduce power consumption, but also can avoid the first sub-display area from emitting light, thereby improving the competitiveness of the display panel.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

An Organic Light Emitting Diode (OLED) panel is one of the hot spots in the research field of flat panel displays, and compared with a Liquid Crystal Display (LCD), an OLED panel has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, fast response speed, and the like. Currently, in the field of flat panel displays such as mobile phones, PDAs, and digital cameras, OLED panels have begun to replace conventional liquid crystal displays. The pixel circuit design is the core technical content of the OLED panel, and has important research significance. However, the transistor in the pixel circuit may have a leakage phenomenon, thereby causing unstable display of the OLED panel.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, which are used for solving the problem of unstable display caused by the leakage phenomenon of a transistor in a pixel circuit.

An embodiment of the present invention provides a display panel, including: a display area and a non-display area surrounding the display area, the display area including: a plurality of sub-pixels and signal transmission lines; each of the sub-pixels includes a pixel circuit; the display area is divided into a plurality of sub-display areas, and the plurality of sub-display areas comprise a first sub-display area and a second sub-display area which correspond to each other;

the non-display area includes: the control circuit comprises a plurality of control voltage input ends and a plurality of driving chips with control voltage output ends which are mutually independent; the same control circuit is connected with different control voltage input ends; the pixel circuits in the sub-display areas are electrically connected with the corresponding control voltage input ends through signal transmission lines; one sub-display area corresponds to one driving chip, and the control voltage output end of the driving chip is electrically connected with the corresponding control voltage input end;

the display panel has a first working state and a second working state;

in the first working state, the driving chip corresponding to the first sub-display area is turned off, and the control circuit inputs a high-level signal to the signal transmission line in the first sub-display area through an electrically connected control voltage input end, so that the levels of the gates of the driving transistors of all the pixel circuits in the first sub-display area are high levels, and the driving transistors are controlled to be turned off, so that the first sub-display area does not emit light; the driving chip corresponding to the second sub-display area is started so as to enable the second sub-display area to display normally;

in the second working state, the driving chip corresponding to the first sub-display area is started to enable the first sub-display area to display normally; and the driving chip corresponding to the second sub-display area is started so as to enable the second sub-display area to normally display.

The embodiment of the invention also provides a display device which comprises the display panel.

The invention has the following beneficial effects:

according to the display panel and the display device provided by the embodiment of the invention, when the display panel is in the second working state, the driving chip corresponding to the first sub-display area is started, so that the first sub-display area can normally display. The driving chip corresponding to the second sub-display area is started to enable the second sub-display area to display normally, and the control circuit does not output signals, so that the influence on the normal display of the first sub-display area and the second sub-display area can be avoided. And when the display panel is in the first working state, the driving chip corresponding to the second sub-display area can be started, so that the second sub-display area can display normally. When the driving chip corresponding to the first sub-display area is turned off, a high-level signal can be input to the signal transmission line in the first sub-display area through the control circuit through the electrically connected control voltage input end, so that the levels of the gates of the driving transistors of all the pixel circuits in the first sub-display area are high levels to control the driving transistors to be turned off, and the first sub-display area can be prevented from emitting light. By arranging the control circuit, the first sub-display area can be made not to emit light when the driving chip corresponding to the first sub-display area is closed, so that the power consumption can be reduced, the first sub-display area can be prevented from emitting light, and the competitiveness of the display panel can be improved.

Drawings

Fig. 1 is a schematic structural diagram of a display panel in the related art;

FIG. 2 is a schematic diagram of a pixel circuit in the related art;

FIG. 3 is a timing diagram of the pixel circuit;

FIG. 4 is a schematic structural diagram of some display panels according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of some pixel circuits according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a plurality of pixel circuits according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of still other display panels in an embodiment of the invention;

FIG. 8 is a schematic structural diagram of still other display panels in an embodiment of the invention;

FIG. 9 is a schematic structural diagram of still other display panels in an embodiment of the invention;

FIG. 10 is a schematic structural diagram of still other display panels in an embodiment of the invention;

FIG. 11 is a schematic structural diagram of still other display panels in an embodiment of the invention;

FIG. 12 is a schematic structural diagram of still other display panels in an embodiment of the invention;

FIG. 13 is a schematic structural diagram of some display devices according to embodiments of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As the demand for portable display devices increases, flexible display technology becomes one of the display technologies with great competitive advantages. One advantage of flexible display technology is its foldability, which allows for an increased display area without increasing the size of the display device, and portability. As shown in fig. 1, the display panel having a flexible and foldable function may include: a first display area a1 and a second display area a 2. Also, the first display region a1 and the second display region a2 of the display panel may each include a plurality of sub-pixels, and each of the sub-pixels may include an electroluminescent diode and a pixel circuit driving the electroluminescent diode to emit light. Illustratively, as shown in fig. 2, the pixel circuit may include: a driving transistor M0, circuit transistors M01 ' to M05 ', and a storage capacitor C0 '. The circuit timing diagram for the pixel circuit shown in fig. 2 is shown in fig. 3. The working process of the pixel circuit can comprise the following steps: t01, T02 and T03. In the stage T01, the signal at the second SCAN signal terminal SCAN2 is a high level signal, and the circuit transistors M02 'and M03' are turned off. The signal of the emission control signal terminal EM is a high level signal, and the circuit transistors M04 'and M05' are turned off. The signal at the first SCAN signal terminal SCAN1 is a low level signal, and the circuit transistor M01' is turned on to provide the low voltage signal at the reference signal terminal VREF to the node N1 (i.e., the gate of the driving transistor M0). In the stage T02, the signal at the first SCAN signal terminal SCAN1 is a high level signal, and the circuit transistor M01' is turned off. The signal of the emission control signal terminal EM is a high level signal, and the circuit transistors M04 'and M05' are turned off. The signal of the second SCAN signal terminal SCAN2 is a low level signal, the circuit transistors M02 'and M03' are turned on, and the signal voltage Vdata of the DATA input terminal DATA is input to the node N2 through the circuit transistor M02 ', and charges the node N1 through the circuit transistor M03' and the driving transistor M0, so that the voltage of the node N1 is Vdata + | Vth |. Where Vth represents the threshold voltage of the driving transistor M0. In the stage T03, the signal at the first SCAN signal terminal SCAN1 is a high level signal, and the circuit transistor M01' is turned off. The signal of the second SCAN signal terminal SCAN2 is a high level signal, and the circuit transistors M02 'and M03' are turned off. The signal of the light-emitting control signal terminal EM is a low level signal, and the circuit transistors M04 ', M05' are turned on, so that the driving transistor M0 generates a driving current according to the voltage of the node N1 and the voltage of the first power source terminal PVDD to drive the light-emitting device L to emit light.

Also, the display panel may further include: a first drive control chip B1 for inputting signals to the first display area a1 and a second drive control chip B2 for inputting signals to the second display area a 2. For example, a signal is input to the reference signal terminal VREF of the pixel circuit in the first display area a1 and a signal is input to the data line through the first driving control chip B1, and a signal is input to the reference signal terminal VREF of the pixel circuit in the second display area a2 and a signal is input to the data line through the second driving control chip B2.

In practical applications, the display panel may be folded along the dashed line L0 (which is not actually present), that is, the first display area a1 and the second display area a2 may be folded along the dashed line L0. After folding, the viewer will look at one side and not the other. In order to reduce power consumption, only one side may be displayed, for example, the second display region a2 may be displayed, and the first display region a1 may not be displayed. In addition, in order to reduce power consumption, the first driving control chip B1 connected to the first display area a1 may be directly turned off, so that the first display area a1 is normally bright due to leakage.

Specifically, since the first driving control chip B1 is directly turned off without generating a signal, the reference signal terminal VREF of the pixel circuit in the first display region a1 is floated and the data line is floated. The node N1 is unstable due to the leakage current of the circuit transistor M01 ', and the node N2 is unstable due to the leakage current of the circuit transistor M02', which may cause the voltages at the nodes N1 and N2 to be susceptible to other signals in the display panel, resulting in the instability of the pixel circuit, and thus the driving transistor M0 may generate a current to drive the light emitting device L to emit light. Alternatively, although the first driving control chip B1 is turned off directly, the reference signal terminal VREF of the pixel circuit in the first display area a1 is still inputted with a signal, and the voltage at the node N1 is changed to a low voltage of the reference signal terminal VREF due to the leakage current of the circuit transistor M01'. This causes the driving transistor M0 to generate a current when the pixel circuit in the first display region a1 is in the T03 phase, thereby causing the light emitting device L in the first display region a1 to emit light.

In view of the above, an embodiment of the present invention provides a display panel, which is shown in fig. 4 and 5, and includes: a display area AA and a non-display area BB surrounding the display area, the display area AA may include: a plurality of subpixels 110 and signal transmission lines; each sub-pixel 110 includes a pixel circuit 111; the display area AA may be divided into a plurality of sub-display areas AA-K (K is not less than 1 and not more than K, K and K are integers, and K is the total number of the sub-display areas, and K is 2 in fig. 4 as an example), and the plurality of sub-display areas include a first sub-display area AA-1 and a second sub-display area AA-2 corresponding to each other.

The non-display area BB may include: the control circuit 120 comprises a plurality of mutually independent control voltage input ends CSI-k and a plurality of drive chips 130-k with control voltage output ends CSO-k; the same control circuit 120 is connected to different control voltage input terminals CSI-k; one driving chip is electrically connected to one control voltage input terminal, and the pixel circuits 111 in the sub-display regions are electrically connected to the corresponding control voltage input terminals through signal transmission lines. And one sub-display area corresponds to one driving chip, one sub-display area corresponds to one control voltage input end, and the control voltage output end of the driving chip is electrically connected with the corresponding control voltage input end. For example, the first sub-display area AA-1 corresponds to the first driving chip 130-1, the first sub-display area AA-1 corresponds to the control voltage input terminal CSI-1, and the control voltage output terminal CSO-1 of the first driving chip 130-1 is electrically connected to the control voltage input terminal CSI-1 corresponding to the first sub-display area AA-1. The second sub-display area AA-2 corresponds to the second driving chip 130-2, the second sub-display area AA-2 corresponds to the control voltage input terminal CSI-2, and the control voltage output terminal CSO-2 of the second driving chip 130-2 is electrically connected with the control voltage input terminal CSI-2 corresponding to the second sub-display area AA-2.

The display panel has a first working state and a second working state; wherein,

in a first working state, the driving chip 130-1 corresponding to the first sub-display area AA-1 is turned off, and the control circuit 120 inputs a high level signal to the signal transmission line in the first sub-display area AA-1 through the electrically connected control voltage input terminal CSI-1, so that the levels of the gates of the driving transistors of all the pixel circuits 111 in the first sub-display area AA-1 are high levels, and the driving transistors are controlled to be turned off, so that the first sub-display area AA-1 does not emit light; the driving chip corresponding to the second sub-display area AA-2 is started so that the second sub-display area AA-2 can normally display;

under a second working state, the driving chip corresponding to the first sub-display area AA-1 is started, so that the first sub-display area AA-1 displays normally; and the driving chip corresponding to the second sub-display area AA-2 is started so as to enable the second sub-display area AA-2 to normally display.

According to the display panel provided by the embodiment of the invention, when the display panel is in the second working state, the driving chip corresponding to the first sub-display area is started, so that the first sub-display area can normally display. The driving chip corresponding to the second sub-display area is started to enable the second sub-display area to display normally, and the control circuit does not output signals, so that the influence on the normal display of the first sub-display area and the second sub-display area can be avoided. And when the display panel is in the first working state, the driving chip corresponding to the second sub-display area can be started, so that the second sub-display area can display normally. When the driving chip corresponding to the first sub-display area is turned off, a high-level signal can be input to the signal transmission line in the first sub-display area through the control circuit through the electrically connected control voltage input end, so that the levels of the gates of the driving transistors of all the pixel circuits in the first sub-display area are high levels to control the driving transistors to be turned off, and the first sub-display area can be prevented from emitting light. By arranging the control circuit, the first sub-display area can be made not to emit light when the driving chip corresponding to the first sub-display area is closed, so that the power consumption can be reduced, the first sub-display area can be prevented from emitting light, and the competitiveness of the display panel can be improved.

It should be noted that, the driving chip turn-off finger may be: the driving chip stops supplying power, does not generate and does not output any signal to the corresponding sub-display region. The drive chip turn-on finger can be: the driving chip supplies power to generate and output any signal to the corresponding sub-display area.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4, the display area AA of the display panel may be divided into two sub-display areas: a first sub-display area AA-1 and a second sub-display area AA-2. Of course, in practical applications, the number of the sub-display areas may also be designed according to practical application environments, which is not described herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4, the display panel further includes: a folding axis L1; wherein, the first sub-display area AA-1 and the second sub-display area AA-2 are respectively positioned at two sides of the folding axis. This allows the first sub-display area AA-1 and the second sub-display area AA-2 to be folded and unfolded along the folding axis.

Illustratively, in the second working state, the first sub-display area AA-1 and the second sub-display area AA-2 are unfolded. That is, the first sub-display area AA-1 and the second sub-display area AA-2 are unfolded along the folding axis, so that the first sub-display area AA-1 and the second sub-display area AA-2 form the entire display area, that is, the entire display area may be displayed to increase the display area.

Illustratively, in the first working state, the first sub-display area AA-1 and the second sub-display area AA-2 are folded. That is, the first sub-display area AA-1 and the second sub-display area AA-2 are folded along the folding axis, and at this time, the first sub-display area AA-1 may stop displaying light and only the second sub-display area AA-2 may display light, so that the user may view only the second sub-display area AA-2, thereby reducing power consumption. In practical applications, in a display product, for example, in a foldable mobile phone, when the foldable mobile phone is folded in a left-right folding manner, the first sub-display area AA-1 may be used as a left display screen of the mobile phone, and the second sub-display area AA-2 may be used as a right display screen of the mobile phone. Or, the second sub-display area AA-2 may be used as a left display screen of the mobile phone, and the first sub-display area AA-1 may be used as a right display screen of the mobile phone. Or, when the mobile phone is folded in an up-and-down folding manner, the first sub-display area AA-1 may be used as the upper display screen of the mobile phone, and the second sub-display area AA-2 may be used as the lower display screen of the mobile phone. Alternatively, the second sub-display area AA-2 may be used as the upper display screen of the mobile phone, and the first sub-display area AA-1 may be used as the lower display screen of the mobile phone. Of course, the design may be determined according to the actual application environment, and is not limited herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4, the display panel may include: a substrate 100, and a plurality of pixel units PX located on the substrate 100. Each pixel unit PX may be made to include a plurality of sub-pixels 110. For example, the sub-pixels included in the pixel unit PX may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel to realize an image display function by red, green, and blue color mixing. It is also possible to make the pixel unit PX include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel to realize an image display function by red, green, blue, and white color mixing.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4 and 5, each sub-pixel 110 may include a light emitting device L and a pixel circuit 111 for driving the light emitting device L to emit light. The light-emitting device comprises an anode, a light-emitting functional layer and a cathode which are stacked. Further, the light emitting device may include: at least one of Organic Light Emitting Diodes (OLED) and Quantum Dot Light Emitting Diodes (QLED). For example, the anode of the light emitting device L serves as a first terminal of the light emitting device L, the cathode of the light emitting device L serves as a second terminal of the light emitting device L, and the second terminal of the light emitting device L is electrically connected to the second power source terminal ELVSS.

In specific implementation, as shown in fig. 5, the pixel circuit 111 may include: a first switching transistor M01, a second switching transistor M02, a third switching transistor M03, a fourth switching transistor M04, a fifth switching transistor M05, a driving transistor M0, and a storage capacitor C0.

The gate of the first switching transistor M01 is electrically connected to the first SCAN signal terminal SCAN1, the first pole of the first switching transistor M01 is electrically connected to the reference signal terminal VREF, and the second pole of the first switching transistor M01 is electrically connected to the gate of the driving transistor M0.

A gate of the second switching transistor M02 is electrically connected to the second SCAN signal terminal SCAN2, a first pole of the second switching transistor M02 is electrically connected to the DATA input terminal DATA, and a second pole of the second switching transistor M02 is electrically connected to the first pole of the driving transistor M0.

A gate of the third switching transistor M03 is electrically connected to the second SCAN signal terminal SCAN2, a first pole of the third switching transistor M03 is electrically connected to a gate of the driving transistor M0, and a second pole of the third switching transistor M03 is electrically connected to a second pole of the driving transistor M0.

A gate of the fourth switching transistor M04 is electrically connected to the light emission control signal terminal EM, a first pole of the fourth switching transistor M04 is electrically connected to the second pole of the driving transistor M0, and a second pole of the fourth switching transistor M04 is electrically connected to the first pole of the light emitting device L.

A gate of the fifth switching transistor M05 is electrically connected to the emission control signal terminal EM, a first pole of the fifth switching transistor M05 is electrically connected to the first power source terminal PVDD, and a second pole of the fifth switching transistor M05 is electrically connected to the first pole of the driving transistor M0.

A first terminal of the storage capacitor C0 is electrically connected to the first power supply terminal PVDD, and a second terminal of the storage capacitor C0 is electrically connected to the gate of the driving transistor M0.

Further, as shown in fig. 6, the pixel circuit 111 may further include: the sixth switching transistor M06. A gate of the sixth switching transistor M06 is electrically connected to the second SCAN signal terminal SCAN2, a first electrode of the sixth switching transistor M06 is electrically connected to the initialization signal terminal VINIT, and a second electrode of the sixth switching transistor M06 is electrically connected to the first electrode of the light emitting device L.

Further, in order to reduce the influence of the leakage current on the voltage of the gate of the driving transistor, in a specific implementation, as shown in fig. 5 and fig. 6, the first switching transistor M01 and the third switching transistor M03 may be transistors with a dual-gate structure, so that the leakage current may be reduced, and thus the instability of the voltage of the node N1 (i.e., the gate of the driving transistor M0) may be reduced, and the stability of the pixel circuit 111 may be improved.

Fig. 5 is a circuit timing diagram corresponding to the pixel circuit 111 shown in fig. 6, as shown in fig. 3. The operation of the pixel circuit 111 may include: t01, T02 and T03. The three stages of T01, T02, and T03 may refer to the above working process, and are not described herein.

The above is merely to illustrate the specific structure of the pixel circuit 111 provided in the embodiment of the present invention, and it is needless to say that in practical applications, the pixel circuit 111 may also adopt another structure capable of compensating the threshold voltage of the driving transistor M0, and the structure is not limited herein.

It is generally necessary to apply a corresponding signal to the pixel circuit 111 to make the pixel circuit 111 drive the light emitting device to emit light. For example, it is common to input a DATA signal to the DATA input terminal DATA of the pixel circuit 111 using a DATA line, input different gate SCAN signals to the first SCAN signal terminal SCAN1 and the second SCAN signal terminal SCAN2 of the pixel circuit 111 using different gate lines, and input a signal to the emission control signal terminal EM of the pixel circuit 111 using an emission control signal line to drive the light emitting device to emit light. A high-voltage power supply signal is input to the first power supply terminal PVDD of the pixel circuit 111 using a power supply voltage signal line (e.g., PVDD signal line), a low-voltage power supply signal is input to the cathode of the light emitting device L using a low-voltage power supply line (e.g., PVSS signal line), a signal is input to the reference signal terminal VREF of the pixel circuit 111 using a reference voltage signal line, and an initialization signal is input to the initialization signal terminal VINIT of the pixel circuit 111 using an initialization signal line. Of course, the present invention includes, but is not limited to, this.

In specific implementation, in the embodiment of the present invention, as shown in fig. 5 to fig. 7, the display area may further include: a plurality of gate lines 141, a plurality of data lines 142, a power voltage signal line 143, and a plurality of reference voltage signal lines 144-k independent of each other; among them, the gate line 141 is used to transmit a gate SCAN signal to input different gate SCAN signals to the first SCAN signal terminal SCAN1 and the second SCAN signal terminal SCAN2 of the pixel circuits 111 in the display region row by row. The power supply voltage signal line 143 is used to transmit a first fixed voltage signal (e.g., a high voltage power supply signal) to input the high voltage power supply signal to the first power supply terminals PVDD of all the pixel circuits 111 in the display area. The DATA input terminals of the pixel circuits 111 of a column of the sub-pixels 110 in the display area are electrically connected to a DATA line 142, so as to input DATA signals to the DATA input terminals DATA of the electrically connected pixel circuits 111 through the DATA line 142. The reference voltage signal line 144-k is used to transmit a second fixed voltage signal to input a signal to the reference signal terminal VREF of the pixel circuit 111.

Exemplarily, as shown in fig. 5 to 7 in combination, the pixel circuits 111 in the display region may be made to share the power supply voltage signal line 143. That is, the pixel circuits 111 in the first and second sub display areas AA-1 and AA-2 are electrically connected to the power voltage signal line 143, and the power voltage signal lines 143 in the first and second sub display areas AA-1 and AA-2 are electrically connected to each other. Similarly, the pixel circuits 111 in the first sub-display area AA-1 and the second sub-display area AA-2 share the low voltage power line.

Illustratively, as shown in fig. 5 to 7, the gate line 141 is shared by the pixel circuits 111 in the sub-pixels 110 in the same row in the display region. That is, the first SCAN signal terminal SCAN1 of the pixel circuits 111 in the same row in the first sub-display area AA-1 and the second sub-display area AA-2 is electrically connected to one gate line 141, and the second SCAN signal terminal SCAN2 is electrically connected to another gate line 141, i.e., the gate line 141 electrically connected to the first SCAN signal terminal SCAN1 of the pixel circuits 111 in the same row in the first sub-display area AA-1 and the second sub-display area AA-2 is not disconnected, and the gate line 141 electrically connected to the second SCAN signal terminal SCAN2 of the pixel circuits 111 in the same row in the first sub-display area AA-1 and the second sub-display area AA-2 is also not disconnected.

Illustratively, as shown in fig. 5 to 7, the reference signal terminals VREF of all the pixel circuits 111 in one sub-display area are electrically connected to the same reference voltage signal line 144-k correspondingly. For example, the first sub-display area AA-1 corresponds to the reference voltage signal line 144-1, and the reference signal terminals VREF of all the pixel circuits 111 in the first sub-display area AA-1 are electrically connected to the same reference voltage signal line 144-1 correspondingly. The second sub-display area AA-2 corresponds to the reference voltage signal line 144-2, and the reference signal terminals VREF of all the pixel circuits 111 in the second sub-display area AA-2 are electrically connected to the same reference voltage signal line 144-2 correspondingly.

In practical implementation, in the embodiment of the present invention, as shown in fig. 7, the signal transmission line may include: with reference to the voltage signal line 144-k, the control voltage input terminal CSI-k may include: the reference voltage input terminal VREFI-k, the control voltage output terminal CSO-k may include: and a reference voltage output end VREFO-k. And, the reference voltage signal line 144-k in each sub-display area AA-k is electrically connected to one reference voltage output terminal VREFO-k of the driving chip 130-k through a corresponding one of the reference voltage input terminals VREFI-k. For example, the reference voltage signal line 144-1 in the first sub-display area AA-1 is electrically connected to the reference voltage output terminal VREFO-1 of the first driving chip 130-1 through the corresponding reference voltage input terminal VREFI-1. The reference voltage signal line 144-2 in the second sub-display area AA-2 is electrically connected to the reference voltage output terminal VREFO-2 of the second driver chip 130-2 through the corresponding reference voltage input terminal VREFI-2.

In particular implementation, in the embodiment of the present invention, as shown in fig. 7, the control circuit 120 may include a plurality of first auxiliary output terminals FZ 1-k; a first auxiliary output terminal FZ1-k is electrically connected to a reference voltage input terminal VREFI-k corresponding to one of the sub-display areas AA-k. For example, the control circuit 120 includes first auxiliary outputs FZ1-1 and FZ 1-2; the first auxiliary output end FZ1-1 corresponds to the first sub-display area AA-1, and the first auxiliary output end FZ1-1 is electrically connected to the reference voltage input end VREFI-1. The first auxiliary output terminal FZ1-2 corresponds to the second sub-display area AA-2, and the first auxiliary output terminal FZ1-2 is electrically connected to the reference voltage input terminal VREFI-2.

In specific implementation, in the embodiment of the present invention, as shown in fig. 8, the control circuit 120 may include: a first sub-reference control circuit 121-1 corresponding to the first sub-display area AA-1, and a second sub-reference control circuit 121-2 corresponding to the second sub-display area AA-2; wherein,

the input terminal of the first sub-reference control circuit 121-1 is electrically connected to the first control signal terminal CH1, the second control signal terminal CH2 and the first light-emitting cutoff signal input terminal EL1, respectively; the output terminal of a first sub-reference control circuit 121-1 is a first auxiliary output terminal FZ 1-1; the first sub-reference control circuit 121-1 is configured to provide the signal of the first light-emitting-cutoff signal input terminal EL1 to the corresponding reference voltage input terminal VREFI-1 according to the signals of the first control signal terminal CH1 and the second control signal terminal CH2 in the first operating state; and disconnecting the first light emission cut-off signal input terminal EL1 from the corresponding reference voltage input terminal VREFI-1 in the second operating state;

the input terminal of the second sub-reference control circuit 121-2 is electrically connected to the third control signal terminal CH3, the fourth control signal terminal CH4 and the second light-emission-cutoff signal input terminal EL2, respectively; the output terminal of one second sub-reference control circuit 121-2 is another first auxiliary output terminal FZ 1-2; and the second sub-reference control circuit 121-2 is configured to disconnect the second light-emission-off signal input terminal EL2 from the corresponding reference voltage input terminal VREFI-2 in both the first operating state and the second operating state.

In order to reduce the signal line arrangement and improve the integration, in the embodiment of the invention, as shown in fig. 8, the first driving chip 130-1 is used to apply corresponding signals to the first control signal terminal CH1, the fourth control signal terminal CH4 and the second light-emitting-off signal input terminal EL2, respectively. In this way, by multiplexing the first driving chip 130-1 to load the first control signal terminal CH1, the fourth control signal terminal CH4, and the second light-emitting-cutoff signal input terminal EL2 with corresponding signals, the arrangement of signal terminals can be reduced, the occupied space of signal lines can be reduced, and the integration level can be improved.

In order to reduce the signal line arrangement and improve the integration, in the embodiment of the invention, as shown in fig. 8, the second driving chip 130-2 is used to apply corresponding signals to the second control signal terminal CH2, the third control signal terminal CH3 and the first light-emitting-cutoff signal input terminal EL1, respectively. In this way, by multiplexing the second driving chip 130-2 to load the second control signal terminal CH2, the third control signal terminal CH3, and the first light-emitting cut-off signal input terminal EL1 with corresponding signals, the arrangement of signal terminals can be reduced, the occupied space of signal lines can be reduced, and the integration level can be improved.

In order to reduce the signal line arrangement and improve the integration, in the embodiment of the invention, as shown in fig. 9, the first control signal terminal CH1 and the second light-emission-off signal input terminal EL2 may be set as the same signal terminal, that is, the first driver chip 130-1 inputs signals to the first control signal terminal CH1 and the second light-emission-off signal input terminal EL2 by using the same pin. Thus, the design difficulty of the first driving chip 130-1 can be reduced, the number of signal terminals can be reduced, and the occupied space of signal lines can be reduced.

In order to reduce the signal line arrangement and improve the integration, in the embodiment of the invention, as shown in fig. 9, the third control signal terminal CH3 and the first light-emitting-cutoff signal input terminal EL1 may be the same signal terminal, that is, the second driver chip 130-2 uses the same pin to input signals to the third control signal terminal CH3 and the first light-emitting-cutoff signal input terminal EL 1. Thus, the design difficulty of the second driving chip 130-2 can be reduced, the number of signal terminals can be reduced, and the occupied space of signal lines can be reduced.

In practical implementation, in the embodiment of the present invention, as shown in fig. 10, the first sub-reference control circuit 121-1 may include: a first resistor R1 and a first transistor M1; a first end of the first resistor R1 is electrically connected to the first control signal terminal CH1, and a second end of the first resistor R1 is electrically connected to the second control signal terminal CH 2; the gate of the first transistor M1 is electrically connected to the first control signal terminal CH1, the first pole of the first transistor M1 is electrically connected to the first light-emitting-cutoff signal input terminal EL1, and the second pole of the first transistor M1 is used as the corresponding first auxiliary output terminal, i.e., the second pole of the first transistor M1 is used as the first auxiliary output terminal FZI-1 of the first sub-reference control circuit 121-1.

In practical implementation, in the embodiment of the present invention, the first resistor R1 may divide the voltage between the first control signal terminal CH1 and the second control signal terminal CH 2. In addition, when the first control signal terminal CH1 and the second control signal terminal CH2 are directly conducted, the current flowing through the first control signal terminal CH1 and the second control signal terminal CH2 is large, and the first resistor R1 is provided to prevent the element from being adversely affected by the large current.

In specific implementation, in the embodiment of the present invention, as shown in fig. 10, the first transistor M1 may be configured as a P-type transistor. Also, the first transistor M1 may supply the signal of the first light emission off signal input terminal EL1 to the first auxiliary output terminal FZI-1 of the first sub-reference control circuit 121-1 under the control of the signal of its gate.

In practical implementation, in the embodiment of the present invention, as shown in fig. 10, the second sub-reference control circuit 121-2 may include: a second resistor R2 and a second transistor M2; a first end of the second resistor R2 is electrically connected to the third control signal terminal CH3, and a second end of the second resistor R2 is electrically connected to the fourth control signal terminal CH 4; the gate of the second transistor M2 is electrically connected to the third control signal terminal CH3, the first pole of the second transistor M2 is electrically connected to the second light-emission-off signal input terminal EL2, and the second pole of the second transistor M2 is used as the corresponding first auxiliary output terminal, i.e., the second pole of the second transistor M2 is used as the first auxiliary output terminal FZI-2 of the second sub-reference control circuit 121-2.

In practical implementation, in the embodiment of the present invention, the second resistor R2 may divide the voltage between the third control signal terminal CH3 and the fourth control signal terminal CH 4. In addition, when the third control signal terminal CH3 and the fourth control signal terminal CH4 are normally directly turned on, the current flowing through the paths of the third control signal terminal CH3 and the fourth control signal terminal CH4 is large, and the second resistor R2 is provided to prevent the element from being adversely affected by the large current.

In specific implementation, in the embodiment of the present invention, as shown in fig. 10, the second transistor M2 may be configured as a P-type transistor. Also, the second transistor M2 may supply the signal of the second light emission off signal input terminal EL2 to the first auxiliary output terminal FZI-2 of the second sub-reference control circuit 121-2 under the control of the signal of its gate.

It should be noted that fig. 8 to 10 only illustrate the reference voltage signal line 144-k144-1 in the first sub-display area AA-1 and the reference voltage signal line 144-k144-2 in the second sub-display area AA-2, and the remaining signal lines are not illustrated.

The above is merely to illustrate the specific structure of the control circuit 120 provided in the embodiment of the present invention, and in the implementation, the specific structure of the control circuit 120 is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

In order to simplify the manufacturing process, in the embodiment of the present invention, as shown in fig. 5, 6 and 10, all the transistors may be configured as P-type transistors. Alternatively, all the transistors may be provided as N-type transistors. In specific implementation, the P-type transistor is turned off under the action of a high-level signal and is turned on under the action of a low-level signal; the N-type transistor is turned on under the action of a high-level signal and is turned off under the action of a low-level signal.

Note that, each Transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), and is not limited herein. In a specific implementation, a first pole of each transistor can be used as a source and a second pole as a drain according to a signal of a gate of each transistor and the type of the transistor; or the first pole is used as the drain and the second pole is used as the source, which is not specifically distinguished here.

The following describes the operation of the display panel provided by the embodiment of the present invention by taking the structure of the display panel shown in fig. 10 as an example, and combining the pixel circuit 111 shown in fig. 6 and the circuit timing diagram shown in fig. 3.

When the first sub-display area AA-1 and the second sub-display area AA-2 are not folded, i.e., are in the unfolded state, the first driving chip 130-1 is turned on to input a high level signal to the first control signal terminal CH1 and the second light-emitting-cutoff signal input terminal EL2, and the first driving chip 130-1 inputs a low level signal to the fourth control signal terminal CH 4. Also, the second driver chip 130-2 is turned on to input a high level signal to the third control signal terminal CH3 and the first light-emitting-cutoff signal input terminal EL1, and the second driver chip 130-2 inputs a low level signal to the second control signal terminal CH 2.

Since the first control signal terminal CH1 is a high-level signal and the second control signal terminal CH2 is a low-level signal, the first control signal terminal CH1 and the second control signal terminal CH2 are turned on through the first resistor R1, so that the signal at the gate of the first transistor M1 is a high-level signal at the first control signal terminal CH1, which causes the first transistor M1 to be turned off, thereby preventing the high-level signal input from the first light-emitting cut-off signal input terminal EL1 from being input into the first sub-display area AA-1. In addition, the first driving chip 130-1 inputs a low voltage signal to the reference voltage input terminal VREFI-1 corresponding to the first sub-display area AA-1, and inputs a corresponding data signal to the data line 142, so that the pixel circuit 111 in the first sub-display area AA-1 operates normally, thereby implementing normal display. The operation of one pixel circuit 111 in the first sub-display area AA-1 will be described as an example. In the stage T01, the signal of the second SCAN signal terminal SCAN2 is a high level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned off. The signal of the emission control signal terminal EM is a high level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned off. The signal at the first SCAN signal terminal SCAN1 is a low level signal, and the first switching transistor M01 is turned on to provide the signal at the low voltage of the reference signal terminal VREF to the node N1 (i.e., the gate of the driving transistor M0).

In the period T02, the signal at the first SCAN signal terminal SCAN1 is a high level signal, and the first switching transistor M01 is turned off. The signal of the emission control signal terminal EM is a high level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned off. The signal of the second SCAN signal terminal SCAN2 is a low level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned on. The signal voltage Vdata of the DATA input terminal DATA is input to the node N2 through the second switching transistor M02, and the node N1 is charged through the third switching transistor M03 and the driving transistor M0, so that the voltage of the node N1 is Vdata + | Vth |. The signal of the initialization signal terminal VINIT is input to the anode of the light emitting device through the sixth switching transistor M06 to initialize the light emitting device.

In the period T03, the signal at the first SCAN signal terminal SCAN1 is a high level signal, and the first switching transistor M01 is turned off. The signal of the second SCAN signal terminal SCAN2 is a high level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned off. The signal of the light emission control signal terminal EM is a low level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned on, so that the driving transistor M0 generates a driving current according to the voltage of the node N1 and the voltage of the first power source terminal PVDD to drive the light emitting device L to emit light.

Since the third control signal terminal CH3 is a high-level signal and the fourth control signal terminal CH4 is a low-level signal, the third control signal terminal CH3 and the fourth control signal terminal CH4 are turned on through the second resistor R2, so that the signal at the gate of the second transistor M2 is a high-level signal at the third control signal terminal CH3, and the second transistor M2 is turned off, thereby preventing the high-level signal input from the second light-emission-off signal input terminal EL2 from being input into the second sub-display area AA-2. In addition, the second driving chip 130-2 inputs a low voltage signal to the reference voltage input terminal VREFI-2 corresponding to the second sub-display area AA-2, and inputs a corresponding data signal to the data line 142, so that the pixel circuit 111 in the second sub-display area AA-2 operates normally, thereby implementing normal display. The working process of the pixel circuit 111 in the second sub-display area AA-2 may be substantially the same as the working process of the pixel circuit 111 in the first sub-display area AA-1, and the pixel circuits 111 in the same row in the first sub-display area AA-1 and the second sub-display area AA-2 work simultaneously to drive the light emitting device to emit light, which is not described herein again.

When the first sub-display area AA-1 and the second sub-display area AA-2 are folded along the folding axis L1, i.e., in the folded state, the first driving chip 130-1 is turned off, and stops outputting any signal. The first control signal terminal CH1, the second light-emission-cutoff signal input terminal EL2, and the fourth control signal terminal CH4 are in a floating state. The second driver chip 130-2 is turned on, and inputs a high level signal to the third control signal terminal CH3 and the first light-emitting-cutoff signal input terminal EL1, and the second driver chip 130-2 inputs a low level signal to the second control signal terminal CH 2.

Since the third control signal terminal CH3 is a high-level signal and the fourth control signal terminal CH4 is floating, the third control signal terminal CH3 is disconnected from the fourth control signal terminal CH4, so that the signal at the gate of the second transistor M2 is a high-level signal at the third control signal terminal CH3, and the second transistor M2 is turned off, thereby preventing the high-level signal input from the second light-emitting-off signal input terminal EL2 from being input into the second sub-display area AA-2. In addition, the second driving chip 130-2 inputs a low voltage signal to the reference voltage input terminal VREFI-2 corresponding to the second sub-display area AA-2, and inputs a corresponding data signal to the data line 142, so that the pixel circuit 111 in the second sub-display area AA-2 operates normally, thereby implementing normal display. The working process of the pixel circuit 111 in the second sub-display area AA-2 may be substantially the same as the working process of the pixel circuit 111 in the second sub-display area AA-1 in the unfolded state, and details thereof are not repeated herein.

Since the first control signal terminal CH1 is floating and the second control signal terminal CH2 is a low level signal, the first control signal terminal CH1 is disconnected from the second control signal terminal CH2, so that the signal at the gate of the first transistor M1 is a low level signal at the second control signal terminal CH2, and the first transistor M1 is turned on, so that the high voltage signal inputted from the first light-emitting cutoff signal input terminal EL1 is inputted into the first sub-display area AA-1, and the high voltage signal is inputted from the reference signal terminals VREF of all the pixel circuits 111 in the first sub-display area AA-1. Thus, each row of pixel circuits 111 in the first sub-display area AA-1 inputs the high voltage signal of the reference signal terminal VREF to the gate of the driving transistor (i.e., the node N1) during the period T01. Also, in the stages T02 and T03, the node N1 is held at a high level signal by the storage capacitor C0. Therefore, the driving transistor is controlled to be cut off in the stages from T01 to T03, so that the current generated by the driving transistor M0 is avoided, and the light emitting device is prevented from emitting light. The operation of one pixel circuit 111 in the first sub-display area AA-1 will be described as an example.

In the stage T01, the signal of the second SCAN signal terminal SCAN2 is a high level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned off. The signal of the emission control signal terminal EM is a high level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned off. The signal at the first SCAN signal terminal SCAN1 is a low level signal, and the first switching transistor M01 is turned on to provide the high voltage signal at the reference signal terminal VREF to the node N1 (i.e., the gate of the driving transistor M0) to turn off the driving transistor M0.

In the period T02, the signal at the first SCAN signal terminal SCAN1 is a high level signal, and the first switching transistor M01 is turned off. The signal of the emission control signal terminal EM is a high level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned off. The signal of the second SCAN signal terminal SCAN2 is a low level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned on. The DATA input DATA is floating, the node N1 is not charged, and the node N1 is kept at the high voltage signal, so that the driving transistor M0 is turned off. The signal of the initialization signal terminal VINIT is input to the anode of the light emitting device through the sixth switching transistor M06 to initialize the light emitting device.

In the period T03, the signal at the first SCAN signal terminal SCAN1 is a high level signal, and the first switching transistor M01 is turned off. The signal of the second SCAN signal terminal SCAN2 is a high level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned off. The signal of the emission control signal terminal EM is a low level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned on. Also, the node N1 is maintained at the high voltage signal to turn off the driving transistor M0, and no current is generated, so that the light emitting device L can be prevented from emitting light.

Fig. 11 is a schematic structural diagram of still other display panels provided in an embodiment of the present invention, which is modified from the embodiment in the foregoing embodiment. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In practical implementation, in the embodiment of the present invention, as shown in fig. 11, the signal transmission line may also include: and a data line 142. The control voltage input terminal CSI-k may include: a data voltage input terminal DAIm-k (M is greater than or equal to 1 and less than or equal to M, M and M are integers, M is the total number of the data lines 142 in one sub-display area, and M is 4 in fig. 11 as an example) corresponding to each data line 142. The control voltage output terminal CSO-k may include: data voltage output terminals DAOm-k corresponding to each data line 142 one to one; wherein one data voltage input terminal DAIm-k is electrically connected to one data voltage output terminal DAOm-k.

For example, as shown in FIG. 11, the first sub-display area AA-1 corresponds to the data voltage input terminal DAIm-1, wherein the data voltage input terminal DAI1-1 is electrically connected to the data voltage output terminal DAO1-1, the data voltage input terminal DAI2-1 is electrically connected to the data voltage output terminal DAO2-1, the data voltage input terminal DAI3-1 is electrically connected to the data voltage output terminal DAO3-1, and the data voltage input terminal DAI4-1 is electrically connected to the data voltage output terminal DAO 4-1.

For example, as shown in FIG. 11, the second sub-display area AA-2 corresponds to the data voltage input terminal DAIm-2, wherein the data voltage input terminal DAI1-2 is electrically connected to the data voltage output terminal DAO1-2, the data voltage input terminal DAI2-2 is electrically connected to the data voltage output terminal DAO2-2, the data voltage input terminal DAI3-2 is electrically connected to the data voltage output terminal DAO3-2, and the data voltage input terminal DAI4-2 is electrically connected to the data voltage output terminal DAO 4-2.

In specific implementation, in the embodiment of the present invention, as shown in fig. 11, the control circuit 120 may include: a third transistor M3M-k corresponding to each data line 142, a first sub data control circuit 122-1 corresponding to the first sub display area AA-1, and a second sub data control circuit 122-2 corresponding to the second sub display area AA-2; the first pole of each third transistor M3M-k is electrically connected to the corresponding data voltage input terminal DAIm-k, the second poles of all the third transistors M3M-1 corresponding to the first sub display area AA-1 are electrically connected to the third light emission off signal input terminal EL3, and the second poles of all the third transistors M3M-2 corresponding to the second sub display area AA-2 are electrically connected to the fourth light emission off signal input terminal EL 4.

In practical implementation, as shown in fig. 11, in the embodiment of the invention, the first sub-data control circuit 122-1 is electrically connected to the fifth control signal terminal CH5, the sixth control signal terminal CH6, and the gate of the third transistor M3M-1 corresponding to the first sub-display area AA-1, respectively; the first sub-data control circuit 122-1 is configured to control the electrically connected third transistor M3M-1 to be turned on according to signals of the fifth control signal terminal CH5 and the sixth control signal terminal CH6 in the first working state; in the second operating state, the third transistor M3M-1, which controls the electrical connection, is turned off.

In practical implementation, as shown in fig. 11, in the embodiment of the invention, the second sub-data control circuit 122-2 is electrically connected to the seventh control signal terminal CH7, the eighth control signal terminal CH8, and the gate of the third transistor M3M-2 corresponding to the second sub-display area AA-2, respectively; the second sub-data control circuit 122-2 is used for controlling the third transistor M3M-2 to be turned off according to the signals of the seventh control signal terminal CH7 and the eighth control signal terminal CH8 in the first operating state and the second operating state, respectively.

In order to reduce the arrangement of the signal lines and improve the integration, in the embodiment of the invention, as shown in fig. 11, the first driving chip 130-1 is used to apply corresponding signals to the fifth control signal terminal CH5, the eighth control signal terminal CH8 and the fourth light-emitting-off signal input terminal EL4, respectively. In this way, by multiplexing the first driving chip 130-1 to load the corresponding signals to the fifth control signal terminal CH5, the eighth control signal terminal CH8, and the fourth light-emitting-cutoff signal input terminal EL4, the arrangement of the signal terminals can be reduced, the occupied space of the signal lines can be reduced, and the integration level can be improved.

In order to reduce the arrangement of the signal lines and improve the integration, in the embodiment of the invention, as shown in fig. 11, the second driving chip 130-2 is used to apply corresponding signals to the sixth control signal terminal CH6, the seventh control signal terminal CH7 and the third light-emitting-off signal input terminal EL3, respectively. In this way, the multiplexing second driving chip 130-2 loads corresponding signals to the sixth control signal terminal CH6, the seventh control signal terminal CH7, and the third light-emitting-cutoff signal input terminal EL3, respectively, so that the arrangement of signal terminals can be reduced, the occupied space of signal lines can be reduced, and the integration level can be improved.

In order to reduce the signal line arrangement and improve the integration, in the embodiment of the present invention, as shown in fig. 11, the fifth control signal terminal CH5 and the fourth light-emission-off signal input terminal EL4 may be set as the same signal terminal, that is, the first driver chip 130-1 inputs signals to the fifth control signal terminal CH5 and the fourth light-emission-off signal input terminal EL4 by using the same pin. Thus, the design difficulty of the first driving chip 130-1 can be reduced, the number of signal terminals can be reduced, and the occupied space of signal lines can be reduced.

In order to reduce the signal line arrangement and improve the integration, in the embodiment of the invention, as shown in fig. 11, the seventh control signal terminal CH7 and the third light-emitting-off signal input terminal EL3 may be the same signal terminal, that is, the second driver chip 130-2 uses the same pin to input signals to the seventh control signal terminal CH7 and the third light-emitting-off signal input terminal EL 3. Thus, the design difficulty of the second driving chip 130-2 can be reduced, the number of signal terminals can be reduced, and the occupied space of signal lines can be reduced.

In specific implementation, in the embodiment of the present invention, as shown in fig. 12, the first sub-data control circuit 122-1 may include: a third resistor R3; a first end of the third resistor R3 is electrically connected to the fifth control signal terminal CH5 and the gate of the corresponding third transistor M3, and a second end of the third resistor R3 is electrically connected to the sixth control signal terminal CH 6.

In practical implementation, in the embodiment of the present invention, the third resistor R3 may divide the voltage between the fifth control signal terminal CH5 and the sixth control signal terminal CH 6. In addition, when the fifth control signal terminal CH5 and the sixth control signal terminal CH6 are directly conducted, the current flowing through the paths of the fifth control signal terminal CH5 and the sixth control signal terminal CH6 is large, and the third resistor R3 is provided to avoid the adverse effect of the large current on the device.

In specific implementation, in the embodiment of the present invention, as shown in fig. 12, the second sub-data control circuit 122-2 may include: a fourth resistor R4; a first end of the fourth resistor R4 is electrically connected to the seventh control signal terminal CH7 and the gate of the corresponding third transistor M3, and a second end of the fourth resistor R4 is electrically connected to the eighth control signal terminal CH 8.

In practical implementation, in the embodiment of the present invention, the fourth resistor R4 may divide the voltage between the seventh control signal terminal CH7 and the eighth control signal terminal CH 8. In addition, when the seventh control signal terminal CH7 and the eighth control signal terminal CH8 are directly turned on, the current flowing through the paths of the seventh control signal terminal CH7 and the eighth control signal terminal CH8 is large, and the fourth resistor R4 is provided to prevent the element from being adversely affected by the large current.

In practical implementation, in the embodiment of the present invention, the third transistor M3 may be configured as a P-type transistor. Of course, the third transistor M3 may be an N-type transistor, which is not limited herein.

In practical implementation, in the embodiment of the present invention, the voltage V3 of the signal at the third light-emission-off signal input terminal may be greater than the voltage Vdd of the signal transmitted on the power supply voltage signal line 143, that is, V3> Vdd. This turns off the driving transistor at the stage T03, thereby preventing the light emitting device from being driven to emit light.

It should be noted that fig. 11 and 12 only illustrate the data line 142142 in the first sub-display area AA-1 and the second sub-display area AA-2, and the remaining signal lines are not illustrated.

The following describes the operation of the display panel provided by the embodiment of the present invention by taking the structure of the display panel shown in fig. 12 as an example, and combining the pixel circuit 111 shown in fig. 6 and the circuit timing diagram shown in fig. 3.

When the first sub-display area AA-1 and the second sub-display area AA-2 are not folded, i.e., are in the unfolded state, the first driving chip 130-1 is turned on to input a high level signal to the fifth control signal terminal CH5 and the fourth light-emitting-cutoff signal input terminal EL4, and the first driving chip 130-1 inputs a low level signal to the eighth control signal terminal CH 8. Also, the second driver chip 130-2 is turned on to input a high level signal to the seventh control signal terminal CH7 and the third light-emission-off signal input terminal EL3, and the second driver chip 130-2 inputs a low level signal to the sixth control signal terminal CH 6.

Since the fifth control signal terminal CH5 is a high-level signal and the sixth control signal terminal CH6 is a low-level signal, the fifth control signal terminal CH5 and the sixth control signal terminal CH6 are turned on through the third resistor R3, so that the signals at the gates of the third transistors M31-1 to M34-1 are high-level signals at the fifth control signal terminal CH5, and the third transistors M31-1 to M34-1 are turned off, thereby preventing the high-level signal input from the third light-emitting cut-off signal input terminal EL3 from being input into the first sub-display area AA-1. In addition, the first driving chip 130-1 inputs a low voltage signal to the reference voltage input terminal VREF1-1 corresponding to the first sub-display area AA-1, and inputs a corresponding data signal to the data line 142, so that the pixel circuit 111 in the first sub-display area AA-1 operates normally, thereby implementing normal display. It should be noted that the working process of the first sub-display area AA-1 in the unfolded state in this embodiment is substantially the same as the working process of the first sub-display area AA-1 in the unfolded state in the above embodiment, and no further description is provided herein.

Since the seventh control signal terminal CH7 is a high-level signal and the eighth control signal terminal CH8 is a low-level signal, the seventh control signal terminal CH7 and the eighth control signal terminal CH8 are turned on through the fourth resistor R4, so that the signals at the gates of the third transistors M31-2 to M34-2 are high-level signals at the seventh control signal terminal CH7, and the third transistors M31-2 to M34-2 are turned off, thereby preventing the high-level signal input from the fourth light-emitting off signal input terminal EL4 from being input into the second sub-display area AA-2. In addition, the second driving chip 130-2 inputs a low voltage signal to the reference voltage input terminal VREF-2 corresponding to the second sub-display area AA-2, and inputs a corresponding data signal to the data line 142, so that the pixel circuit 111 in the second sub-display area AA-2 operates normally, thereby implementing normal display. It should be noted that the working process of the second sub-display area AA-2 in the unfolded state in this embodiment is substantially the same as the working process of the second sub-display area AA-2 in the unfolded state in the above embodiment, and no further description is provided herein.

When the first sub-display area AA-1 and the second sub-display area AA-2 are folded along the folding axis L1, i.e., in the folded state, the first driving chip 130-1 is turned off, and stops outputting any signal. The fifth control signal terminal CH5, the fourth light-emission-cutoff signal input terminal EL4, and the eighth control signal terminal CH8 are in a floating state. The second driver chip 130-2 is turned on, and inputs a high level signal to the seventh control signal terminal CH7 and the third light-emission-off signal input terminal EL3, and the second driver chip 130-2 inputs a low level signal to the sixth control signal terminal CH 6.

Since the seventh control signal terminal CH7 is a high level signal and the eighth control signal terminal CH8 is floating, the seventh control signal terminal CH7 is disconnected from the eighth control signal terminal CH8, so that the signals at the gates of the third transistors M31-2 to M34-2 are high level signals at the seventh control signal terminal CH7, which causes the third transistors M31-2 to M34-2 to be turned off, thereby disconnecting the fourth light-emitting-off signal input terminal EL4 from the data voltage input terminals DAI1-2 to DAI4-2 corresponding to the second sub-display area AA-2. In addition, the second driving chip 130-2 inputs a low voltage signal to the reference voltage input terminal corresponding to the second sub-display area AA-2, and inputs a corresponding data signal to the data line 142, so that the pixel circuit 111 in the second sub-display area AA-2 operates normally, thereby implementing normal display. The working process of the pixel circuit 111 in the second sub-display area AA-2 may be substantially the same as the working process of the pixel circuit 111 in the second sub-display area AA-2 in the unfolded state, and details thereof are not repeated herein.

Since the fifth control signal terminal CH5 is floating, and the sixth control signal terminal CH6 is a low-level signal, the fifth control signal terminal CH5 is disconnected from the sixth control signal terminal CH6, so that the signals at the gates of the third transistors M31-1 to M34-1 are low-level signals at the sixth control signal terminal CH6, and the third transistors M31-1 to M34-1 are turned on, so that the high-voltage signal inputted from the third light-emission-off signal input terminal EL3 is inputted to the corresponding DATA voltage input terminals DAI1-1 to DAI4-1, and the high-voltage signal inputted from the third light-emission-off signal input terminal EL3 is inputted to the DATA lines in the first sub-display area AA-1, so that the DATA input terminals DATA of all the pixel circuits 111 in the first sub-display area AA-1 are inputted with high-voltage signals. Thus, each row of pixel circuits 111 controls the driving transistor to be turned off during the period T03, so as to prevent the driving transistor M0 from generating current, and further prevent the light emitting device from emitting light. The operation of one pixel circuit 111 in the first sub-display area AA-1 will be described as an example.

In the stage T01, the signal of the second SCAN signal terminal SCAN2 is a high level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned off. The signal of the emission control signal terminal EM is a high level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned off. The signal at the first SCAN signal terminal SCAN1 is a low level signal, the first switch transistor M01 is turned on, and if the reference signal terminal VREF is floating, the signal at the reference signal terminal VREF is not inputted to the node N1 (i.e., the gate of the driving transistor M0).

In the period T02, the signal at the first SCAN signal terminal SCAN1 is a high level signal, and the first switching transistor M01 is turned off. The signal of the emission control signal terminal EM is a high level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned off. The signal of the second SCAN signal terminal SCAN2 is a low level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned on. The voltage V3 at the third light-emission-off signal input terminal is input to the DATA signal terminal DATA. The voltage V3 of the high voltage signal at the DATA input terminal DATA is input to the node N2 through the second switching transistor M02, and the node N1 is charged through the third switching transistor M03 and the driving transistor M0 so that the voltage at the node N1 is V3+ | Vth |. The signal of the initialization signal terminal VINIT is input to the anode of the light emitting device through the sixth switching transistor M06 to initialize the light emitting device.

In the period T03, the signal at the first SCAN signal terminal SCAN1 is a high level signal, and the first switching transistor M01 is turned off. The signal of the second SCAN signal terminal SCAN2 is a high level signal, and the second switching transistor M02, the third switching transistor M03 and the sixth switching transistor M06 are turned off. The signal of the emission control signal terminal EM is a low level signal, and the fourth switching transistor M04 and the fifth switching transistor M05 are turned on. The signal transmitted on the power supply voltage signal line 143 is input to the first electrode of the driving transistor through the first power supply terminal PVDD so that the voltage of the first electrode of the driving transistor is Vdd. Also, the voltage of the node N1 is maintained at V3+ | Vth |, since V3> Vdd, so that the driving transistor M0 is turned off, no current is generated, and thus the light emitting device L can be prevented from emitting light.

Based on the same inventive concept, an embodiment of the present invention further provides a liquid crystal display panel, including an opposite substrate and an array substrate that are oppositely disposed, and a liquid crystal layer located between the opposite substrate and the array substrate, where the array substrate is any one of the array substrates provided by the embodiments of the present invention.

Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The principle of the display device to solve the problem is similar to the display panel, so the implementation of the display device can be referred to the implementation of the display panel, and repeated details are not repeated herein.

In practical implementation, the display device provided in the embodiment of the present invention may be a mobile phone as shown in fig. 13. Of course, the display device provided in the embodiment of the present invention may also be any product or component having a display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A display panel, comprising: a display area and a non-display area surrounding the display area, the display area including: a plurality of sub-pixels and signal transmission lines; each of the sub-pixels includes a pixel circuit; the display area is divided into a plurality of sub-display areas, and the plurality of sub-display areas comprise a first sub-display area and a second sub-display area which correspond to each other;

the display area further includes: a plurality of gate lines and a power voltage signal line; the grid line is used for transmitting a grid scanning signal, and the power supply voltage signal line is used for transmitting a first fixed voltage signal; pixel circuits in the display region share the power supply voltage signal line; pixel circuits in the same row of the sub-pixels in the display area share a grid line;

the display panel has a first working state and a second working state;

in the second working state, the driving chip corresponding to the first sub-display area is started to enable the first sub-display area to display normally; the driving chip corresponding to the second sub-display area is started so as to enable the second sub-display area to display normally;

the display area further includes: a plurality of reference voltage signal lines independent of each other; the reference voltage signal line is used for transmitting a second fixed voltage signal; the reference signal terminals of all the pixel circuits in one sub-display area are correspondingly and electrically connected with the same reference voltage signal wire; the signal transmission line includes: the reference voltage signal line; the control voltage input terminal includes: a reference voltage input terminal; the control voltage output terminal includes: a reference voltage output terminal; the reference voltage signal wire in each sub-display area is electrically connected with one reference voltage output end of the driving chip through the corresponding reference voltage input end; the control circuit comprises a plurality of first auxiliary outputs; one of the first auxiliary output terminals is electrically connected with the reference voltage input terminal corresponding to one of the sub-display regions; or,

the display area further includes: a plurality of data lines; the signal transmission line includes: the data line; the control voltage input terminal includes: a data voltage input terminal corresponding to each data line one to one; the control voltage output terminal includes: a data voltage output terminal corresponding to each data line one to one; the data input ends of the pixel circuits of a column of sub-pixels in the display area are correspondingly and electrically connected with one data line; one of the data voltage input terminals is electrically connected to one of the data voltage output terminals; the control circuit includes: the third transistor corresponds to each data line one by one, the first sub-data control circuit corresponds to the first sub-display area, and the second sub-data control circuit corresponds to the second sub-display area; a first pole of each third transistor is electrically connected to the corresponding data voltage input terminal, second poles of all third transistors corresponding to the first sub-display region are electrically connected to the third light-emitting cut-off signal input terminal, and second poles of all third transistors corresponding to the second sub-display region are electrically connected to the fourth light-emitting cut-off signal input terminal; the first sub data control circuit is respectively electrically connected with a fifth control signal end, a sixth control signal end and a grid electrode of a third transistor corresponding to the first sub display area; the first sub-data control circuit is configured to control the third transistor electrically connected to the first sub-data control circuit to be turned on according to signals of the fifth control signal terminal and the sixth control signal terminal in the first working state; in the second working state, the third transistor which controls the electric connection is turned off; the second sub data control circuit is respectively electrically connected with a seventh control signal end, an eighth control signal end and a grid electrode of a third transistor corresponding to the second sub display area; and the second sub-data control circuit is configured to control the electrically connected third transistor to be turned off according to the signals of the seventh control signal terminal and the eighth control signal terminal in the first working state and the second working state, respectively.

2. The display panel according to claim 1, wherein the control circuit comprises: the first sub-reference control circuit corresponds to the first sub-display area, and the second sub-reference control circuit corresponds to the second sub-display area;

the input end of the first sub-reference control circuit is respectively and electrically connected with the first control signal end, the second control signal end and the first light-emitting cut-off signal input end; an output of said first sub-reference control circuit is said first auxiliary output; the first sub-reference control circuit is configured to provide a signal at the first light-emitting cut-off signal input end to the corresponding reference voltage input end according to signals at the first control signal end and the second control signal end in the first working state; and disconnecting the first light-emitting cut-off signal input end from the corresponding reference voltage input end in the second working state;

the input end of the second sub-reference control circuit is respectively and electrically connected with the third control signal end, the fourth control signal end and the second light-emitting cut-off signal input end; one output terminal of the second sub-reference control circuit is another first auxiliary output terminal; and the second sub-reference control circuit is used for disconnecting the second light-emitting cut-off signal input end from the corresponding reference voltage input end in the first working state and the second working state.

3. The display panel according to claim 2, wherein the first sub-display region corresponds to a first driving chip, and the second sub-display region corresponds to a second driving chip;

the first driving chip is used for loading corresponding signals to the first control signal end, the fourth control signal end and the second light-emitting cut-off signal input end respectively;

the second driving chip is used for loading corresponding signals to the second control signal end, the third control signal end and the first light-emitting cut-off signal input end respectively.

4. The display panel according to claim 3, wherein the first control signal terminal and the second light-emission-off signal input terminal are the same signal terminal; and/or the presence of a gas in the gas,

the third control signal end and the first light-emitting cut-off signal input end are the same signal end.

5. The display panel of any of claims 2-4, wherein the first sub-reference control circuit comprises: a first resistor and a first transistor; the first end of the first resistor is electrically connected with the first control signal end, and the second end of the first resistor is electrically connected with the second control signal end; the grid electrode of the first transistor is electrically connected with the first control signal end, the first electrode of the first transistor is electrically connected with the first light-emitting cut-off signal input end, and the second electrode of the first transistor is used as the corresponding first auxiliary output end; and/or the presence of a gas in the gas,

the second sub-reference control circuit includes: a second resistor and a second transistor; a first end of the second resistor is electrically connected to the third control signal end, and a second end of the second resistor is electrically connected to the fourth control signal end; the grid electrode of the second transistor is electrically connected with the third control signal end, the first electrode of the second transistor is electrically connected with the second light-emitting cut-off signal input end, and the second electrode of the second transistor is used as the corresponding first auxiliary output end.

6. The display panel of claim 5, wherein the first sub-reference control circuit comprises: when the first resistor and the first transistor are used, the first transistor is a P-type transistor;

the second sub-reference control circuit includes: and when the second resistor and the second transistor are used, the second transistor is a P-type transistor.

7. The display panel according to claim 1, wherein the first driving chip is configured to apply corresponding signals to the fifth control signal terminal, the eighth control signal terminal, and the fourth light-emission-off signal input terminal, respectively;

the second driving chip is used for loading corresponding signals to the sixth control signal end, the seventh control signal end and the third light-emitting cut-off signal input end respectively.

8. The display panel according to claim 7, wherein the fifth control signal terminal and the fourth light-emission-off signal input terminal are the same signal terminal; and/or the presence of a gas in the gas,

the seventh control signal end and the third light-emitting cut-off signal input end are the same signal end.

9. The display panel of claim 1, wherein the first sub-data control circuit comprises: a third resistor; a first end of the third resistor is electrically connected to the fifth control signal terminal and the gate of the corresponding third transistor, respectively, and a second end of the third resistor is electrically connected to the sixth control signal terminal; and/or the presence of a gas in the gas,

the second sub-data control circuit includes: a fourth resistor; a first end of the fourth resistor is electrically connected to the seventh control signal terminal and the gate of the corresponding third transistor, respectively, and a second end of the fourth resistor is electrically connected to the eighth control signal terminal.

10. The display panel according to claim 1, wherein the third transistor is a P-type transistor.

11. The display panel according to claim 1, wherein a voltage of a signal at the third light emission off signal input terminal is larger than a voltage of a signal transmitted on the power supply voltage signal line.

12. The display panel according to any one of claims 1 to 4, wherein in the first operation state, the first sub-display area and the second sub-display area are folded;

in the second working state, the first sub-display area and the second sub-display area are in an unfolded state.

13. The display panel according to claim 12, wherein the display panel further comprises: a folding shaft; wherein the first sub-display area and the second sub-display area are respectively located at two sides of the folding axis.

14. The display panel of any one of claims 1-4, wherein the pixel circuit further comprises: the driving circuit comprises a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a driving transistor and a storage capacitor;

the grid electrode of the first switching transistor is electrically connected with the first scanning signal end, the first electrode of the first switching transistor is electrically connected with the reference signal end, and the second electrode of the first switching transistor is electrically connected with the grid electrode of the driving transistor;

a gate electrode of the second switching transistor is electrically connected with the second scanning signal terminal, a first electrode of the second switching transistor is electrically connected with the data input terminal, and a second electrode of the second switching transistor is electrically connected with the first electrode of the driving transistor;

the grid electrode of the third switching transistor is electrically connected with the second scanning signal end, the first electrode of the third switching transistor is electrically connected with the grid electrode of the driving transistor, and the second electrode of the third switching transistor is electrically connected with the second electrode of the driving transistor;

the grid electrode of the fourth switching transistor is electrically connected with the light-emitting control signal end, the first electrode of the fourth switching transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the fourth switching transistor is electrically connected with the first electrode of the light-emitting device;

a grid electrode of the fifth switching transistor is electrically connected with the light-emitting control signal end, a first electrode of the fifth switching transistor is electrically connected with the first power supply end, and a second electrode of the fifth switching transistor is electrically connected with the first electrode of the driving transistor;

the first end of the storage capacitor is electrically connected with the first power supply end, and the second end of the storage capacitor is electrically connected with the grid electrode of the driving transistor.

15. A display device characterized by comprising the display panel according to any one of claims 1 to 14.