CN110809068A - Novel address distribution circuit - Google Patents
Novel address distribution circuit Download PDFInfo
- Publication number
- CN110809068A CN110809068A CN201911098490.2A CN201911098490A CN110809068A CN 110809068 A CN110809068 A CN 110809068A CN 201911098490 A CN201911098490 A CN 201911098490A CN 110809068 A CN110809068 A CN 110809068A
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- Prior art keywords
- address
- resistor
- controller
- interface
- filter capacitor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/50—Address allocation
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
The application relates to a novel address allocation circuit, which comprises a controller and an address identification module, wherein the address identification module is connected with one pin of the controller, and comprises an address identification resistor with an adjustable resistance value; the controller is characterized in that an address table is prestored in the controller, the resistance value of the address identification resistor is adjusted to enable the address identification module to output the level, the output level is sent to the controller, and the controller receives and reads the output level through a pin connected with the address identification module and corresponds the output level to the address table to convert the output level into an ID/IP address. The address identification module is connected with only one pin of the controller, so that multi-bit address allocation can be realized, address replacement and adjustment can be carried out without external interface equipment or a network, the size is small, the cost is low, and the maintenance is convenient.
Description
Technical Field
The invention relates to a novel address distribution circuit.
Background
The existing industrial internet-of-things controllers all need IP or ID addresses to work in a networking mode, and the currently commonly used address settings are generally divided into two types: 1. the memory mode is that the address is stored in the chip by software operation, if the address is changed, the address is given by an external interface, the original old address in the chip is erased by operating the software, and a new address is written in. 2. And presetting high and low levels by using port pins of the MCU or the CPU or the conversion chip, reading the preset values as addresses, and resetting the high and low levels of the port pins if the addresses need to be replaced.
The disadvantages of these two address allocation approaches are evident: first, if the controller is not networked or otherwise unable to interface with an external device, the address cannot be adjusted for a new address. In the second mode, more port resources need to be occupied, for example, 8 ports need to be occupied by 8-bit addresses, and 16 ports need to be occupied if 16-bit addresses are occupied, so that the cost is high and the size is large.
Disclosure of Invention
The invention aims to provide a novel address allocation circuit, which can realize multi-bit address allocation only by being connected with one pin of a controller, can replace and adjust addresses without external interface equipment or a network, and has the advantages of small volume, low cost and convenient maintenance.
In order to achieve the purpose, the invention provides the following technical scheme: a novel address allocation circuit comprises a controller and an address identification module connected with only one pin of the controller, wherein the address identification module comprises an address identification resistor with an adjustable resistance value; the controller is characterized in that an address table is prestored in the controller, the resistance value of the address identification resistor is adjusted to enable the address identification module to output the level, the output level is sent to the controller, and the controller receives and reads the output level through a pin connected with the address identification module and corresponds the output level to the address table to convert the output level into an ID/IP address.
Further, the address identification module is connected with a TX/AD pin of the controller.
Further, the address identification module comprises a first interface module connected with the controller and a second interface module in butt joint with the first interface module, and the second interface module comprises a second interface connected with the address identification resistor.
Further, the first interface module comprises a first interface, a first resistor, a second resistor and a filter capacitor set, wherein the first interface is in butt joint with the second interface, the first end of the first resistor is connected with the first end of the first interface, the second end of the first resistor is connected with a power supply, the first end of the filter capacitor set is connected with the first end of the first interface, the second end of the filter capacitor set is connected with the second end of the first interface and grounded, the first end of the second resistor is connected with the first end of the filter capacitor set, and the second end of the second resistor is connected with one pin of the controller.
Furthermore, the filter capacitor bank comprises a low-frequency filter capacitor connected with the second resistor, an intermediate-frequency filter capacitor connected with the low-frequency filter capacitor, and a high-frequency filter capacitor used for connecting the intermediate-frequency filter capacitor and the first interface.
Further, the first voltage is a voltage dividing resistor, and when the first interface module is in butt joint with the second interface module, the address identification resistor and the first resistor form a voltage dividing circuit.
Further, the second resistor is a current limiting resistor.
The invention has the beneficial effects that: the address identification module is provided with the controller and is connected with the controller, the address identification module comprises the address identification resistor, the change and the adjustment of the address in the controller can be realized through changing the resistance value of the address identification resistor, external interface equipment or a network is not needed, multi-bit address distribution can be realized, the size is small, the cost is low, and the maintenance is convenient.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is a block diagram of the novel address assignment circuit of the present invention.
Fig. 2 is a circuit diagram of the novel address assignment circuit of the present invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Referring to fig. 1 to 2, the novel address allocation circuit in a preferred embodiment of the present invention includes a controller 1 and an address identification module 2 connected to only one pin of the controller 1, so that other functional pins of the controller 1 are not occupied by the address identification module 2, thereby achieving the effects of miniaturization, low cost and simple maintenance of the whole circuit. In this embodiment, the controller 1 is a 20-pin MCU. Indeed, in other embodiments, the controller 1 may be other, and is not limited herein according to the actual situation.
The pin has an address recognition function and can communicate with the outside, and in this embodiment, the pin is a TX/AD pin of the controller 1 to fully utilize the resolution of the a/D converter and realize the recognition of the multi-bit address through the reading of the a/D converter. Indeed, in other embodiments, the pins may be other pins, and are not limited herein according to actual requirements. Wherein the address identification module 2 comprises an address identification resistor 23 with an adjustable resistor value. The controller 1 prestores an address table, adjusts the resistance value of the address identification resistor 23 to enable the address identification module 2 to output a level, and sends the output level to the controller 1, and the controller 1 receives and reads the output level through a pin connected with the address identification module 2 and corresponds the output level with the address table to convert the output level into an ID/IP address.
The address recognition module 2 includes a first interface module 21 connected to the controller 1 and a second interface module 22 interfacing with the first interface module 21, and the second interface module 22 includes a second interface P2 connected to the address recognition resistor 23. The first interface module 21 includes a first interface P1, a first resistor R1, a second resistor R2 and a filter capacitor bank, which are connected to the second interface P2, wherein a first end of the first resistor R1 is connected to a first end of the first interface P1, a second end of the first resistor R1 is connected to a power VCC, a first end of the filter capacitor bank is connected to a first end of the first interface P1, a second end of the filter capacitor bank is connected to a second end of the first interface P1 and grounded, a first end of the second resistor R2 is connected to a first end of the filter capacitor bank, and a second end of the second resistor R2 is connected to one of pins of the controller 1, i.e., to a TX/AD pin. In the present embodiment, the first port P1 and the second port P2 are two-pin ports. Indeed, in other embodiments, the first interface P1 and the second interface P2 may be other interfaces, and are not limited herein according to the actual situation. More specifically, the filter capacitor bank includes a low-frequency filter capacitor C1 connected to the second resistor R2, an intermediate-frequency filter capacitor C2 connected to the low-frequency filter capacitor C1, and a high-frequency filter capacitor C3 for connecting the intermediate-frequency filter capacitor C2 and the first port P1. The first voltage R1 is a voltage dividing resistor, and when the first interface module 21 is connected to the second interface module 22, the address identifying resistor 23 and the first resistor R1 form a voltage dividing circuit. The second resistor is a current limiting resistor. The anti-interference performance of the novel address allocation circuit can be ensured by arranging the first resistor R1\ the second resistor R2 and the filter capacitor group.
It should be noted that the address identification resistor 23 and the second interface P2 may also form a second interface module 22, the second interface module 22 may be installed on the device main body, the first interface module 21 is connected with the controller 1 to form a control board, when the control board is replaced, the control board may be directly plugged into the second interface module 22 to automatically identify the device address, so as to achieve the effect of convenient replacement of the control board.
The novel address allocation circuit of the invention is implemented as follows: the first interface module 21 and the second interface module 22 are connected by the first interface and the second interface in a butt joint manner, at this time, the address identification resistor 23 and the first resistor structure R1 form a voltage division circuit to output a level, and the output level is filtered by the filter capacitor bank and then transmitted to the pin of the controller 1 through the second resistor R2. The pin receives the output level and reads an a/D value corresponding to the level, and then corresponds the a/D value to the content in the address table to convert the output level to an ID/IP address to the controller 1. If the address needs to be adjusted or replaced, only the resistance value of the address identification resistor 23 needs to be replaced or adjusted, and the method is quick and convenient.
In summary, the following steps: this application is provided with controller 1 and the address identification module 2 of being connected with controller 1, and address identification module 2 includes address identification resistance 23, and the change and the adjustment of address in controller 1 both can be realized through the resistance value that changes address identification resistance 23, need not through external interface equipment or network, and can realize many address allocation, and is small and with low costs, convenient maintenance.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. The novel address distribution circuit is characterized by comprising a controller and an address identification module connected with only one pin of the controller, wherein the address identification module comprises an address identification resistor with an adjustable resistance value; the controller is characterized in that an address table is prestored in the controller, the resistance value of the address identification resistor is adjusted to enable the address identification module to output the level, the output level is sent to the controller, and the controller receives and reads the output level through a pin connected with the address identification module and corresponds the output level to the address table to convert the output level into an ID/IP address.
2. The novel address assignment circuit of claim 1, wherein the address identification module is connected to a TX/AD pin of the controller.
3. The novel address assignment circuit of claim 1, wherein the address identification module includes a first interface module connected to the controller and a second interface module interfacing with the first interface module, the second interface module including a second interface connected to the address identification resistor.
4. The novel address assignment circuit of claim 3, wherein the first interface module includes a first interface interfacing with the second interface, a first resistor, a second resistor, and a filter capacitor bank, a first end of the first resistor is connected to a first end of the first interface, a second end of the first resistor is connected to a power supply, a first end of the filter capacitor bank is connected to a first end of the first interface, a second end of the filter capacitor bank is connected to a second end of the first interface and to ground, a first end of the second resistor is connected to a first end of the filter capacitor bank, and a second end of the second resistor is connected to one of the pins of the controller.
5. The novel address assignment circuit of claim 4, wherein the filter capacitor bank comprises a low frequency filter capacitor connected to the second resistor, an intermediate frequency filter capacitor connected to the low frequency filter capacitor, and a high frequency filter capacitor for connecting the intermediate frequency filter capacitor to the first interface.
6. The novel address assignment circuit of claim 4, wherein the first voltage is a voltage dividing resistor, and when the first interface module is connected to the second interface module, the address identification resistor and the first resistor form a voltage dividing circuit.
7. The novel address assignment circuit of claim 4, wherein the second resistor is a current limiting resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911098490.2A CN110809068A (en) | 2019-11-12 | 2019-11-12 | Novel address distribution circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911098490.2A CN110809068A (en) | 2019-11-12 | 2019-11-12 | Novel address distribution circuit |
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| Publication Number | Publication Date |
|---|---|
| CN110809068A true CN110809068A (en) | 2020-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911098490.2A Pending CN110809068A (en) | 2019-11-12 | 2019-11-12 | Novel address distribution circuit |
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| CN (1) | CN110809068A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112327690A (en) * | 2020-10-30 | 2021-02-05 | 科华恒盛股份有限公司 | Multi-module physical address sampling system |
| CN118034528A (en) * | 2024-04-02 | 2024-05-14 | 广州众远智慧科技有限公司 | Infrared touch frame circuit board, infrared touch frame and infrared touch screen |
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| US20020024959A1 (en) * | 2000-08-26 | 2002-02-28 | Samsung Electronics Co., Ltd. | Network address conversion system for enabling access to a node having a private IP address, a method therefor, and a recording medium for recording the method |
| CN102685037A (en) * | 2012-06-08 | 2012-09-19 | 汕头市易普联科技有限公司 | Gateway equipment |
| CN204013486U (en) * | 2014-08-27 | 2014-12-10 | 国家电网公司 | The circuit of device address is set with toggle switch |
| CN108897277A (en) * | 2018-08-09 | 2018-11-27 | 昆明理工大学 | A kind of independent I/O module address automatic allocating method and structure of PLC |
| CN110109040A (en) * | 2019-05-30 | 2019-08-09 | 奇瑞新能源汽车技术有限公司 | A kind of address scaling method of batteries of electric automobile acquisition unit |
-
2019
- 2019-11-12 CN CN201911098490.2A patent/CN110809068A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020024959A1 (en) * | 2000-08-26 | 2002-02-28 | Samsung Electronics Co., Ltd. | Network address conversion system for enabling access to a node having a private IP address, a method therefor, and a recording medium for recording the method |
| CN102685037A (en) * | 2012-06-08 | 2012-09-19 | 汕头市易普联科技有限公司 | Gateway equipment |
| CN204013486U (en) * | 2014-08-27 | 2014-12-10 | 国家电网公司 | The circuit of device address is set with toggle switch |
| CN108897277A (en) * | 2018-08-09 | 2018-11-27 | 昆明理工大学 | A kind of independent I/O module address automatic allocating method and structure of PLC |
| CN110109040A (en) * | 2019-05-30 | 2019-08-09 | 奇瑞新能源汽车技术有限公司 | A kind of address scaling method of batteries of electric automobile acquisition unit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112327690A (en) * | 2020-10-30 | 2021-02-05 | 科华恒盛股份有限公司 | Multi-module physical address sampling system |
| CN112327690B (en) * | 2020-10-30 | 2022-08-09 | 科华恒盛股份有限公司 | Multi-module physical address sampling system |
| CN118034528A (en) * | 2024-04-02 | 2024-05-14 | 广州众远智慧科技有限公司 | Infrared touch frame circuit board, infrared touch frame and infrared touch screen |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200218 |