CN110808733A - Fuse logic operation circuit with high reliability - Google Patents
Fuse logic operation circuit with high reliability Download PDFInfo
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- CN110808733A CN110808733A CN201911154081.XA CN201911154081A CN110808733A CN 110808733 A CN110808733 A CN 110808733A CN 201911154081 A CN201911154081 A CN 201911154081A CN 110808733 A CN110808733 A CN 110808733A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The invention provides a high-reliability fuse logic operation circuit, which comprises more than one single fuse circuit and a logic operation circuit. In more than one single fuse circuit, the single fuse circuit refers to the series connection of a fuse and a pull-up device or a pull-down device, the output of each single fuse circuit is connected to the input of a logic operation circuit, the output of the logic operation circuit is the output of the circuit, and the function of the logic operation circuit is that as long as the fuse in one single fuse circuit is blown, the output of the logic operation circuit is inverted in logic level compared with the output of the logic operation circuit without the fuse. Because the fuse is blown and then has the possibility of being reconnected, when more than one fuse is blown and the fuse less than the number of the blown fuse is reconnected, the output level of the logic operation circuit is not inverted, so the output of the fuse logic operation circuit has the advantage of high reliability, the circuit is simple to realize and has the advantage of low cost.
Description
Technical Field
The invention relates to the field of fuse circuits, in particular to a high-reliability fuse logic operation circuit.
Background
As shown in fig. 6, a conventional fuse logic operation circuit is composed of a single fuse circuit, which is generally a series connection of a resistor and a fuse, and an inverter whose level is inverted when the fuse is blown. The fuse logic operation circuit is generally used for parameter trimming or function selection of a circuit, if the fuse is incompletely burnt or a fuse area is polluted, the fuse with a certain probability is reconnected, and accordingly the parameter trimming or function selection of the circuit fails, and the circuit has the defect that the failure rate of the parameter trimming or function selection of the circuit is high, namely the traditional fuse logic operation circuit is low in reliability.
Disclosure of Invention
The invention provides a fuse logic operation circuit with high reliability, which aims to solve the defect of low reliability of the traditional fuse logic operation circuit.
In order to solve the above technical problems, the present invention provides a fuse logic operation circuit with high reliability, which includes more than one single fuse circuit and logic operation circuit. In more than one single fuse circuit, the single fuse circuit refers to the series connection of a fuse and a pull-up device or a pull-down device, the pull-up device or the pull-down device is a resistance device or a device which is equivalent to a resistance, the output of each single fuse circuit is connected to the input of a logic operation circuit, the output of the logic operation circuit is the output of the circuit, and the function of the logic operation circuit is that as long as the fuse in one single fuse circuit is blown, the output of the logic operation circuit is inverted in logic level compared with the output of the logic operation circuit without the fuse. In addition, in actual operation, when the fuse is required to be blown, at least two or all of the fuses in all the single fuse circuits connected with the input of the logic operation circuit are blown, because the fuse has the possibility of being reconnected after being blown, when more than one fuse is blown, the fuse less than the number of the blown fuse is reconnected, the output level of the logic operation circuit cannot be inverted, and the probability of the reconnection of the more than one fuse after being blown is much lower than the probability of the reconnection of the single fuse after being blown, so the fuse logic operation circuit has the advantages of strong output stability and high reliability, and the circuit is simple to implement and has the advantage of low cost.
The present invention takes the example that the outputs of two single fuse circuits are connected to the input of the logic operation circuit, because the function of the logic operation circuit is that, as long as there is a fuse in one single fuse circuit blown, the output of the logic operation circuit is inverted in logic level compared to no fuse, that is, when both fuses are blown, the output of the logic operation circuit is inverted in logic level compared to no fuse, after that, if there is a fuse reconnected, the output of the logic operation circuit is not inverted, only when both fuses are reconnected, the output of the logic operation circuit is inverted to the level when no fuse is blown, assuming that the probability of the fuse being reconnected after being blown is one thousandth, the probability of both fuses being reconnected is:
(0.001×0.001)×2＝0.000002
i.e., one in fifty-ten-thousandths, it follows that the present invention greatly improves the reliability of the circuit.
The multiplication by 2 in the above formula is because the number of fuses is doubled in this scheme compared to the background art scheme.
Preferably, the number of the single fuse circuits is at least two.
Preferably, in practical applications, at least two fuses of the plurality of individual fuse circuits are blown or none of the fuses are blown.
The invention has the following beneficial effects: the fuse logic operation circuit with high reliability improves the reliability of the circuit, is simple to realize, and has the advantage of low cost compared with other schemes for improving the reliability.
Drawings
FIG. 1 is a schematic diagram of a high-reliability fuse logic operation circuit according to the present invention.
Fig. 2 is a high-reliability fuse logic operation circuit according to a first embodiment of the present invention.
Fig. 3 is a high reliability fuse logic operation circuit according to a second embodiment of the present invention.
Fig. 4 is a high-reliability fuse logic operation circuit according to a third embodiment of the present invention.
Fig. 5 is a high-reliability fuse logic operation circuit according to a fourth embodiment of the present invention.
Fig. 6 is a schematic diagram of the background art.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, the present invention provides a high-reliability fuse logic operation circuit, which includes more than one single fuse circuit and logic operation circuit. In more than one single fuse circuit, the single fuse circuit refers to the series connection of fuses and pull-up devices or pull-down devices, the output of each single fuse circuit is connected to the input of the logic operation circuit, the output of the logic operation circuit is the output of the circuit, and the function of the logic operation circuit is that, as long as the fuses in one single fuse circuit are blown, the output of the logic operation circuit is inverted in logic level compared with the output of the logic operation circuit without the fuses, because the fuses are re-connected after being blown, when more than one fuses are blown, the fuses less than the number of blown fuses are re-connected, and the output level of the logic operation circuit is not inverted, so that the output of the fuse logic operation circuit has the advantages of high reliability, the circuit is simple to implement and has the advantage of low cost.
The first embodiment of the present invention, as shown in fig. 2, includes two single fuse circuits formed by serially connecting a fuse and a pull-down device NMOS transistor, and a logic operation circuit formed by a two-input nand gate. One end of a fuse F1 is connected with a power supply, the other end of the fuse F1 is connected with a signal line a, the source end of a pull-down device NMOS tube N1 is connected with a ground wire, the drain end of the fuse F2 is connected with the signal line a, the grid of the fuse F2 is connected with the power supply, the other end of the fuse F2 is connected with a signal line b, the source end of a pull-down device NMOS tube N2 is connected with the ground wire, the drain end of the fuse F is connected with the signal line b, the grid of the fuse F2 is connected with the power supply, the signal line a and.
The first embodiment of the present invention: when the fuse F1 and the fuse F2 are not blown, the signal line a is at a high level, the signal line b is at a high level, and the output end y of the NAND gate is at a low level; after the fuse F1 and the fuse F2 are blown, the signal line a is low, the signal line b is low, the output terminal y of the NAND gate is high, when the fuse F1 is reconnected due to incomplete burning or contamination, the fuse F2 maintains the blown state, the signal line a is high, the signal line b is low, the output terminal y of the NAND gate is still high, and the level inversion does not occur due to the reconnection of the fuse F1, and similarly, when the fuse F2 is reconnected due to incomplete burning or contamination, the fuse F1 maintains the blown state, the signal line a is low, the signal line b is high, the output terminal y of the NAND gate is still high, the level inversion does not occur due to the reconnection of the fuse F2, the fuse F1 and the fuse F2 are reconnected due to incomplete burning or contamination, the signal line a is high, the signal line b goes high and the nand gate output y flips to low, resulting in circuit failure.
From a logical analysis of the first embodiment of the present invention, it can be seen that: if the nand gate output y needs to be high level according to application parameters such as trimming or function selection, and the fuse F1 and the fuse F2 are both blown, after the fuse F1 and the fuse F2 are both blown, the circuit will fail only if the fuse F1 and the fuse F2 are both reconnected because of incomplete burning or contamination, and assuming that the probability of reconnection after blowing is one thousandth, the probability of reconnection of both fuses is:
(0.001×0.001)×2＝0.000002
namely, one fiftieth of a ten thousand, the factor of multiplying 2 in the above formula is that the number of fuses in the scheme is doubled compared with the scheme in the conventional technology, a circuit fails when one fuse is reconnected due to incomplete burning or contamination, and if the probability that the fuse is reconnected after being burned out is one thousandth, the failure rate of the circuit in the conventional technology is one thousandth, while the failure rate of the circuit in the embodiment is one fiftieth of a ten thousand, so that the reliability of the circuit is greatly improved.
The second embodiment of the present invention, as shown in fig. 3, includes two single fuse circuits formed by connecting a fuse and a pull-up PMOS transistor in series, and a logic operation circuit formed by a two-input nor gate. One end of a fuse F1 is connected with a ground wire, the other end of the fuse F1 is connected with a signal wire a, the source end of a pull-up PMOS tube P1 is connected with a power supply, the drain end of the fuse F2 is connected with the ground wire with low level, one end of the fuse F2 is connected with the ground wire, the other end of the fuse F2 is connected with a signal wire b, the source end of a pull-up PMOS tube P2 is connected with the power supply, the drain end of the fuse F1 is connected with the signal wire b, the gate of the fuse F is connected with the ground wire with low level, the signal wire a is connected with one input end of a NOR gate with two input ends, the.
Second embodiment of the invention: when the fuse F1 and the fuse F2 are not blown, the signal line a is at a low level, the signal line b is at a low level, and the two-input end NOR gate output end y is at a high level; after the fuse F1 and the fuse F2 are blown, the signal line a is at a high level, the signal line b is at a high level, the nor output terminal y is at a low level, when the fuse F1 is reconnected due to incomplete burning or contamination, the fuse F2 maintains the blown state, the signal line a is at a low level, the signal line b is at a high level, the nor output terminal y remains at a low level, and the level inversion does not occur due to the reconnection of the fuse F1, and similarly, when the fuse F2 is reconnected due to incomplete burning or contamination, the fuse F1 maintains the blown state, the signal line a is at a high level, the signal line b is at a low level, the nor output terminal y remains at a low level, and the level inversion does not occur due to the reconnection of the fuse F2, the fuse F1 and the fuse F2 are reconnected due to incomplete burning or contamination, the signal line a is at a low level, the signal line b is low and the nor gate output y flips to high, resulting in circuit failure.
From a logical analysis of the second embodiment of the present invention, it can be seen that: if the two-input nor output y is required to be at low level according to parameter trimming or function selection in an application, and the fuse F1 and the fuse F2 are both blown, after the fuse F1 and the fuse F2 are both blown, the circuit will fail only when the fuse F1 and the fuse F2 are both reconnected due to incomplete burning or contamination, and assuming that the probability of reconnection after blowing is one thousandth, the probability of reconnection of both fuses is:
(0.001×0.001)×2＝0.000002
that is, one fiftieth of a ten thousand, the factor of multiplying 2 in the above formula is because the number of fuses in the scheme is doubled compared with the scheme in the conventional technology, and when one fuse in the conventional technology is reconnected because of incomplete burning or contamination, the circuit will fail, and assuming that the probability that the fuse is reconnected after being burned out is one thousandth, the failure rate of the circuit in the conventional technology is one thousandth, while the failure rate of the circuit in this embodiment is about one fiftieth of a ten thousand, so the reliability of the circuit is also improved greatly.
The third embodiment of the present invention, as shown in fig. 4, includes three single fuse circuits formed by connecting fuses in series with pull-down device resistors, and a logic operation circuit formed by a three-input nand gate. One end of a fuse F1 is connected with a power supply, the other end of the fuse F1 is connected with a signal line a, one end of a pull-down device resistor R1 is connected with a ground line, the other end of the fuse F2 is connected with the power supply, the other end of the fuse F2 is connected with a signal line b, one end of a pull-down device resistor R2 is connected with the ground line, the other end of the pull-down device resistor R3 is connected with the power supply, the other end of the pull-down device resistor R3 is connected with the ground line, the other end of the pull-down device resistor R2 is connected with the signal line c, the signal line a, the signal line b and the signal line c.
Third embodiment of the invention: when the fuse F1, the fuse F2 and the fuse F3 are not blown, the signal line a is at a high level, the signal line b is at a high level, the signal line c is at a high level, and the output y of the NAND gate with three input ends is at a low level; after the fuse F1, the fuse F2 and the fuse F3 are all blown, the signal line a is at low level, the signal line b is at low level, the signal line c is at low level, the output terminal y of the NAND gate is at high level, when two fuses or one of the fuse F1, the fuse F2 and the fuse F3 is reconnected due to incomplete burning or contamination, and at least one fuse maintains the blown state, the output terminal y of the three-input NAND gate is still at high level, and when the fuse F1, the fuse F2 and the fuse F3 are reconnected due to incomplete burning or contamination, the output terminal y of the three-input NAND gate is inverted to low level, thereby causing the circuit failure.
From a logical analysis of the third embodiment of the present invention, it can be seen that: if the output y of the three-input nand gate needs to be high level according to the application parameters such as trimming or function selection, and the three fuses of the fuse F1, the fuse F2 and the fuse F3 are all blown, after the fuse F1, the fuse F2 and the fuse F3 are all blown, the circuit will fail only when the fuse F1, the fuse F2 and the fuse F3 are all reconnected due to incomplete burning or contamination, and assuming that the probability that the fuse is reconnected after being blown is one thousandth, the probability that the three fuses are reconnected is:
(0.001×0.001×0.001)×3＝0.000000003
that is, three parts per billion, the factor of 3 in the above formula is because the number of fuses is increased by two compared with the conventional method, in the conventional method, when one fuse is reconnected due to incomplete burning or contamination, the circuit fails, and assuming that the probability of reconnection after the fuse is burned out is one thousandth, the failure rate of the circuit in the conventional method is one thousandth, while the failure rate of the circuit in this embodiment is about three parts per billion, so the reliability of the circuit is also improved.
The fourth embodiment of the present invention, as shown in fig. 5, includes three single fuse circuits formed by connecting a fuse and a pull-up PMOS transistor in series, and a logic operation circuit formed by a three-input nor gate. One end of a fuse F1 is connected with a ground wire, the other end of the fuse F1 is connected with a signal wire a, the source end of a pull-up PMOS tube P1 is connected with a power supply, the drain end of the fuse F2 is connected with the signal wire a, the grid of the fuse F2 is connected with a low-level ground wire, one end of the fuse F2 is connected with the ground wire, the other end of the fuse F2 is connected with the signal wire b, the source end of a pull-up PMOS tube P2 is connected with the power supply, the drain end of the fuse F3 is connected with the signal wire b, the grid of the fuse F3 is connected with the low-level ground wire, one end of the fuse F3 is connected with the ground wire, the other end of the fuse F3 is connected with the power supply, the drain end of the fuse F36is connected.
Fourth embodiment of the invention: when the fuse F1, the fuse F2 and the fuse F3 are not blown, the signal line a is at a low level, the signal line b is at a low level, the signal line c is at a low level, and the output terminal y of the three-input NOR gate is at a high level; after the fuse F1, the fuse F2 and the fuse F3 are all blown, the signal line a is at high level, the signal line b is at high level, the signal line c is at high level, the three-input nor gate output y is at low level, when two fuses or one of the fuse F1, the fuse F2 and the fuse F3 is reconnected due to incomplete burning or contamination, and at least one fuse maintains the blown state, the three-input nor gate output y is still at low level, and when the fuse F1, the fuse F2 and the fuse F3 are reconnected due to incomplete burning or contamination, the three-input nor gate output y is inverted to high level, thereby causing the circuit failure.
From a logical analysis of the fourth embodiment of the present invention, it can be seen that: if the three-input nor gate output y is required to be at a low level according to parameter trimming or function selection in an application, and three fuses of the fuse F1, the fuse F2 and the fuse F3 are all blown, after the fuse F1, the fuse F2 and the fuse F3 are all blown, a circuit fails only when three fuses of the fuse F1, the fuse F2 and the fuse F3 are reconnected due to incomplete burning or contamination, and assuming that the probability that the fuses are reconnected after being blown is one thousandth, the probability that the three fuses are reconnected is:
(0.001×0.001×0.001)×3＝0.000000003
that is, three parts per billion, the factor of 3 in the above formula is because the number of fuses is increased by two compared with the conventional method, in the conventional method, when one fuse is reconnected due to incomplete burning or contamination, the circuit fails, and assuming that the probability of reconnection after the fuse is burned out is one thousandth, the failure rate of the circuit in the conventional method is one thousandth, while the failure rate of the circuit in this embodiment is about three parts per billion, so the reliability of the circuit is also improved.
In summary, the fuse logic operation circuit with high reliability provided by the invention improves the reliability of the output of the fuse logic operation circuit by the characteristic that the probability that two or more fuses are reconnected because of incomplete burning or contamination is far less than the probability that one fuse is reconnected because of incomplete burning or contamination, and the like.
The above description is only an example of the present invention, and is not intended to limit the present invention, and it is obvious to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (9)
1. A high-reliability fuse logic operation circuit is characterized by comprising more than one single fuse circuit and logic operation circuit. Wherein the output of each individual fuse circuit is connected to the input of the logic operation circuit.
2. The high reliability fuse logic operation circuit of claim 1 wherein the single fuse circuit refers to a series connection of a fuse and either a pull-up device or a pull-down device.
3. The pull-up device or pull-down device of claim 2, wherein the pull-up device or pull-down device is a resistive device or a device that is equivalent to a resistor, such as a MOS transistor with a relatively large on-resistance, or an active device with a relatively large on-resistance, or a combination of an active device with a relatively large on-resistance and a resistor.
4. The high reliability fuse logic operation circuit according to claim 1, wherein the output of the single fuse circuit is a connection point of a pull-up device or a pull-down device and a fuse.
5. The high reliability fuse logic operation circuit according to claim 1, wherein the more than one single fuse circuits, i.e., the single fuse circuits are at least two.
6. The highly reliable fuse logic operation circuit according to claim 1, wherein the logic operation circuit functions such that whenever a fuse in a single fuse circuit is blown, the output of the logic operation circuit is inverted in logic level as compared with when no fuse is blown.
7. The high reliability fuse logic operation circuit according to claim 1, wherein the logic operation circuit may be a nand gate or a nor gate.
8. The high reliability fuse logic operation circuit according to claim 1, wherein the logic operation circuit may be a combination of logic gates functionally similar to a nand gate or a nor gate.
9. The high reliability fuse logic operation circuit according to claim 1, wherein the logic operation circuit may be a nand gate, or an analog circuit with a similar nor gate function and a combination thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911154081.XA CN110808733A (en) | 2019-11-22 | 2019-11-22 | Fuse logic operation circuit with high reliability |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911154081.XA CN110808733A (en) | 2019-11-22 | 2019-11-22 | Fuse logic operation circuit with high reliability |
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| CN110808733A true CN110808733A (en) | 2020-02-18 |
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| CN201911154081.XA Pending CN110808733A (en) | 2019-11-22 | 2019-11-22 | Fuse logic operation circuit with high reliability |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114078551A (en) * | 2020-08-21 | 2022-02-22 | 美光科技公司 | Random option inversion for memory devices |
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2019
- 2019-11-22 CN CN201911154081.XA patent/CN110808733A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114078551A (en) * | 2020-08-21 | 2022-02-22 | 美光科技公司 | Random option inversion for memory devices |
| CN114078551B (en) * | 2020-08-21 | 2023-01-03 | 美光科技公司 | Random option inversion for memory devices |
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Application publication date: 20200218 |
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| WD01 | Invention patent application deemed withdrawn after publication |