JPH10256486A - Semiconductor input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prepare a test mode without preparing a special terminal for test, and make it in such environment that the test can be performed without fail, by making an input level judging circuit output the result of the judgment on the voltage of the second node which has judgment level between power voltage and ground. SOLUTION: An input terminal 1 is connected to an electrostatic protective circuit 101, and one of the node 105 of its output is inputted to an input circuit 102, and the other end to a switching circuit 103. Moreover, the other of the switching circuit 103 is inputted into a resistance element 104 and an input level judging circuit 105. Then, if the input signal from the input terminal 1 is at or above a value where a certain voltage is added to power voltage, the nodes 105 and 107 are connected with each other, and the node 107 goes up to the voltage applied to the input terminal 1. The input level judging circuit 108 receives this rising voltage, and has judgment level between the power voltage and the ground, and judges the voltage of the node 107, and outputs the condition to a test mode output terminal 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for setting a test mode by applying a voltage higher than a power supply voltage or a voltage lower than a ground only at the time of a test in a case where available terminals of a semiconductor chip are limited. It concerns a possible circuit.

[0002]

2. Description of the Related Art In recent years, semiconductor circuits have been miniaturized, and the design technique has shifted from gate-level design to language-based design, enabling a drastically large-scale circuit design. . As a result, the importance of circuit test methods has also increased.

A conventional test method is disclosed in Japanese Unexamined Patent Publication No.
As described in Japanese Patent Application Laid-Open No. 055897, a test mode is created by applying a different voltage between two normal terminals, or by changing the power-on timing, which is performed in Japanese Patent Application Laid-Open No. 06-066899. By omitting, the test mode terminal is omitted.

[0004]

However, Japanese Patent Application Laid-Open No.
In the case of the method described in Japanese Patent No. 055897, it is necessary to prepare two specific terminals and to newly prepare a diode inside the circuit in order to create a state to be tested. ing.

In the method disclosed in Japanese Patent Application Laid-Open No. 06-066899, a special sequence is required when a normal LSI tester is used to create a test state when the power supply voltage is changed. However, there is a lack of mass productivity. Further, it is necessary to provide a comparator inside the circuit. For this reason, an increase in chip size and a decrease in yield have been considered, and these have led to an increase in chip cost.

[0006] The present invention is to solve such problems, and an object of the present invention is to solve these problems by using a normal process without preparing special terminals for testing. The purpose of the present invention is to provide a test mode and an environment in which a test can be reliably performed.

[0007]

[Means for Solving the Problems]

(1) The above object is to provide an input having an input terminal, inputting a voltage applied from the input terminal to the input terminal through an electrostatic protection circuit, determining the voltage level, and outputting a result of the determination to a semiconductor internal circuit. A circuit, wherein a first terminal is connected from the input terminal to a first node passing through the electrostatic protection circuit, a switching circuit having a second terminal connected to a second node, and the switching circuit ,
The voltage of the first node, a certain voltage higher than the power supply voltage of the input circuit, to determine the above or below, if less than a certain voltage, the first terminal and the second terminal become conductive. Conversely, if the voltage is lower than a certain voltage, the first terminal and the second terminal become non-conductive, and input the second node, a resistance element having both ends connected to ground, and the second node. An input level determination circuit that outputs to a test mode output terminal, and the input level determination circuit has a determination level between a power supply voltage and a ground, and achieves by outputting a result of determining a voltage of the second node. Is done.

The switching circuit comprises a source,
And a first P-channel MOS transistor having a substrate connected to the first node, a gate connected to a power supply, and a drain connected to a second node.

The switching circuit comprises a source,
A second P-channel MOS transistor having one end connected to the substrate and the other end connected to the gate and the other end connected to the source and the substrate. A third P-channel MOS transistor having a drain at the other end, the second P-channel MOS transistor, and the third P-channel MOS transistor each configured by connecting one or more in series. It is achieved by doing.

(2) As another means for realizing the above object, an input terminal is provided, a voltage applied from the input terminal to the input terminal through an electrostatic protection circuit is input, and the voltage level is determined. An input circuit that outputs a result determined to the circuit, wherein a first terminal is connected from the input terminal to a first node passing through the electrostatic protection circuit, and a second terminal is connected to a second node. The switching circuit, the switching circuit, the voltage of the first node, a certain voltage lower than the power supply voltage of the input circuit, determines or less than, less than the certain voltage, the first voltage The terminal and the second terminal become conductive,
Conversely, if the voltage is equal to or higher than a certain voltage, the first terminal and the second terminal become non-conductive, and the second node and a resistance element having both ends connected to ground and the second node as inputs. An input level determination circuit that outputs a test mode output terminal, and the input level determination circuit has a determination level between a power supply voltage and a ground, and is achieved by outputting a result of determining a voltage of the second node. You.

Further, the switching circuit includes a source,
And a substrate connected to the first node, a gate connected to ground and a drain connected to a second node.
This is achieved by being configured with a channel type MOS transistor.

Further, the switching circuit comprises a source,
And a second N-channel MOS transistor having one end connected to the substrate and the other end connected to the gate and the drain connected to the source and the substrate at one end. A third N-channel MOS transistor having the other end as
This is achieved by having one or more of the second N-channel MOS transistor and the third N-channel MOS transistor connected in series.

(3) As another means for realizing the above object, an input terminal is provided, a voltage applied from the input terminal to the input terminal through an electrostatic protection circuit is input, and the voltage level is determined. An input circuit that outputs a result determined to the circuit, wherein a first terminal is connected from the input terminal to a first node passing through the electrostatic protection circuit, and a second terminal is connected to a second node. The first switching circuit, the first switching circuit, the voltage of the first node, a certain voltage higher than the power supply voltage of the input circuit, determines or less than, less than a certain voltage If so, the first terminal and the second terminal become conductive, and conversely, if less than a certain voltage, the first terminal and the second terminal become non-conductive, the second node and the third Terminal, gra And a second switching circuit having a seventh control terminal, the second node being connected to a fifth terminal, the ground being connected to a sixth terminal, and the first node being connected to a sixth terminal. And a third switching circuit to which an eighth control terminal is connected, and the second node as an input, output to a test mode output terminal, and to the seventh control terminal of the second switching circuit. An input level determining circuit for outputting, and the input level determining circuit has a determination level between a power supply voltage and a ground, and outputs a result of determining a voltage of the second node to the test mode output terminal and the second switching circuit. The second switching circuit receives an output from the input determination circuit at the seventh control terminal, and the second node is at a low level if the second node is at a low level. The third terminal and the fourth terminal are conductive, and conversely, if the terminal is at a high level, the third terminal and the fourth terminal are non-conductive, and the third switching circuit has a power supply voltage and a ground connected to a control terminal. If the first node has a low level, the fifth terminal and the sixth terminal become conductive, and
Conversely, if the signal is at a high level, the fifth terminal and the sixth terminal are made non-conductive.

The first switching circuit has a source and a substrate connected to the first node, a gate connected to a power supply, and a drain connected to a first node connected to a second node.
This is achieved by being configured with a channel type MOS transistor.

The first switching circuit includes a second P-channel MOS transistor having one end connected to the source and the substrate and the other end connected to the gate and the drain; And a third P-channel MOS transistor having a gate connected to a power supply voltage and a drain connected to the other end, the second P-channel MOS transistor, and the third P-channel MOS transistor. This is achieved by having one or a plurality of MOS transistors connected in series.

The second switching circuit has a source and a substrate connected to the ground, a gate connected to a seventh control terminal, and a drain connected to a third terminal. Is achieved.

Further, the third switching circuit has an inverter having an eighth control terminal connected to an input, an output of the inverter connected to a gate, a source and a substrate connected to the ground, and a drain connected to the ground. This is achieved by being constituted by the fifth N-channel MOS transistor connected to the fifth terminal.

(4) As another means for realizing the above object, an input terminal is provided, a voltage applied from the input terminal to the input terminal through an electrostatic protection circuit is input, and the voltage level is determined. An input circuit that outputs a result determined to the circuit, wherein a first terminal is connected from the input terminal to a first node passing through the electrostatic protection circuit, and a second terminal is connected to a second node. The first switching circuit and the first switching circuit determine whether the voltage of the first node is a certain voltage lower than the ground of the input circuit, is equal to or greater than or less than a certain voltage. If the first terminal and the second terminal are conductive, if the voltage is equal to or higher than a certain voltage, the first terminal and the second terminal are non-conductive, the second node and the third terminal , And a second switching circuit having a seventh control terminal, connected to the fourth terminal, the second node and a fifth terminal, connected to a power supply and a sixth terminal, the first node and A third switching circuit to which an eighth control terminal is connected, and the second node as an input, an output to a test mode output terminal, and an output to the seventh control terminal of the second switching circuit. The input level determination circuit, and the input level determination circuit has a determination level between a power supply voltage and ground, and determines a result of determining the voltage of the second node by using the test mode output terminal and the second switching circuit. Output to the seventh control terminal, the second switching circuit receives the output from the input level determination circuit at the seventh control terminal, and the third node if the second node is at a high level. The third terminal and the fourth terminal are non-conductive if the terminal and the fourth terminal are conductive, and conversely if the terminal is low level, the third switching circuit determines whether the control terminal is between the power supply voltage and the ground. The first terminal has a high level, the fifth terminal and the sixth terminal are conductive, and if the first node is low, the fifth terminal and the sixth terminal are nonconductive. Is achieved by

The first switching circuit comprises a first P-channel MOS transistor having a source and a substrate connected to the first node, a gate connected to ground, and a drain connected to a second node. This is achieved by being configured.

The first switching circuit includes a second N-channel MOS transistor having one end connected to the source and the substrate and the other end connected to the gate and the drain; A third N-channel MOS transistor having one end connected to the substrate and the substrate, a gate serving as a ground, and a drain serving as the other end; the second N-channel MOS transistor;
And at least one of the third N-channel MOS transistors is connected in series.

The second switching circuit has a source and a substrate connected to the ground, a gate connected to a seventh control terminal, and a drain connected to a third terminal. Is achieved.

Further, the third switching circuit has an inverter having an eighth control terminal connected to the input, an output of the inverter connected to the gate, a source and a substrate connected to the ground, and a drain connected to the ground. This is achieved by the fifth P-channel MOS transistor connected to the third terminal.

Further, in (1) or (3), the static electricity protection circuit is achieved by being an electrostatic protection circuit in which no current flows even when a high voltage is applied between a power supply and the input terminal.

Further, in (2) or (4), the static electricity protection circuit is achieved by being a static electricity protection circuit in which no current flows even when a low voltage is applied between a ground and the input terminal.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor input device according to the present invention. The input terminal 1 is connected to the static electricity protection circuit 101, and one of the output nodes 105 is connected to the input circuit 10
2 and the other end is input to the switching circuit 103. The other side of the switching circuit 103 is input to the resistance element 104 and the input level determination circuit 105.
The other end of the resistance element 104 is connected to ground 0,
The input level judging circuit 108 outputs to the test mode output terminal 3.

The signal input from the input terminal 1 is protected from electrostatic breakdown by the electrostatic protection circuit 101, the input circuit 102 determines whether the signal is high or low, and the result is output to the output terminal 2.

On the other hand, the signal output from the electrostatic protection circuit 101 is input to the switching circuit 103. If the switching circuit 103 is equal to or lower than a voltage obtained by adding a certain voltage to the power supply voltage of the input circuit 102, the switching circuit 103 does not conduct between the nodes 105 and 107. That is, node 105 and node 10
7, the voltage of the node 107 drops to the ground level at the resistance element 104. The input voltage determination circuit 108 receives the reduced voltage.
The input level determination circuit 108 has a determination level between the power supply voltage and the ground, and determines the voltage of the node 107. In this case, since the node 107 is at the ground level, the result is determined to be low. The state is output to the test mode output terminal 3.

Here, the signal input from the input terminal 1 is
If the voltage is equal to or higher than a voltage obtained by adding a certain voltage to the power supply voltage, the switching circuit 103 having received the voltage has a function of conducting between the nodes 105 and 107. Therefore, the node 105 and the node 107 are connected, a current flows through the resistance element 104, and the node 107 is connected to the input terminal 1
Rise to the voltage applied to. The input voltage determination circuit 108 receives the increased voltage. The input level determination circuit 104 has a determination level between the power supply voltage and the ground,
The voltage of the node 107 is determined. In this case node 1
Since 07 has a voltage higher than the power supply voltage, the result is determined to be high, and the state is output to the test mode output terminal 3.

FIG. 2 is an expanded view of the block diagram of FIG. The static electricity protection circuit is connected between the ground 0 and the node 206, and the static electricity protection diode 201 is provided between them. The protection diode 201 is only between the ground and the power supply 9 and the node 20.
There is no between 6. This is because the input terminal 1 may have a voltage higher than the power supply voltage. In this case, a current path is formed to prevent a current from flowing. In FIG. 2, an inverter 202 is used as an input circuit. Further, a P-channel MOS transistor 203 is used as a switching circuit. This P-channel MOS transistor 203 has its gate connected to power supply 9 and its source and substrate connected to node 20.
6, the drain is connected to the node 207. The node 207 is connected to the resistor 204 and the inverter 205 as an input level determination circuit. The output of the inverter 205 is connected to the test mode output terminal 3.

Assuming that the threshold voltage of the P-channel MOS transistor 203 is Vtp, and the power supply voltage of the input circuit and the input level determination circuit is Vdd, when a voltage equal to or higher than Vdd + Vtp is applied to the input terminal 1, Since the gate is at the power supply voltage Vdd,
P-channel MOS transistor 203 conducts. Therefore, the voltage of the node 207 becomes close to the voltage applied to the input terminal 1, and the output of the inverter 205 having the node 207 as an input becomes low.

FIG. 17 shows the state of the node 207 at that time. The horizontal axis indicates the voltage applied to the input terminal 1, and the vertical axis indicates the voltage of the node 207. A dashed line 1710 is a line indicating the relationship of the voltage applied to the input terminal 1 = the voltage of the node 207. While the voltage applied to the input terminal 1 is low, the P-channel MOS transistor 203 is in a non-conductive state and thus keeps 0 V. When the voltage is sufficiently smaller than the resistance, the voltage of the node 207 becomes almost the voltage applied to the input terminal 1. FIG. 18 illustrates the above-described node 207.
The output voltage of the inverter 205 receiving the voltage of FIG. The horizontal axis represents the voltage applied to the input terminal 1 and the vertical axis represents the inverter 2
05 output voltage. Just when the voltage applied to the input terminal 1 exceeds Vdd + Vtp, the inverter 2
It can be seen that the output voltage at 05 is inverted. Therefore, from the ground level 0 V to the power supply voltage Vd
Until d, the output of the inverter 205 keeps the power supply voltage level, and it can be seen that the output never reaches the power supply voltage.

In normal use of the present semiconductor, the voltage applied to the input terminal 1 is from the ground level to the power supply voltage. In this range, the output of the inverter 205 is the power supply voltage. However, when the test mode is desired, the test mode output terminal 3 is grounded by applying a voltage equal to or higher than the power supply voltage which is not normally used to the input terminal 1, so that the test mode can be set. I understand.

FIG. 3 shows the switching circuit 103 of FIG. 1 realized by two P-channel MOS transistors. The P-channel MOS transistor 303 has its source and substrate connected to a node 307 and its gate connected to a node 308. P-channel MOS transistor 304
Is connected to the node 308 at the source and the substrate, and to the power supply 9 at the gate.

FIG. 4 shows the switching circuit 10 of FIG.
3 is realized by a plurality of P-channel MOS transistors. P-channel MOS transistor 403
Is the source and substrate at node 408, and the gate is node 4
09. A plurality of equivalent connections are connected in series to reach a P-channel MOS transistor. The P-channel MOS transistor 405 has its source and substrate connected to a node 410, and its gate connected to the power supply 9. FIGS. 19 and 20 illustrate the respective voltages in FIGS. 3 and 4. FIG. FIG. 19 shows FIG.
8, the horizontal axis indicates the voltage applied to the input terminal 1, and the vertical axis indicates the voltage of the node 411. A dashed line 1910 indicates the relationship of the voltage applied to the input terminal 1 = the voltage of the node 411.

The voltage at node 409 is a P-channel MOS
The transistor 403 lowers the voltage by the threshold voltage of the P-channel MOS transistor 403. This is shown by the solid line 1901. Similarly, the voltage decreases by the amount of the P-channel MOS transistor connected in series, and the voltage at node 410 is shown by a solid line 1902. P-channel MO having the voltage of this node 410 as the source voltage
The S transistor 405 is turned on when a voltage difference between the voltage of the power supply 9 and the threshold voltage or more occurs. The state is shown by a solid line 1903. At this time, it is assumed that the conduction resistance of P-channel MOS transistors 403 to 405 is sufficiently smaller than resistance 407.

FIG. 20 shows the output of the inverter 406 receiving the voltage of the node 411. As in FIG. 18, the horizontal axis represents the voltage applied to the input terminal 1, and the vertical axis represents the inverter 40.
6 is the output voltage. When the voltage applied to the input terminal 1 exceeds Vdd + Vtp, the inverter 40
It can be seen that the output voltage of No. 6 is inverted. Assuming that n P-channel MOS transistors are connected from the P-channel MOS transistor 403 to the P-channel MOS transistor 405, it can be understood that the output voltage of the inverter 406 starts to be inverted at Vdd + nVtp. It can be seen that the voltage is higher by (n−1) · Vtp than the voltage in FIG. Therefore, it can be seen that application of a voltage higher than the power supply voltage can be increased in steps of Vtp. This means that the P-channel MOS transistors are connected in multiple stages in series even when the signal input to the input terminal 1 swings more than the sum of the power supply voltage and the threshold voltage and the test mode may be entered. By doing so, it can be seen that the test mode can be set at a higher voltage and that there is sufficient room for use in a normal state. Note that the order of the transistors connected in series does not matter here.

FIG. 5 shows an N-channel MOS as a resistance element.
It uses a transistor. N-channel MOS
The source and substrate of transistor 505 are connected to ground 0
And a gate and a drain connected to a node 507. N-channel MOS transistor 505 is set to N
By using the channel MOS transistor, the resistance can be realized by a normal N-channel MOS transistor without adding a special process as the resistor.

FIG. 6 is a block diagram of another semiconductor input device according to the present invention. Input terminal 1 is an electrostatic protection circuit 60
1 and its output, one of the nodes 606, enters the input circuit 602, and the other
3 is input. The other side of the switching circuit 603 is input to the resistance element 605 and the input determination circuit 604. The other end of the resistance element 605 is connected to the power supply 9, and the input level determination circuit 604 outputs to the test mode output terminal 3. The signal input from the input terminal 1 is protected from electrostatic damage by the electrostatic protection circuit 601, the input circuit 602 determines a high level or a low level, and the result is output to the output terminal 2.

On the other hand, the signal output from the electrostatic protection circuit 601 is input to the switching circuit 603. If the switching circuit 603 is equal to or higher than a voltage obtained by subtracting a certain voltage from the ground of the input circuit 602, the switching circuit 603 does not conduct between the nodes 606 and 607. That is, nodes 606 and 6
07, the voltage of the node 607 rises to the power supply voltage level at the resistance element 605. The increased voltage is received by the input level determination circuit 604.
The input level determination circuit 604 has a determination level between the power supply voltage and the ground, and determines the voltage of the node 607. In this case, since node 607 is at the power supply voltage level,
The result is determined to be high. The state is output to the test mode output terminal 3.

Here, the signal input from the input terminal 1 is
If the voltage is lower than a voltage obtained by subtracting a certain voltage from the ground, the switching circuit 603 receiving the voltage has a function of conducting between the nodes 606 and 607. Therefore, the node 605 and the node 607 are connected, a current flows through the resistor 605, and the node 607 is connected to the input terminal 1
Rise to the voltage applied to. The increased voltage is received by the input level determination circuit 604. The input level determination circuit 604 has a determination level between the power supply voltage and the ground,
The voltage of the node 607 is determined. In this case node 6
Since 07 has a voltage lower than the ground voltage, the result is determined to be low, and the state is output to the test mode output terminal 3.

FIG. 7 is an expanded version of the block diagram of FIG. 6 as a specific circuit. The electrostatic protection circuit is connected between the power supply 9 and the node 706, and an electrostatic protection diode 701 is installed between the power supply 9 and the node 706. This protection diode 701
Is only between grounds, ground 0 and node 70
There is no between 6. This is to prevent the current from flowing through the current path in such a case that the input terminal 1 may be lower than the ground voltage. FIG. 7 as input circuit
Uses an inverter 702. An N-channel MOS transistor 703 is used as a switching circuit. This N-channel MOS transistor 703
Has its gate connected to ground 0, its source and substrate connected to node 706, and its drain connected to node 707. The node 707 is connected to the resistor 705 and the inverter 704 as an input level determination circuit. The output of the inverter 704 is connected to the test mode output terminal 3.

Assuming that the threshold voltage of the N-channel MOS transistor 703 is Vtn, when a voltage of -Vtn or less is applied to the input terminal 1, the gate of the N-channel MOS transistor 703 is grounded. The transistor 703 is turned on. Therefore, node 707 is close to the voltage applied to input terminal 1 and, therefore, inverter 7 having node 707 as an input.
The output of 04 goes high.

FIG. 21 shows the state of the node 707 at that time. The horizontal axis shows the voltage applied to the input terminal 1, and the vertical axis shows the voltage of the node 707. A dashed line 2110 indicates the relationship of the voltage applied to the input terminal 1 = the voltage of the node 707. While the voltage applied to the input terminal 1 is high, the N-channel MOS transistor 703 is in a non-conductive state, so that the voltage Vdd is maintained. When the voltage is sufficiently smaller than the resistance, the voltage of the node 707 becomes almost the voltage applied to the input terminal 1.

FIG. 22 shows the output voltage of inverter 704 receiving the voltage of node 707 described above. The horizontal axis represents the voltage applied to the input terminal 1 and the vertical axis represents the output voltage of the inverter 704. The voltage applied to input terminal 1 is-
It can be seen that the output voltage of the inverter 704 is inverted around a point lower than Vtn. Therefore, the output of the inverter 704 maintains the ground level from the ground level 0 V to the power supply voltage Vdd,
It turns out that the power supply voltage is never reached. The voltage applied to the input terminal 1 ranges from the ground level to the power supply voltage in normal use of the present semiconductor, and the output of the inverter 704 is the power supply voltage in this range. However, when the test mode is desired, a voltage lower than the ground which is not normally used is applied to the input terminal 1 so that the test mode output terminal 3 becomes the power supply voltage and the test mode can be set. I understand.

FIG. 8 shows the switching circuit 603 of FIG. 6 realized by two N-channel MOS transistors. N-channel MOS transistor 805 has its source and substrate connected to node 807, and its gate connected to node 808. N-channel MOS transistor 804
Has its source and substrate connected to node 808 and its gate to ground 0.

FIG. 9 shows the switching circuit 60 of FIG.
3 is realized by a plurality of N-channel MOS transistors. N-channel MOS transistor 905
Is the source and substrate at node 908 and the gate is node 9
09. A plurality of equivalent connections are connected in series to reach an N-channel MOS transistor 904. N-channel MOS transistor 905
Has its source and substrate connected to node 911 and its gate to ground 0.

FIGS. 8 and 9 are described with reference to FIG.
3 and FIG. 23, as in FIG. 21, the horizontal axis indicates the voltage applied to the input terminal 1, and the vertical axis indicates the voltage of the node 911. The broken line indicates the relationship of the voltage applied to the input terminal 1 = the voltage of the node 911.

The voltage at node 909 is an N-channel MOS
The transistor 903 increases the voltage by the threshold voltage of the N-channel MOS transistor 903. This is shown by the solid line 2301. Similarly, the voltage rises by the N-channel MOS transistor connected in series, and the voltage at node 910 is shown by a solid line 2302. N-channel MO having the voltage of node 910 as the source voltage
The S transistor 905 is turned on when a voltage difference between the voltage of the ground 0 and the threshold voltage or more occurs. The state is shown by a solid line 2303. At this time, N channel MO
The conduction resistance of S transistors 903 to 905 is
It is assumed that it is sufficiently smaller than 7.

FIG. 24 shows the output of inverter 906 receiving the voltage of node 911. 23, the horizontal axis represents the voltage applied to the input terminal 1 and the vertical axis represents the inverter 90.
6 is the output voltage. It can be seen that the output voltage of the inverter 905 is inverted when the voltage applied to the input terminal 1 falls below −Vtn. N channel MO
Assuming that n N-channel MOS transistors are connected from the S transistor 903 to the N-channel MOS transistor 905, it can be seen that the output voltage of the inverter 906 starts to be inverted at −n · Vtn. It can be seen that the voltage is lower by (n−1) · Vtn than the voltage in FIG. Therefore, it can be seen that the application of a voltage equal to or lower than the ground voltage can be increased in steps of Vtn. This means that input terminal 1
Even if a signal inputted to the N-channel MOS transistor swings more than the sum of the threshold voltages and may enter the test mode, the N-channel MOS transistors are connected in series in multiple stages, thereby lowering the voltage. To set the test mode. Note that the order of the transistors connected in series does not matter here.

FIG. 10 shows a P-channel MO as a resistance element.
This uses an S transistor. P channel MO
The source and substrate of S transistor 1007 are connected to power supply 9
The gate and the drain are connected to the node 1009. P-channel MOS transistor 1007
By using a P-channel MOS transistor, the resistance can be realized by a normal P-channel MOS transistor without adding a special process for the resistance.

FIG. 11 is a block diagram of another semiconductor input device according to the present invention. Input terminal 1 is electrostatic protection circuit 1
101, one of the outputs, a node 1106, enters the input circuit 1101, and the other ends are the switching circuit (1) 1102 and the switching circuit (3) 1
The signal is input to the control terminal 104. The output of the switching circuit (1) 1102 is connected to the switching circuit (2) 11
03, input to the switching circuit (3) 1104 and the input determination circuit 1105. Switching circuit (3) 11
The other end of the switching circuit 04 is connected to the ground 0, and the control terminal of the switching circuit (3) is connected to the node 1106. The input level determination circuit 1105 outputs the signal to the test mode output terminal 3. Switching circuit (2) 11
Reference numeral 03 has one end connected to the node 1107, the other end connected to the ground 0, and a control terminal connected to the node 1108 output from the input level determination circuit 1105.

The signal input from the input terminal 1 is protected from electrostatic damage by the electrostatic protection circuit 1101, the input circuit 1101 determines a high level or a low level, and the result is output to the output terminal 2.

On the other hand, the signal output from the electrostatic protection circuit 1101 is input to the switching circuit (1) 1102. If the switching circuit (1) 1102 is equal to or lower than a voltage obtained by adding a certain voltage to the power supply voltage of the input circuit 1101, the switching circuit (1) 1102 does not conduct between the node 1106 and the node 1107.
That is, there is no connection between the node 1106 and the node 1107. At this time, if the node 1107 is at the ground level, the input level determination circuit
7 is determined to be low, and a voltage for transmitting the low to the node 1108 is output. If the node 1107 is low, the switching circuit (2) 1103 conducts the node 1107 and the ground 0. The switching circuit (3) has a judgment level between the ground and the power supply voltage.
If 106 is at a high level, node 1107 and ground 0 are turned off. Conversely, if the node 1106 is at the low level, the node 1107 and the ground 0 are made conductive. As a result, the voltage of the node 1107 is lowered to the ground level by the switching circuit (3) 1104. The reduced voltage is input to the input level determination circuit 110.
5 receives. The input level determination circuit 1105 has a determination level between the power supply voltage and the ground, and determines the voltage of the node 1107. In this case, since the node 1107 is at the ground level, the result is determined to be low. The state is output to the test mode output terminal 3.

Here, the signal input from the input terminal 1 is
If the voltage is equal to or higher than a voltage obtained by adding a certain voltage to the power supply voltage, the switching circuit (1) 1102 receiving the voltage
Has a function of conducting between the node 1106 and the node 1107. Therefore, the connection between the node 1106 and the node 1107 is established. At this time, the switching circuit (2) is in a conductive state, but the conduction resistance of the switching circuit (1) 1102 is low, so that the node 1107 rises to near the voltage applied to the input terminal 1. The increased voltage is received by the input level determination circuit 1105. Input level judgment circuit 1
105 has a judgment level between the power supply voltage and the ground,
The voltage of the node 1107 is determined. In this case, since the node 1107 has a voltage higher than the power supply voltage, the result is determined to be high, and the state is output to the test mode output terminal 3. At the same time, the fact that the node 1107 is at the high level is transmitted to the switching circuit (2) 1103 through the node 1108. Switching circuit (2) 11
03 is a non-conductive state between the node 1107 and the ground 0 when the node 1107 is at a high level. Therefore, there is no path through which a current flows between the input terminal 1 and the ground 0, and no unnecessary current flows.

When the signal input from the input terminal 1 is close to the ground level, the potential of the node 1106 also decreases, the switching circuit (3) 1104 becomes conductive, and the node 1107 can be lowered to the ground level. .

FIG. 12 is an expanded version of the block diagram shown in FIG. 11 into a specific circuit. The electrostatic protection circuit is connected between the ground 0 and the node 1208, and an electrostatic protection diode 1201 is provided between the ground 0 and the node 1208. An inverter 1202 is used as an input circuit. A P-channel MOS transistor 1 is used as the switching circuit (1).
203 is used. This P-channel MOS transistor 1203 has its gate connected to power supply voltage 9, its source and substrate at node 1208, and its drain at node 1208.
9 is connected. The node 1209 is connected to two N-channel MOS transistors 1205 and 1206 as switching circuits (2) and (3) and to an inverter 1204 as an input level determining circuit. The output of the inverter 1204 is connected to the test mode output terminal 3.

P channel MOS transistor 1203
Is the threshold voltage of Vtp, and the power supply voltage of the input circuit and the input level determination circuit is Vdd,
When a voltage of dd + Vtp or more is applied, the P-channel MO
Since the gate of the S transistor 1203 is at the power supply voltage Vdd, the P-channel MOS transistor 1203
3 conducts. Suppose N-channel MOS transistor 1
Even if 205 is in the normal conduction state, if the conduction resistance of P-channel MOS transistor 1203 is smaller, node 1209 will be close to the voltage applied to input terminal 1 and, therefore, inverter 1204 having node 1209 as an input. Is low. The node 1211 receiving this state becomes an N-channel MOS transistor 1205
Is turned off. On the other hand, since the node 1208 is at the high level in this state, the inverter 1207 turns off the N-channel MOS transistor 1206 to lower the node 1210 to the low level. Therefore, there is no path for current to flow from the input terminal 1 to the ground 0, so that no current flows even if the input terminal 1 has a high voltage.

When a voltage equal to or lower than Vdd + Vtp is applied to the input terminal 1, the P-channel MOS transistor 120
Since the gate of No. 3 is at the power supply voltage Vdd, the P-channel MOS transistor 1203 is turned off. At this time, until the N-channel MOS transistor 1206 is turned off, the node 1209 is in a state where no connection is made. However, when the input terminal 1 becomes lower than the judgment voltage of the inverter 1207, the inverter 1210
Outputs high and the N-channel MOS transistor 12
06 is made conductive, whereby the node 1209 goes to the ground level, and thus the N-channel MOS transistor 1205 becomes conductive, and thereafter the node 1220
09 is latched at the ground level.

FIG. 13 shows a switching circuit in which N-channel MOS transistors are connected in series in multiple stages as shown in FIG. As a result, the voltage of the input terminal 1 becomes n from the P-channel transistors 1321 to 1303, with the threshold voltage of the P-channel transistor being Vtp.
If there are P-channel transistors, Vdd
It can be seen that if the voltage does not rise to + n · Vtp, no row is output to the test mode output terminal 3. Note that the order of the transistors connected in series does not matter here.

FIG. 14 is a block diagram of another semiconductor input device according to the present invention. Input terminal 1 is electrostatic protection circuit 1
One of the output nodes 1407 is connected to the input circuit 1402 and the other is connected to the switching circuit (1) 1403 and the switching circuit (3) 1
It is input to the control terminal 406. The output of the switching circuit (1) 1403 is output from the switching circuit (2) 14
05, input to the switching circuit (3) 1406 and the input level determination circuit 1404. The other end of the switching circuit (3) 1406 is connected to the power supply 9, and the control terminal of the switching circuit (3) 1406 is connected to the node 14
07. The input level determination circuit 1404 outputs the signal to the test mode output terminal 3. The switching circuit (2) 1405 has one end connected to the node 1408 and the other end connected to a node 1409 output from the input level determination circuit 1404.

The signal input from the input terminal 1 is protected from electrostatic damage by the electrostatic protection circuit 1401, the input circuit 1402 determines whether the signal is at the high level or the low level, and the result is output to the output terminal 2.

On the other hand, the signal output from the electrostatic protection circuit 1401 is input to the switching circuit (1) 1403. If the switching circuit (1) 1403 is at a certain voltage lower than the ground level or higher than a certain level, the switching circuit (1) 1403 does not conduct between the node 1407 and the node 1408. That is, node 1
There is no connection between 407 and node 1408. At this time, if node 1408 is at the power supply voltage level, input level determination circuit 1404 determines that node 1408 is high,
A voltage for transmitting a row to the node 1409 is output. If this node 1408 is high, the switching circuit (2) 14
05 makes the node 1408 and the power supply 9 conductive. The switching circuit (3) 1406 has a judgment level between the ground and the power supply voltage. When the node 1407 is at a low level, the node 1408 and the power supply 9 are turned off. Conversely, if node 1407 is at a high level, node 14
08 and the power supply 9 are made conductive. From this node 14
08 is increased to the power supply voltage level by the switching circuit (3) 1406. The input voltage determination circuit 1404 receives the increased voltage. The input level determination circuit 1404 has a determination level between the power supply voltage and the ground, and determines the voltage of the node 1408. In this case, since the node 1408 is at the power supply voltage level, the result is determined to be high. The state is output to the test mode output terminal 3.

Here, the signal input from the input terminal 1 is
If the voltage is below a certain voltage below the ground, the switching circuit (1) 1403 which has received the voltage turns the node 1
407 and the node 1408 are electrically connected to each other. Therefore, the connection between the node 1407 and the node 1408 is established. At this time, the switching circuit (2) 1405 is conducting, but if the conduction resistance of the switching circuit (1) 1403 is reduced, the node 1408 becomes the input terminal 1
To near the applied voltage. The input level determination circuit 1404 receives the reduced voltage. The input level determination circuit 1404 has a determination level between the power supply voltage and the ground, and determines the voltage of the node 1408. In this case, node 1408 is at a voltage below ground,
The result is determined to be low, and the state is output to the test mode output terminal 3. At the same time, the fact that the node 1408 is at the low level is transmitted to the switching circuit (2) 1405 through the node 1409. The switching circuit (2) 1405 turns off the node 1408 and the power supply 9 when the node 1408 is at the low level. For this reason, there is no path through which a current flows between the input terminal 1 and the power supply 9, and no unnecessary current flows.

When the signal input from input terminal 1 is close to the power supply voltage level, the potential of node 1407 rises, switching circuit (3) 1406 becomes conductive, and node 1408 is raised to the power supply voltage level. Can be done.

FIG. 15 is an expanded version of the block diagram shown in FIG. 14 into a specific circuit. Static electricity protection circuit is power supply 9
And a node 1507, and an electrostatic protection diode 1520 is provided therebetween. An inverter 1501 is used as an input circuit. An N-channel MOS transistor 1502 is used as the switching circuit (1).
I'm using This N-channel MOS transistor 1
Reference numeral 502 connects the gate to the power supply 9, connects the source and the substrate to the node 1507, and connects the drain to the node 1508. Node 1508 is a switching circuit (2),
(3) Two P-channel MOS transistors 1
504 and 1505 and an input level determination circuit connected to the inverter 1503. Inverter 1503
Are connected to the test mode output terminal 3.

N-channel MOS transistor 1502
If a threshold voltage of −Vtn or less is applied to the input terminal 1, the gate of the N-channel MOS transistor 1502 is at ground 0.
N-channel MOS transistor 1502 conducts.
Even if the P-channel MOS transistor 1504 is in the normal conduction state, if the conduction resistance of the N-channel MOS transistor 1502 is smaller, the node 15
08 becomes close to the voltage applied to the input terminal 1, so that the output of the inverter 1503 which receives the node 1508 as an input becomes high. The node 1510 that has received this state
Channel MOS transistor 1504 is turned off. On the other hand, since the node 1507 is at the low level in this state, the inverter 1506 is connected to the node 1505
To a high level, the P-channel MOS transistor 1505 is turned off. Therefore, input terminal 1
There is no path for current to flow from
Therefore, even if the input terminal 1 has a low voltage, no current flows.

When a voltage equal to or higher than -Vtn is applied to the input terminal 1, the gate of the N-channel MOS transistor 1502 is grounded.
The S transistor 1502 is turned off. At this time, node 1508 is in a state where no connection is made until N-channel MOS transistor 1505 is turned off. However, input terminal 1 is connected to inverter 1506
Inverter 1506 outputs a low level to bring N-channel MOS transistor 1505 into a conductive state, whereby node 1508 attains the power supply voltage level and thus P-channel MOS transistor 1
504 becomes conductive, and thereafter node 1508 is latched at the power supply voltage level.

FIG. 16 shows a switching circuit in which N-channel MOS transistors are connected in series in multiple stages as shown in FIG. As a result, the voltage of the input terminal 1 becomes n from the n-channel transistors 1604 to 1602 with the threshold voltage of the n-channel transistor being Vtn.
Assuming that there are N-channel transistors, it is understood that a high output is not output to the test mode output terminal 3 unless the voltage drops to −n · Vtn. Note that the order of the transistors connected in series does not matter here.

Although the embodiment of the present invention has been described above, other developments are conceivable.

[0071]

As described above, by using the semiconductor input device of the present invention, a normal terminal can be used as a test terminal even when it is difficult to add test terminals on a chip.

In addition to the test mode setting, an input circuit which can normally input only binary values can be easily applied to a multi-value input circuit.

Further, the input terminal of the present invention is not limited to the input,
Application is possible even in the case of bidirectional input / output.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram of one embodiment of the present invention.

FIG. 3 is a diagram of one embodiment of the present invention.

FIG. 4 is a diagram of one embodiment of the present invention.

FIG. 5 is a diagram of one embodiment of the present invention.

FIG. 6 is a block diagram of one embodiment of the present invention.

FIG. 7 is a diagram of one embodiment of the present invention.

FIG. 8 is a diagram of one embodiment of the present invention.

FIG. 9 is a diagram of one embodiment of the present invention.

FIG. 10 is a diagram of one embodiment of the present invention.

FIG. 11 is a block diagram of one embodiment of the present invention.

FIG. 12 is a diagram of one embodiment of the present invention.

FIG. 13 is a diagram of one embodiment of the present invention.

FIG. 14 is a block diagram of one embodiment of the present invention.

FIG. 15 is a diagram of one embodiment of the present invention.

FIG. 16 is a diagram of one embodiment of the present invention.

FIG. 17 is a diagram for explaining one embodiment of the present invention.

FIG. 18 is a view for explaining one embodiment of the present invention.

FIG. 19 is a diagram for explaining one embodiment of the present invention.

FIG. 20 illustrates an example of the present invention.

FIG. 21 is a view for explaining one embodiment of the present invention.

FIG. 22 is a view for explaining one embodiment of the present invention.

FIG. 23 is a diagram for explaining one embodiment of the present invention.

FIG. 24 illustrates an example of the present invention.

[Explanation of symbols]

0 Ground 1 Input terminal 2 Output terminal 3 Test mode output terminal 9 Power supply 101, 601, 1101, 1401 Static electricity protection circuit 102, 602, 1101, 1402 Input circuit 103, 603, 1102, 1104, 1103, 14
03, 1406, 1409 Switching circuit 108, 604, 1105, 1409 Input level determination circuit 104, 605, 705 Resistance element 1106 First node 1107 Second node 1121 First terminal 1122 Second terminal 1123 Third terminal 1124 4th terminal 1125 5th terminal 1126 6th terminal 1127 7th terminal 1128 8th terminal 1407 1st node 1408 2nd node 1421 1st terminal 1422 2nd terminal 1423 3rd terminal 1424 4th terminal 1425 5th terminal 1426 6th terminal 1427 7th terminal 1428 8th terminal

Claims (18)

[Claims] An input circuit having an input terminal, inputting a voltage applied from the input terminal to the input terminal through an electrostatic protection circuit, determining the voltage level, and outputting a determination result to a semiconductor internal circuit. A switching circuit in which a first terminal is connected from the input terminal to a first node passing through the electrostatic protection circuit, and a second terminal is connected to a second node, the switching circuit includes: The voltage of the first node, a certain voltage higher than the power supply voltage of the input circuit, to determine the above or less, if the certain voltage or more, the first terminal and the second terminal become conductive, Conversely, if less than a certain voltage, the first terminal and the second terminal become non-conductive, the second node, a resistance element having both ends connected to ground, and the second node as an input. An input level determination circuit that outputs to a test mode output terminal, wherein the input level determination circuit has a determination level between a power supply voltage and a ground, and outputs a result of determining a voltage of the second node. Semiconductor input circuit. 2. The semiconductor input circuit according to claim 1, wherein
The switching circuit includes a first P-channel MOS transistor having a source and a substrate connected to the first node, a gate connected to a power supply, and a drain connected to a second node. Semiconductor input circuit. 3. The semiconductor input circuit according to claim 1, wherein
The switching circuit includes a second P-channel MOS transistor having one end connected to the source and the substrate and the other end connected to the gate and the drain, and one end connected to the source and the substrate. One or more of a third P-channel MOS transistor having a gate as a power supply voltage and a drain at the other end, the second P-channel MOS transistor, and the third P-channel MOS transistor. A semiconductor input circuit characterized in that the semiconductor input circuit is configured by connecting a plurality of serially connected devices. 4. An input circuit having an input terminal, receiving a voltage applied from the input terminal to the input terminal through an electrostatic protection circuit, determining the voltage level, and outputting a result of the determination to a semiconductor internal circuit. A switching circuit in which a first terminal is connected from the input terminal to a first node passing through the electrostatic protection circuit, and a second terminal is connected to a second node, the switching circuit includes: The voltage of the first node is determined to be greater than or less than a certain voltage lower than the power supply voltage of the input circuit.If the voltage is less than a certain voltage, the first terminal and the second terminal become conductive, Conversely, if the voltage is equal to or higher than a certain voltage, the first terminal and the second terminal become non-conductive, the second node, and a resistance element having both ends connected to ground, and the second node as an input. An input level determination circuit that outputs to a test mode output terminal, wherein the input level determination circuit has a determination level between a power supply voltage and a ground, and outputs a result of determining a voltage of the second node. Semiconductor input circuit. 5. The semiconductor input circuit according to claim 4, wherein
The switching circuit includes a first N-channel MOS having a source and a substrate connected to the first node, a gate connected to ground, and a drain connected to a second node.
A semiconductor input circuit comprising a transistor. 6. The semiconductor input circuit according to claim 4, wherein
The switching circuit includes a second N-channel MOS transistor having one end connected to the source and the substrate and the other end connected to the gate and the drain, and one end connected to the source and the substrate. A third N-channel MOS transistor having a gate as a ground and a drain as another end, one or more of the second N-channel MOS transistor and the third N-channel MOS transistor, respectively. A semiconductor input circuit characterized by being connected in series. 7. An input circuit having an input terminal, inputting a voltage applied from the input terminal to the input terminal through an electrostatic protection circuit, determining the voltage level, and outputting a determination result to a semiconductor internal circuit. A first switching circuit having a first terminal connected from the input terminal to a first node passing through the electrostatic protection circuit, and a second terminal connected at a second node; The switching circuit of the first node, the voltage of the certain voltage higher than the power supply voltage of the input circuit, determines or less than or less than, if the certain voltage or more, the first terminal and the second terminal Terminals become conductive, and conversely, if less than a certain voltage, the first terminal and the second terminal become non-conductive, and the second node and the third terminal are connected to the ground and the fourth terminal. The seventh control A second switching circuit having a second node, a third node connected to the second node and a fifth terminal, a ground and a sixth terminal, and a third node connected to the first node and an eighth control terminal. A switching circuit, having the second node as an input, outputting to a test mode output terminal, and an input level determination circuit outputting to the seventh control terminal of the second switching circuit; and Having a determination level between a power supply voltage and ground, outputting a result of determining the voltage of the second node to the test mode output terminal and the seventh control terminal of the second switching circuit, The switching circuit receives an output from the input determination circuit at the seventh control terminal, the third terminal and the fourth terminal become conductive if the second node is low level, If the third terminal and the fourth terminal are non-conductive, the third switching circuit has a judgment level between the power supply voltage and the ground at the control terminal, and the first node is at the low level. Then, the fifth terminal and the sixth terminal become conductive, and conversely, if the level is high, the fifth terminal and the sixth terminal become non-conductive. 8. The semiconductor input circuit according to claim 7, wherein
The first switching circuit includes a first P-channel MOS having a source and a substrate connected to the first node, a gate connected to a power supply, and a drain connected to a second node.
A semiconductor input circuit comprising a transistor. 9. The semiconductor input circuit according to claim 7, wherein
The first switching circuit connects the source and the substrate to a second P-channel MOS transistor having one end connected to the source and the substrate and the other end connected to the gate to the drain. A third P-channel MOS transistor having a gate as a power supply voltage and a drain at another end;
Channel type MOS transistor, and the third P
A semiconductor input circuit comprising one or a plurality of channel type MOS transistors connected in series. 10. The semiconductor input circuit according to claim 7, wherein said second switching circuit has a source and a substrate connected to said ground, a gate connected to a seventh control terminal, and a drain connected to a third terminal. A semiconductor input circuit comprising a fourth N-channel type MOS transistor. 11. The semiconductor input circuit according to claim 7, wherein said fifth switching circuit has an inverter having an eighth control terminal connected to an input, an output of said inverter connected to a gate, a source, And a fifth N connected to the ground and the drain to the third terminal.
A semiconductor input circuit comprising a channel type MOS transistor. 12. An input circuit which has an input terminal, receives a voltage applied from said input terminal to said input terminal through an electrostatic protection circuit, determines said voltage level, and outputs the determined result to a semiconductor internal circuit. A first switching circuit having a first terminal connected from the input terminal to a first node passing through the electrostatic protection circuit, and a second terminal connected to a second node; The switching circuit of the first node determines whether the voltage of the first node is a certain voltage lower than the ground of the input circuit, is greater than or less than, if less than a certain voltage, the first terminal and the second terminal The terminal becomes conductive, and conversely if the voltage is equal to or higher than a certain voltage, the first terminal and the second terminal become non-conductive, and the second node and the third terminal are connected to the power supply and the fourth terminal, Seventh control end A second switching circuit having,
A third switching circuit connected to the second node and the fifth terminal, a power supply and a sixth terminal, and connected to the first node and an eighth control terminal; and An input level determination circuit that outputs a determination level between a power supply voltage and ground, and an input level determination circuit that outputs the determination level to the seventh control terminal of the second switching circuit. And outputting a result of determining the voltage of the second node to the test mode output terminal and the seventh control terminal of the second switching circuit, wherein the second switching circuit includes the input level determination circuit. Is received by the seventh control terminal, the third terminal and the fourth terminal become conductive when the second node is at a high level, and the third terminal when the second node is at a low level. The fourth terminal becomes non-conductive, the third switching circuit has a judgment level between the power supply voltage and the ground at the control terminal, and the fifth terminal and the fifth terminal are connected when the first node is at a high level. A semiconductor input circuit characterized in that the sixth terminal is conductive, and conversely, if the signal is at a low level, the fifth terminal and the sixth terminal are non-conductive. 13. The semiconductor input circuit according to claim 12, wherein said first switching circuit has a source and a substrate connected to said first node, a gate connected to ground,
A semiconductor input circuit comprising a first P-channel MOS transistor having a drain connected to a second node. 14. A semiconductor input circuit according to claim 12, wherein said first switching circuit has one end connected to a source and a substrate and the other end connected to a gate and a drain. A third N-channel MOS transistor having one end connected to a source and a substrate, a gate serving as a ground, and a drain serving as another end, and the second N-channel MOS transistor , And one or more third N-channel MOS transistors connected in series. 15. The semiconductor input circuit according to claim 12, wherein said second switching circuit has a source and a substrate connected to said ground, a gate connected to a seventh control terminal, and a drain connected to a third terminal. And a fourth P-channel MOS transistor. 16. The semiconductor input circuit according to claim 12, wherein said third switching circuit has an inverter having an eighth control terminal connected to an input, an output of said inverter connected to a gate, a source, And a fifth P having a substrate connected to the ground and a drain connected to a third terminal.
A semiconductor input circuit comprising a channel type MOS transistor. 17. The semiconductor input circuit according to claim 1, wherein said electrostatic protection circuit is an electrostatic protection circuit in which no current flows even when a high voltage is applied between a power supply and said input terminal. A semiconductor input circuit characterized by the above-mentioned. 18. The semiconductor input circuit according to claim 4, wherein said electrostatic protection circuit is an electrostatic protection circuit in which no current flows even when a low voltage is applied between a ground and said input terminal. A semiconductor input circuit characterized by the above-mentioned.