CN110808298B - Graded potential barrier low-dark-current mesa photodiode and manufacturing method thereof - Google Patents
Graded potential barrier low-dark-current mesa photodiode and manufacturing method thereof Download PDFInfo
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Abstract
The invention belongs to the technical field of detector chip manufacturing, and relates to a stage potential barrier low dark current mesa photodiode; the mesa photodiode is provided with an N-type mesa, an absorption mesa and a P-type mesa which are connected in a stacking way from top to bottom; the surface of each mesa is covered with a passivation layer; a graded barrier layer is arranged in an absorption table top of the mesa photodiode, and the graded barrier layer has a nine-layer structure from top to bottom; an N electrode is arranged on the N-type table top, a P electrode is arranged on the P-type table top, and the P electrode and the N electrode form a coplanar electrode; the invention reduces the surface leakage current and the body dark current of the mesa photodiode by adopting the hierarchical potential barrier structure, thereby improving the reliability of the mesa photodiode.
Description
Technical Field
The invention belongs to the technical field of detector chip manufacturing, and particularly relates to a graded potential barrier low-dark-current mesa photodiode and a manufacturing method thereof.
Background
With the development of the photodiode towards high speed and high bandwidth, the preparation process gradually changes from a planar process to a mesa process. The mesa etching process destroys the periodic integrity of crystal lattices, exposes the surface of the semiconductor material to the environment, introduces a surface interface state, and inevitably increases surface dark current. The dark current composition also includes: generating a composite current, a diffusion current, an inter-band tunneling current, an auxiliary tunneling current, etc. The high dark current reduces the performance and reliability of the mesa photodiode, and there is a greater risk of failure.
In the prior art, a plurality of mesa photodiodes are prepared, for example, in "a mesa photodiode with a high-reliability NIP structure and a manufacturing method thereof" with patent application number CN201811598480.0, a mesa photodiode is proposed, which comprises a semi-insulating substrate, on which a buffer layer, a contact layer, an absorption layer, a graded layer and a barrier layer are grown; the structure adopts a three-layer mesa chip structure, a passivation layer covers the surface of a mesa, an N electrode is led out from the N-type mesa, and a P electrode is led out from the P-type mesa, so that a coplanar electrode is formed by the N electrode and the P electrode; meanwhile, the P-type layer is placed at the lowest part and is deeply buried in the material, the built-in electric field can be limited at the center in the body through the design, and the leakage current and edge breakdown at the edge of the mesa can be inhibited.
However, in such a structure, the surface leakage current and the body dark current cannot be reduced, and thus a mesa type photodiode capable of reducing the surface leakage current and the body dark current is urgently required.
Disclosure of Invention
In order to solve the problems of the prior art, the invention provides a mesa photodiode with a hierarchical potential barrier and low dark current, which has the following structure:
the mesa photodiode comprises a three-layer mesa structure, namely an N-type mesa a, an absorption mesa b and a P-type mesa c which are connected in a stacking mode from top to bottom, wherein the bottommost layer of the steps of the P-type mesa is a semi-insulating substrate 1; the surface of each mesa of the mesa photodiode is covered with a passivation layer; a graded barrier layer 5 is arranged in an absorption mesa b of the mesa photodiode, and the graded barrier layer 5 sequentially includes from top to bottom: a first N-type InGaAs layer 51, a first N-type delta doping layer 52, a first InAlGaAs non-doped graded layer 53, a first P-type delta doping layer 54, an InAlAs non-doped barrier layer 55, a second P-type delta doping layer 56, a second InAlGaAs non-doped graded layer 57, a second N-type delta doping layer 58 and a second N-type InGaAs layer 59; an N electrode a1 is arranged on the N-type mesa a and extends to the semi-insulating substrate 1 along the N-type mesa a, a P electrode c1 is arranged on the P-type mesa c and extends to the semi-insulating substrate 1 along the P-type mesa c, and the P electrode c1 and the N electrode a1 form a coplanar electrode.
Preferably, the first N-type InGaAs layer 51, the first inalgas non-doped graded layer 53, the second inalgas non-doped graded layer 57, and the second N-type InGaAs layer 59 In the graded barrier layer 5 are made of In0.53AlxGa0.47-xAs, InAlAs non-doped barrier layer 55 is In0.52Al0.48As; wherein the value of x is 0-0.47.
Preferably, the thicknesses of the first N-type delta doped layer 52, the second N-type delta doped layer 58, the first P-type delta doped layer 54 and the second P-type delta doped layer 56 in the graded barrier layer 5 are all 5-10 nm, and the doping concentration is more than 1 × 1018cm-3。
Preferably, the InAlAs-undoped barrier layer 55 of the graded barrier layer 5 has a thickness of 200 to 500nm and a forbidden bandwidth of 1.46 eV.
Preferably, the thicknesses of the first non-inalga doped graded layer 53 and the second non-inalga doped graded layer 57 in the graded barrier layer 5 are both 300 to 800nm, and the forbidden band widths of the first non-inalga doped graded layer 53 and the second non-inalga doped graded layer 57 are varied within the range of 0.74 to 1.46eV according to the variation of x.
Preferably, the conduction band difference Δ Ec of the graded barrier layer 5 ranges: 0.5Ev < Δ Ec <0.85Ev, the valence band difference Δ Ev ranges from: 0< Δ Ev <0.1 eV.
Preferably, the first N-type InGaAs layer 51 and the second N-type InGaAs layer 59 of the graded barrier layer 5 have a thickness of 50 to 200nm and a doping concentration of 1 to 5 × 1016cm-3。
Preferably, the N electrode a1 is led out from the N-type InP contact layer 8 of the N-type mesa a to the surface of the N-type mesa a, and the P electrode c1 is led out from the P-type InGaAs contact layer 3 to the surface of the P-type mesa c.
A method for manufacturing a graded potential barrier low dark current mesa photodiode comprises the following steps:
s1: an intrinsic InP buffer layer 2, a P-type InGaAs contact layer 3, a first InGaAsP gradual change layer 4, a graded barrier layer 5, an InGaAs absorption layer 6, a second InGaAsP gradual change layer 7 and an N-type InP contact layer 8 are sequentially deposited on an InP semi-insulating substrate 1 through Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE);
s2: removing part of the N-type InP contact layer 8 by wet etching, and etching the mesa to the first InGaAsP graded layer 4 to form a first mesa layer;
s3: spin-coating photoresist on the mesa by a photoetching process, exposing and developing the second mesa to be etched, and etching the mesa to the P-type InGaAs contact layer 3 in a wet etching manner to obtain the second mesa;
s4: defining a third layer of table top by photoetching, reserving a P electrode evaporation space, and etching the table top to a semi-insulating substrate in a wet etching mode to obtain a third layer of table top;
s5: cleaning the surface with acetone and ethanol, and passivating the surface of the table top by inductively coupled plasma chemical vapor deposition (SiNx) to a certain thickness
S6: defining a photosensitive surface and an electrode hole by a photoetching process to expose a top layer material of the table top;
s7: preparing a Ti/Pt/Au metal film by using an electron beam evaporation platform, and manufacturing a P/N type electrode by stripping
S8: and thinning the epitaxial wafer to 100-200 μm by using a chemical mechanical polishing mode.
The invention reduces the surface leakage current and the body dark current of the mesa photodiode by adopting the hierarchical potential barrier structure, thereby improving the reliability of the mesa photodiode.
Drawings
FIG. 1 is a schematic diagram of a mesa-type photodiode of the present invention;
FIG. 2 is a schematic diagram of a graded barrier energy band structure according to the present invention;
FIG. 3 is a schematic diagram of a NIP band structure;
FIG. 4 is a schematic diagram of the NIP band structure of the present invention inserted with a graded barrier;
FIG. 5 is a schematic diagram of the structure of the NIP structure photodiode material of the present invention;
the semiconductor device comprises a semiconductor substrate 1, a semi-insulating substrate 2, an intrinsic InP buffer layer 3, a P-type InGaAs contact layer 4, a first InGaAsP gradient layer 5, a grading barrier layer 51, a first N-type InGaAs layer 52, a first N-type delta doping layer 53, a first InAlGaAs gradient layer not doped with InAlGaAs 54, a first P-type delta doping layer 55, an InAlAs barrier layer not doped with InAlAs 56, a second P-type delta doping layer 57, a second InAlGaAs gradient layer not doped with InAlGaAs 58, a second N-type delta doping layer 59, a second N-type InGaAs layer 6, an InGaAs absorption layer 7, a second InGaAsP gradient layer 8 and an N-type InP contact layer;
a. n-type mesa, a1, N electrode, b, absorption mesa, c, P-type mesa, c1, P electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention relates to a mesa photodiode with a hierarchical potential barrier and low dark current, which comprises a three-layer mesa structure, an N-type mesa a, an absorption mesa b and a P-type mesa c which are connected in a stacking mode from top to bottom, and a semi-insulating substrate 1 is arranged on the bottommost layer of the steps of the P-type mesa.
As shown in fig. 2, the surface of each mesa of the mesa-type photodiode is covered with a passivation layer; a graded barrier layer 5 is arranged in an absorption mesa b of the mesa photodiode, and the graded barrier layer 5 sequentially includes from top to bottom: a first N-type InGaAs layer 51, a first N-type delta doping layer 52, a first InAlGaAs non-doped graded layer 53, a first P-type delta doping layer 54, an InAlAs non-doped barrier layer 55, a second P-type delta doping layer 56, a second InAlGaAs non-doped graded layer 57, a second N-type delta doping layer 58 and a second N-type InGaAs layer 59, which have a nine-layer structure; an N electrode a1 is arranged on the N-type mesa a and extends to the semi-insulating substrate 1 along the N-type mesa a, a P electrode c1 is arranged on the P-type mesa c and extends to the semi-insulating substrate 1 along the P-type mesa c, and the P electrode c1 and the N electrode a1 form a coplanar electrode.
The first N-type InGaAs layer 51, the first InAlGaAs non-doped graded layer 53, the second InAlGaAs non-doped graded layer 57 and the second N-type InGaAs layer 59 In the graded barrier layer 5 are made of In0.53AlxGa0.47-xAs, InAlAs non-doped barrier layer 55 is In0.52Al0.48As; wherein the value of x is 0-0.47.
The thicknesses of the first N-type delta doping layer 52 and the second N-type delta doping layer 58 or the first P-type delta doping layer 54 and the second P-type delta doping layer 56 in the graded barrier layer are all 5-10 nm, and the doping concentration is more than 1 multiplied by 1018cm-3。
The N-type delta doping layer or the P-type delta doping layer is used for adjusting the offset of a valence band and a conduction band; hole movement is made easier by eliminating valence band offset, while allowing the conduction band to have sufficient height to block electron movement.
The thickness of the InAlAs non-doped barrier layer 55 in the graded barrier layer is 200-500 nm, and the forbidden bandwidth is 1.46 eV.
The forbidden bandwidth of the non-doped InAlAs barrier layer is higher than that of the N-type InGaAs layer, and a high-band-gap conduction band barrier can be constructed by using the non-doped InAlAs barrier layer 55 to block the flow of electrons.
The thicknesses of the first non-InAlGaAs-doped gradual change layer 53 and the second non-InAlGaAs-doped gradual change layer 57 In the graded barrier layer 5 are 300-800 nm, and when the non-InAlGaAs-doped gradual change layer is not In-doped0.53AlxGa0.47-xAs, In varies with x In the range of 0 to 0.470.53AlxGa0.47-xThe forbidden band width of As is varied within the range of 0.74-1.46 eV.
InAlGaAs graded layer not doped with InAs is used for determining In0.53Ga0.47As and In0.52Al0.48From low band gap to high between AsThe band gap is linearly graded.
The conduction band difference Δ Ec of the graded barrier layer ranges from: 0.5Ev < Δ Ec <0.85Ev, the valence band difference Δ Ev ranges from: 0< Δ Ev <0.1 eV.
The first N-type InGaAs layer 51 and the second N-type InGaAs layer 59 of the graded barrier layer 5 have a thickness of 50 to 200nm and a doping concentration of 1 x 1016cm-3～5×1016cm-3。
The N electrode a1 of the mesa photodiode is led out from the N-type InP contact layer 8 of the N-type mesa a to the surface of the N-type mesa a, and the P electrode c1 is led out from the P-type InGaAs contact layer 3 to the surface of the P-type mesa c.
The graded barrier layer is located at the edge of the depletion region of the mesa-type photodiode.
As shown in FIG. 3, the NIP band structure without the insertion of the grading barrier can be seen from the figure, in which E isCAnd EVThe energy band structures of the two bands are similar.
As shown in FIG. 4, the NIP band structure after the insertion of the graded barrier can be seen as EVThe band structure of (A) is not changed, and ECA significant change in the band structure of (a).
As shown In FIG. 5, the photodiode material structure with NIP structure is formed by sequentially depositing an intrinsic InP buffer layer 2, a P-type InGaAs contact layer 3, a first InGaAsP graded layer 4, and In on an InP semi-insulating substrate 10.53AlxGa0.47-xAs、In0.52Al0.48An As graded barrier layer 5, an InGaAs absorption layer 6, a second InGaAsP graded layer 7 and an N-type InP contact layer 8.
A method for manufacturing a graded potential barrier low dark current mesa photodiode comprises the following steps:
s1: depositing corresponding materials by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE);
s2: removing part of the N-type InP contact layer 8 by wet etching, and etching the mesa to the second N-type InGaAsP graded layer 7 to form a first mesa;
s3: spin-coating photoresist on the mesa by a photoetching process, exposing and developing the second mesa to be etched, and etching the mesa to the P-type InGaAs contact layer 3 in a wet etching manner to obtain the second mesa;
s4: defining a third layer of table top by photoetching, reserving a P electrode evaporation space, and etching the table top to the semi-insulating substrate 1 in a wet etching mode to obtain a third layer of table top;
s5: cleaning the surface with acetone and ethanol, and passivating the surface of the table top by inductively coupled plasma chemical vapor deposition (SiNx) to a certain thickness
S6: defining a photosensitive surface and an electrode hole by a photoetching process to expose a top layer material of the table top;
s7: preparing a layer of titanium Ti or platinum Pt or gold Au metal film by using an electron beam evaporation table, and manufacturing a P-type electrode and an N-type electrode in a stripping mode, wherein the thickness of the P-type electrode and the N-type electrode is
S8: and thinning the epitaxial wafer to 100-200 μm by using a chemical mechanical polishing mode.
The first layer of table top, the second layer of table top and the third layer of table top in the three-layer table top structure are concentric cylinders, the diameter of the first layer of table top is 40-50 mu m, the diameter of the second layer of table top is 60-70 mu m, and the diameter of the third layer of table top is 130-140 mu m.
Preferably, the first layer mesa diameter is 45 μm, the second layer mesa diameter is 65 μm, and the third layer mesa diameter is 135 μm.
After the processes of dielectric film, photoetching and etching, a three-step mesa structure in a concentric circle is formed. The first layer of table top is used as an N electrode contact table, the area of the first layer of table top determines the distribution width of a central electric field, and the lateral expansion range of a depletion region is restricted; the second layer of mesa is etched to a depth reaching the P-type InGaAs contact layer and serves as a P electrode contact mesa, the size of a mesa side wall fringe electric field is reduced along with the increase of the mesa diameter, and the lower fringe electric field is beneficial to reducing the fringe electric leakage of the InGaAs with the narrow forbidden band width of the side wall fringe. The larger the mesa diameter, the wider the carrier collection area. The width of the second layer of the mesa comprehensively considers the fringe electric field and the carrier collection area to obtain the minimum dark current; and directly etching the third layer of table top to the semi-insulating substrate to place the P electrode bonding pad and the N electrode bonding pad. In the wet etching process, defect damage is avoided, and the side wall of the table top is smooth and continuous. The mesa passivation process can effectively reduce the surface recombination center of the material and has good interface state.
And defining a P electrode or an N electrode by photoetching and evaporation processes. The electrode preparation process adopts a metal film layer with good adhesiveness to form good ohmic contact with the material. The electrode shape should avoid peak protrusion to prevent local joule heating. The thickness of the side wall climbing electrode meets the requirement of the working condition of the maximum absolute rated value.
Finishing the preparation of the chip through a thinning process; and selecting proper thinning thickness and abrasive size to reduce the number of back defects.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A mesa photodiode with a hierarchical potential barrier and low dark current comprises a three-layer mesa structure, an N-type mesa (a), an absorption mesa (b) and a P-type mesa (c) which are connected in a stacking mode from top to bottom, and a semi-insulating substrate (1) is arranged at the bottommost layer of a step of the P-type mesa (c); the mesa-type photodiode is characterized in that the surface of each layer of mesa is covered with a passivation layer; a graded barrier layer (5) is arranged in an absorption mesa (b) of the mesa photodiode, and the graded barrier layer (5) sequentially comprises from top to bottom: the solar cell comprises a first N-type InGaAs layer (51), a first N-type delta doping layer (52), a first InAlGaAs non-doped gradient layer (53), a first P-type delta doping layer (54), an InAlAs non-doped barrier layer (55), a second P-type delta doping layer (56), a second InAlGaAs non-doped gradient layer (57), a second N-type delta doping layer (58) and a second N-type InGaAs layer (59); an N electrode (a1) is arranged on the N-type mesa (a) and extends to the semi-insulating substrate (1) along the N-type mesa (a), a P electrode (c1) is arranged on the P-type mesa (c) and extends to the semi-insulating substrate (1) along the P-type mesa (c), and the P electrode (c1) and the N electrode (a1) form a coplanar electrode.
2. The graded barrier low dark current mesa photodiode of claim 1, wherein: the first N-type InGaAs layer (51), the first InAlGaAs non-doped graded layer (53), the second InAlGaAs non-doped graded layer (57) and the second N-type InGaAs layer (59) In the graded barrier layer (5) are made of In0.53AlxGa0.47-xAs, non-InAlAs doped barrier layer (55) is In0.52Al0.48As; wherein the value of x is 0-0.47.
3. The graded barrier low dark current mesa photodiode of claim 2, wherein: the thicknesses of the first N type delta doping layer (52), the second N type delta doping layer (58) or the first P type delta doping layer (54) and the second P type delta doping layer (56) in the graded barrier layer (5) are all 5-10 nm, and the doping concentration is more than 1 x 1018cm-3。
4. The graded barrier low dark current mesa photodiode of claim 2, wherein: the thickness of the InAlAs non-doped barrier layer (55) in the graded barrier layer (5) is 200-500 nm, and the forbidden bandwidth is 1.46 eV.
5. The graded barrier low dark current mesa photodiode of claim 2, wherein: the thicknesses of the first InAlGaAs non-doped gradual change layer (53) and the second InAlGaAs non-doped gradual change layer (57) in the grading barrier layer (5) are both 300-800 nm, and the forbidden band widths of the first InAlGaAs non-doped gradual change layer (53) and the second InAlGaAs non-doped gradual change layer (57) are changed within the range of 0.74-1.46 eV along with the change of x.
6. The graded barrier low dark current mesa photodiode of claim 2, whereinIn the following steps: the first N-type InGaAs layer (51) and the second N-type InGaAs layer (59) of the graded barrier layer (5) both have a thickness of 50-200 nm and a doping concentration of 1 × 1016cm-3～5×1016cm-3。
7. The graded barrier low dark current mesa photodiode of claim 2, wherein: the conduction band difference delta Ec range of the graded barrier layer (5) is as follows: 0.5Ev < Δ Ec <0.85Ev, the valence band difference Δ Ev ranges from: 0< Δ Ev <0.1 eV.
8. The mesa type photodiode of claim 1, wherein the N electrode (a1) is extracted from the N-type InP contact layer (8) of the N-type mesa (a) to the surface of the N-type mesa (a), and the P electrode (c1) is extracted from the P-type InGaAs contact layer (3) of the P-type mesa (c) to the surface of the P-type mesa (c).
9. A method for manufacturing a mesa photodiode with a graded potential barrier and low dark current is characterized by comprising the following steps:
s1: sequentially depositing an intrinsic InP buffer layer (2), a P-type InGaAs contact layer (3), a first InGaAsP gradient layer (4), a graded barrier layer (5), an InGaAs absorption layer (6), a second InGaAsP gradient layer (7) and an N-type InP contact layer (8) on an InP semi-insulating substrate (1) through metal organic compound chemical vapor deposition or molecular beam epitaxy;
s2: removing part of the N-type InP contact layer (8) by adopting a wet etching mode, and etching the mesa to the second InGaAsP gradual change layer (7) to form a first layer mesa;
s3: spin-coating photoresist on the mesa by a photoetching process, exposing and developing the second layer mesa to be corroded, and etching the mesa to the P-type InGaAs contact layer (3) in a wet corrosion mode to obtain the second layer mesa;
s4: defining a third layer of table top by photoetching, reserving a P electrode evaporation space, and etching the table top to the semi-insulating substrate (1) in a wet etching mode to obtain a third layer of table top;
s5: surface cleaning with acetone and ethanolWashing, adopting inductively coupled plasma chemical vapor deposition SiNx to passivate the surface of the table top to a certain thickness
S6: defining a photosensitive surface and an electrode hole by a photoetching process to expose a top layer material of the table top;
s7: preparing a layer of titanium Ti, platinum Pt and gold Au metal film by using an electron beam evaporation table, and manufacturing a P-type electrode and an N-type electrode in a stripping mode, wherein the thickness of the P-type electrode and the N-type electrode is
S8: and thinning the epitaxial wafer to 100-200 μm by using a chemical mechanical polishing mode.
10. The method according to claim 9, wherein the first, second and third mesas are concentric cylinders, the diameter of the first mesa is 40-50 μm, the diameter of the second mesa is 60-70 μm, and the diameter of the third mesa is 130-140 μm.
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