CN110808206A - Method for reducing number of photomasks used in flash memory flow sheet and application thereof - Google Patents
Method for reducing number of photomasks used in flash memory flow sheet and application thereof Download PDFInfo
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- CN110808206A CN110808206A CN201911094242.0A CN201911094242A CN110808206A CN 110808206 A CN110808206 A CN 110808206A CN 201911094242 A CN201911094242 A CN 201911094242A CN 110808206 A CN110808206 A CN 110808206A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
The invention relates to the technical field of semiconductor manufacturing, and discloses a method for reducing the number of photomasks used in flash memory flow sheets and application thereof. The invention greatly reduces the cost of the photomask, is suitable for the design and development of new circuits needing to manufacture a small number of wafers, can effectively save the research and development cost of projects, and has practical value.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for reducing the number of photomasks used in flash memory flow sheets and application thereof.
Background
In the process of chip development, besides circuit design, an entity wafer is actually manufactured through wafer flow, and then final function test and verification are completed after the chip is prepared through cutting and packaging.
Generally, the development of new technology applications will have several stages, and it will take several wafer runs to verify the chips and improve the functions in the early stages. The stage is purely input, the number of wafers of the tape-out is not large, but a complete set of photomask still needs to be prepared, the cost of the photomask is a large proportion of the tape-out cost of the new product wafer, and the photomask cannot be used in mass production in the later period, so that certain waste of resources is caused.
As is well known, the floating gate flash process is a process technology for manufacturing NOR flash chips, which is a very common chip for storing small-capacity data and program codes. However, the present applicant has developed the first type of integrated storage and computation chip in China based on the NOR flash architecture, and the NOR flash architecture is used for performing matrix computation and processing of data, which is a new application in the prior art, so that research and development verification of new technologies are required, and these technologies do not yield in the early stage of investment.
One of the methods in the prior art is to use an MPW (multi-project wafer) mode in logic chip generation to save the cost in project development, specifically, a set of masks is published to carry a plurality of products of a plurality of design companies, and after wafer tape-out is completed, chips are respectively cut for verification, which is also low in cost, but the limitation of this mode is:
1. the MPW is generally a logic process, for example, a specific process technology such as a floating gate type flash memory is adopted, so that enough products are likely to be accumulated to be used as wafer flow sheets;
2. not in time, the users need to wait for enough products of different companies to be made together;
3. privacy is poor, and there is a risk of leakage in the information due to the aggregation of information on circuit designs involving different companies.
Disclosure of Invention
To overcome the disadvantages of the prior art, the present invention provides a method for reducing the number of masks used in flash memory tape-out and the application thereof, so as to solve the problems in the background art.
The technical scheme adopted by the invention for solving the technical problems is as follows: a method of reducing the number of masks used in flash tape-out, comprising:
collecting all photomask parameters of the existing photomask group in the flash memory tape-out, and classifying the photomask parameters according to the parameters, wherein the parameters comprise photomask identification numbers, photomask types, seal film types, photomask grades, pattern brightness and pattern types;
carrying out merging operation on all photomasks in the existing photomask group according to the photomask type, the sealing film type, the pattern brightness and the pattern type parameter consistency to form a new photomask group, and sequentially carrying out photomask preparation;
and performing subsequent flow film processes including exposure, development and photoetching by using the prepared photomask.
Preferably, the reticle level after merging is not lower than the highest level of the reticle levels before merging.
Preferably, the number of the photomasks in the existing photomask set is 28, and the number of the photomasks in the new photomask set is 11.
Preferably, the number of the photomasks to be combined each time is not more than 4.
Preferably, the performing the merge operation includes:
equally arranging a new photomask area on the new photomask according to one fourth of the size of the original photomask area; and arranging shielding areas among different new photomask areas on the new photomask.
Preferably, the width of the shielding region is not less than 625um, and the shielding region is a chromium region.
Preferably, the performing the merge operation further comprises:
and arranging the alignment mark, the process monitoring structure and the electrical property monitoring structure on the original photomask on a new cutting path in the new photomask, wherein the area of the new cutting path is one fourth of the area of the cutting path on the original photomask.
Preferably, when performing exposure, lithography using the merged reticle, different lithography steps use different associated new reticle areas on the reticle.
The invention also provides a preparation method of the flash memory chip, which comprises the steps of the method for reducing the number of the photomasks used in the flash memory flow sheet.
The invention also provides a flash memory chip prepared by the preparation method.
Compared with the prior art, the invention has the following beneficial effects:
the invention is suitable for being used in the stage of research, development and verification of a new technology, slightly increases about 60 hours on the basis of sacrificing a small amount of wafer flow time and verifying the total process time of the wafer flow, greatly reduces the cost of the photomask under the condition that the cost of the wafer is increased, and can be combined into 11 photomasks by 28 photomasks originally, thereby being suitable for the condition that a small amount of wafers need to be manufactured, particularly the design of a new circuit with the total wafer number less than 100, and effectively saving the research and development cost of a project under the condition that the cost of the photomask accounts for about 80% of the cost of the new product wafer flow.
Further salient features and significant advances with respect to the present invention over the prior art are described in further detail in the examples section.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings: FIG. 1 is a schematic structural view of an original mask A in example 1; FIG. 2 is a schematic structural view of a reticle B in example 1; FIG. 3 is a schematic structural view of a reticle C in example 1;
FIG. 4 is a schematic structural view of a reticle D in example 1;
FIG. 5 is a diagram illustrating a new mask structure generated after merging the original masks A, B, C, D in example 1;
FIG. 6 is a schematic structural view of a reticle A1 according to example 1;
FIG. 7 is a schematic structural view of a reticle B1 according to example 1;
FIG. 8 is a schematic structural view of a reticle C1 used in example 1;
FIG. 9 is a schematic diagram of a new photomask structure generated after merging original photomasks A1, B1 and C1 in example 1;
FIG. 10 is a schematic view of the original mask A2 according to example 1;
FIG. 11 is a schematic structural view of a reticle B2 according to example 1;
FIG. 12 is a schematic diagram illustrating a new mask structure generated after merging original masks A2 and B2 in example 1;
FIG. 13 is a schematic view of the original mask A3 in example 1;
FIG. 14 is a diagram illustrating a new mask structure generated after merging the original mask A3 in example 1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. It should be noted that certain names are used throughout the specification and claims to refer to particular components. It will be understood that one of ordinary skill in the art may refer to the same component by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. As used in the specification and claims of this application, the terms "comprises" and "comprising" are intended to be open-ended terms that should be interpreted as "including, but not limited to," or "including, but not limited to. The embodiments described in the detailed description are preferred embodiments of the present invention and are not intended to limit the scope of the present invention.
Example 1
A method for reducing the number of photomasks used in flash memory tape-out in the present embodiment includes: collecting all photomask parameters of the existing photomask group in the flash memory flow sheet, wherein the number of photomasks in the existing photomask group is 28, and classifying the photomasks according to the parameters, wherein the parameters comprise photomask identification numbers, photomask types, sealing film types, photomask grades, graph brightness and graph types;
the method for combining the photomasks with the consistent photomask type, sealed film type, pattern brightness and pattern type parameters specifically comprises the following steps: equally arranging a new photomask area on the new photomask according to one fourth of the size of the original photomask area; setting a shielding area between different new photomask areas on the new photomask; the width of the shielding area is not less than 625um, and the shielding area can be a chromium area;
arranging the alignment mark, the process monitoring structure and the electrical property monitoring structure on the original photomask on a new cutting path in the new photomask, wherein the area of the new cutting path is one fourth of the area of the cutting path on the original photomask, and the area/width of the cutting path can be adjusted according to actual conditions;
forming a new photomask group when the combined photomask grade is not lower than the highest grade in the photomask grades before combination, wherein the number of photomasks in the new photomask group is 11, and the photomasks are prepared in sequence, and the number of photomasks combined each time in the combination process is not more than 4;
performing subsequent flow film processes including exposure, development and photoetching by using the prepared photomask; in particular, when performing exposure, lithography using the merged reticle, different lithography steps use different new reticle areas associated with the reticle.
| Original light cover identification number | Name of photomask | Photomask grading | Mask type | Type of sealing film | Pattern shading | Kind of pattern |
| 1 | CAA | M | HT_PSM | A | Dark | Line |
| 2 | PAA | G | BIM | B | Dark | Line |
| 3 | NWH | B | BIM | B | Clear | Line |
| 4 | PWH | B | BIM | B | Clear | Line |
| 5 | TOW | D | BIM | B | Clear | Line |
| 6 | ONO | C | BIM | B | Dark | Line |
| 7 | PW | B | BIM | B | Dark | Line |
| 8 | NW | B | BIM | B | Clear | Line |
| 9 | DG | D | BIM | B | Clear | Line |
| 10 | CG | M | HT_PSM | A | Dark | Line |
| 11 | GP | H | BIM | B | Dark | Line |
| 12 | NLH | D | BIM | B | Clear | Line |
| 13 | PLH | D | BIM | B | Clear | Line |
| 14 | SAS | J | BIM | B | Dark | Line |
| 15 | NLL | D | BIM | B | Clear | Line |
| 16 | PLL | D | BIM | B | Clear | Line |
| 17 | SN | D | BIM | B | Clear | Line |
| 18 | SP | D | BIM | B | Clear | Line |
| 19 | SAB | D | BIM | B | Dark | Line |
| 20 | CT | M | HT_PSM | A | Clear | Hole |
| 21 | M1 | M | HT_PSM | A | Clear | Line |
| 22 | V1 | J | HT_PSM | B | Clear | Hole |
| 23 | M2 | K | BIM | B | Clear | Line |
| 24 | V2 | J | HT_PSM | B | Clear | Hole |
| 25 | M3 | I | BIM | B | Clear | Line |
| 26 | PA | D | BIM | B | Clear | Line |
| 27 | ALPA | D | BIM | B | Dark | Line |
| 28 | TMR | A | BIM | B | Clear | Line |
TABLE 1
Referring to table 1, which is a list of the number of original photomasks and parameters, in this embodiment, photomask parameters in the floating gate type flash memory process production are listed, and include the number of layers, the photomask type, the seal film type, the photomask grade, the pattern brightness and darkness, and the pattern type for classification, the number of original photomasks is 28, referring to table 2, the number of photomasks after parameter optimization and the specific classification are 11 photomasks after combination optimization;
TABLE 2
Meanwhile, the original alignment mark, the original process monitoring structure and the original electrical monitoring structure need to be arranged in the cutting channel of the original quarter-sized area. If the arrangement is not available, the width of the cutting path can be properly increased; and (5) after the photomask is made, producing by using a new photomask.
The requirement that a plurality of photomasks are reduced in original size and combined into one photomask is met, the 4 parameters of the photomask type, the sealing film type, the pattern brightness and the pattern type are completely consistent, the photomask with the low precision grade on the photomask grade can be produced by using the photomask with the higher precision grade, otherwise, the photomask cannot be produced, and the layout area after the circuit integration is about one fourth of the original photomask area
After the photomask is manufactured, the manufactured photomask can be used for production, the number of the photomasks is 11, a plurality of (at most 4) photoetching steps share one photomask for exposure, and when the same photomask is used for photoetching, different photoetching steps use different areas of the same photomask, and the area size is about one fourth of the original area size.
To further understand the merging scheme of the present invention, examples of four cases in merging are given in the present embodiment:
fig. 1-5 are schematic diagrams of combining four photomasks into a new photomask, wherein fig. 1 is an original photomask a, fig. 2 is an original photomask B, fig. 3 is an original photomask C, fig. 4 is an original photomask D, and fig. 5 is a schematic diagram of a new photomask structure generated after combining the original photomasks A, B, C, D, wherein the size of the photolithography area including ABCD is one fourth of the original size; the new masks with the new mask identification numbers 1, 2, 4, 5 in table 2 are all obtained by the merging method;
fig. 6-9 are schematic diagrams showing three photomasks combined into a new photomask, wherein fig. 6 is an original photomask a1, fig. 7 is an original photomask B1, fig. 8 is an original photomask C1, fig. 9 is a new photomask generated after combining the original photomasks a1, B1 and C1, the size of the photoetching area containing a1, B1 and C1 is one fourth of the original size, and the new photomask has a blank about one fourth of the available area; the new reticle in table 2 with the new reticle identification number 6 was obtained for this merging method;
please refer to fig. 10-12, which are schematic diagrams of merging 2 photomasks into a new photomask, wherein fig. 10 is an original photomask a2, fig. 11 is an original photomask B2, fig. 12 is a new photomask generated after merging the original photomasks a2 and B2, and the size of the new photomask including the photolithography areas a2 and B2 is one fourth of the original size; the new mask will have a blank of about one-half of the available area; the new masks in table 2 with the new mask identification numbers 7, 8, 9 were obtained for this merging method;
referring to fig. 13-14, which are schematic diagrams of merging 1 mask into a new mask, wherein fig. 13 is an original mask A3, and fig. 14 is a new mask generated after merging the original mask A3, which includes a lithography area A3, which is one-fourth of the original size; the new mask will have about three quarters of the available area blank; the new masks identified by the mask numbers 3, 10, and 11 in table 2 are obtained by this merging method, because the front and rear masks are used together in the ic manufacturing process to manufacture the circuit correctly, so even if there is only one mask, the pattern is processed in the same way to merge.
The invention provides a manufacturing method for reducing the number of used photomasks in a floating gate type flash memory flow sheet, which is suitable for being used in the research, development and verification stage of a new technology and can effectively save the development cost of a project.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A method for reducing the number of masks used in flash tape-out, comprising:
collecting all photomask parameters of the existing photomask group in the flash memory tape-out, and classifying the photomask parameters according to the parameters, wherein the parameters comprise photomask identification numbers, photomask types, seal film types, photomask grades, pattern brightness and pattern types;
carrying out merging operation on all photomasks in the existing photomask group according to the photomask type, the sealing film type, the pattern brightness and the pattern type parameter consistency to form a new photomask group, and sequentially carrying out photomask preparation;
and performing subsequent flow film processes including exposure, development and photoetching by using the prepared photomask.
2. The method of claim 1, wherein the merged mask level is not lower than the highest level of the mask levels before merging.
3. The method of claim 1, wherein the number of masks in the existing mask set is 28, and the number of masks in the new mask set is 11.
4. The method of claim 1, wherein the number of masks used in the flash memory stream is not more than 4 masks per merge.
5. The method of claim 1, wherein the performing the merge operation comprises:
equally arranging a new photomask area on the new photomask according to one fourth of the size of the original photomask area;
and arranging shielding areas among different new photomask areas on the new photomask.
6. The method of claim 5, wherein the width of the mask area is not less than 625 μm, and the mask area is a chrome area.
7. The method of claim 5, wherein the performing the merge operation further comprises:
and arranging the alignment mark, the process monitoring structure and the electrical property monitoring structure on the original photomask on a new cutting path in the new photomask.
8. The method of claim 1, wherein different photolithography steps use different associated new mask areas on the mask when performing exposure and photolithography using the merged mask.
9. A method for manufacturing a flash memory chip, comprising the steps of the method for reducing the number of photomasks used in a flash memory tape-out according to any of claims 1 to 8.
10. A flash memory chip prepared by the method of claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911094242.0A CN110808206A (en) | 2019-11-11 | 2019-11-11 | Method for reducing number of photomasks used in flash memory flow sheet and application thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911094242.0A CN110808206A (en) | 2019-11-11 | 2019-11-11 | Method for reducing number of photomasks used in flash memory flow sheet and application thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710851B1 (en) * | 2002-01-29 | 2004-03-23 | Lsi Logic Corporation | Multi pattern reticle |
| CN101656225A (en) * | 2008-08-22 | 2010-02-24 | 台湾积体电路制造股份有限公司 | Hybrid multi-layer photo-mask set and manufacturing method thereof |
| CN105974729A (en) * | 2016-05-25 | 2016-09-28 | 京东方科技集团股份有限公司 | Mask plate management system and mask plate use method |
-
2019
- 2019-11-11 CN CN201911094242.0A patent/CN110808206A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710851B1 (en) * | 2002-01-29 | 2004-03-23 | Lsi Logic Corporation | Multi pattern reticle |
| CN101656225A (en) * | 2008-08-22 | 2010-02-24 | 台湾积体电路制造股份有限公司 | Hybrid multi-layer photo-mask set and manufacturing method thereof |
| CN105974729A (en) * | 2016-05-25 | 2016-09-28 | 京东方科技集团股份有限公司 | Mask plate management system and mask plate use method |
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Application publication date: 20200218 |