CN110798068A - Boosting circuit of CPU direct drive MOS tube - Google Patents
Boosting circuit of CPU direct drive MOS tube Download PDFInfo
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- 238000012935 Averaging Methods 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/1557—Single ended primary inductor converters [SEPIC]
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Abstract
The invention discloses a booster circuit for directly driving an MOS (metal oxide semiconductor) transistor by a CPU (central processing unit), and relates to the field of electronic circuits. The booster circuit comprises a power supply input end, a boost inductor, a rectification and overshoot suppression circuit and a boost output end which are sequentially connected, and further comprises a CPU and a first MOS tube. The rectification and overshoot suppression circuit comprises a third capacitor, a first diode and a third MOS tube which are connected in parallel. According to the invention, the pulse with a certain duty ratio is output through the PWM signal output pin of the CPU to directly drive the boost inductor and the first MOS tube, and the boost inductor is electrified to store energy during the conduction period of the first MOS tube; during the turn-off period of the first MOS tube, the stored energy of the boost inductor is changed into self-inductance high-voltage pulse, and the self-inductance high-voltage pulse is converted into high-voltage direct current after rectification and filtering to supply power to a load. The rectification and overshoot suppression circuit comprises a first diode (rectifier diode), a third MOS (metal oxide semiconductor) tube and a third capacitor which are connected in parallel, and the transient voltage overshoot suppression circuit is composed of the third capacitor and can suppress transient surge of the boost output voltage under the condition that the load is suddenly reduced or disappears.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a booster circuit for directly driving an MOS (metal oxide semiconductor) transistor by a CPU (central processing unit).
Background
In the prior art, a PWM port of a CPU is adopted to directly drive a transistor or an MOS transistor in some product designs, and the voltage is converted into a boost voltage through a boost inductor, a diode rectifier, and a capacitor filter, and the boost voltage is output to a specific load to work, so as to replace a special boost chip.
However, most of such circuits do not have closed-loop feedback control of output voltage at present, and even if the circuits have closed-loop feedback control, the problem of transient surge of boost output voltage under the condition that the load suddenly becomes small or the load disappears cannot be solved, because the CPU needs software processing time to perform a plurality of a/D sampling and digital filtering operations on the changed output voltage, and the response speed is relatively slow. During the period, if the external load is suddenly changed or disconnected, the load current is suddenly reduced or disappeared, and the CPU cannot calculate the effective value of the boost output voltage and reduce the PWM duty ratio, so that the PWM driving waveform output by the CPU still continues to drive the boost circuit according to the original duty ratio, the actual boost capacity is obviously larger than the reduced load consumption, the boost output voltage is instantaneously increased, and even the load is broken down due to abnormal high voltage output. If the beauty instrument is in contact with the skin of a human body, the user can feel uncomfortable when the beauty instrument is used. Therefore, how to suppress the transient surge of the boost output voltage under the condition that the load current suddenly decreases or disappears is a technical difficulty of directly driving the MOS tube boost circuit by the CPU.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a booster circuit for directly driving an MOS (metal oxide semiconductor) transistor by a CPU (central processing unit), which can inhibit the transient surge of the boost output voltage under the condition that the load is suddenly reduced or disappears.
One embodiment of the invention provides a booster circuit of a CPU direct drive MOS tube, which comprises a power supply input end, a booster inductor, a CPU, a first MOS tube, a rectification and overshoot suppression circuit and a boost output end, wherein the power supply input end is respectively connected with one end of the booster inductor and the input end of the CPU;
the rectification and overshoot suppression circuit comprises a third capacitor, a first diode and a third MOS tube which are connected in parallel, the boosting inductor is respectively connected with the anode of the first diode and the drain electrode of the third MOS tube, the cathode of the first diode and the source electrode of the third MOS tube are connected with the boosting output end, and the grid electrode of the third MOS tube is grounded through the third capacitor.
The booster circuit of the CPU direct drive MOS tube of the embodiment of the invention has at least the following beneficial effects:
the method comprises the steps that pulses with a certain duty ratio are output through a PWM signal output pin of a CPU to directly drive a boosting inductor and a first MOS (metal oxide semiconductor) tube, and the boosting inductor is electrified to store energy during the conduction period of the first MOS tube; during the turn-off period of the first MOS tube, the stored energy of the boost inductor is changed into self-inductance high-voltage pulse, and the self-inductance high-voltage pulse is converted into direct current with higher voltage after rectification and filtering to supply power to a load. The rectification and overshoot suppression circuit comprises a first diode (rectifier diode), a third MOS (metal oxide semiconductor) tube and a third capacitor which are connected in parallel, and the transient voltage overshoot suppression circuit is composed of the third capacitor and can suppress transient surge of the boost output voltage under the condition that the load is suddenly reduced or disappears.
According to another embodiment of the present invention, a second MOS transistor is further connected between the boost inductor and the rectifying and overshoot suppression circuit, a SW pin of the CPU is connected to a gate of the second MOS transistor, the boost inductor is connected to a source of the second MOS transistor, and a drain of the second MOS transistor is connected to an anode of the first diode and a drain of the third MOS transistor, respectively.
According to another embodiment of the present invention, the CPU directly drives the boost circuit of the MOS transistor, and the rectifying and overshoot suppressing circuit further includes a third resistor, one end of the third resistor is connected to one end of the third capacitor, and the other end of the third resistor is connected to the source of the third MOS transistor.
According to another embodiment of the present invention, the power supply input end includes a first capacitor and a second capacitor, an anode of the first capacitor is connected to one end of the boost inductor, a cathode of the first capacitor is grounded, one end of the second capacitor is connected to one end of the boost inductor, and another end of the second capacitor is grounded.
According to another embodiment of the present invention, the boost output terminal includes a fourth capacitor and a fifth capacitor, an anode of the fourth capacitor is connected to a cathode of the first diode and a source of the third MOS transistor, a cathode of the fourth capacitor is grounded, one end of the fifth capacitor is connected to a cathode of the first diode and a source of the third MOS transistor, and another end of the fifth capacitor is grounded.
According to other embodiments of the present invention, the CPU directly drives the boost circuit of the MOS transistor, the boost circuit further includes a voltage detection circuit, an input end of the voltage detection circuit is connected to the boost output end, and an output end of the voltage detection circuit is connected to the a/D pin of the CPU.
According to other embodiments of the present invention, the CPU directly drives the boost circuit of the MOS transistor, and the voltage detection circuit includes a fourth resistor, a fifth resistor, and a sixth capacitor. One end of the fourth resistor is connected with the boosting output end, the other end of the fourth resistor is respectively connected with one end of the fifth resistor and the A/D pin of the CPU, the other end of the fifth resistor is grounded, and the A/D pin of the CPU is grounded through the sixth capacitor.
Drawings
FIG. 1 is a circuit block diagram of a voltage boosting circuit of an embodiment of the present invention in which a CPU directly drives a MOS transistor;
fig. 2 is a schematic circuit diagram of a voltage boosting circuit according to an embodiment of the present invention, in which a CPU directly drives a MOS transistor.
Detailed Description
The concept and technical effects of the present invention will be clearly and completely described below in conjunction with the embodiments to fully understand the objects, features and effects of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and those skilled in the art can obtain other embodiments without inventive effort based on the embodiments of the present invention, and all embodiments are within the protection scope of the present invention.
In the description of the present invention, if an orientation description is referred to, for example, the orientations or positional relationships indicated by "upper", "lower", "front", "rear", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, only for convenience of describing the present invention and simplifying the description, but not for indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. If a feature is referred to as being "disposed," "secured," "connected," or "mounted" to another feature, it can be directly disposed, secured, or connected to the other feature or indirectly disposed, secured, connected, or mounted to the other feature.
In the description of the embodiments of the present invention, if "a number" is referred to, it means one or more, if "a plurality" is referred to, it means two or more, if "greater than", "less than" or "more than" is referred to, it is understood that the number is not included, and if "greater than", "lower" or "inner" is referred to, it is understood that the number is included. If reference is made to "first" or "second", this should be understood to distinguish between features and not to indicate or imply relative importance or to implicitly indicate the number of indicated features or to implicitly indicate the precedence of the indicated features.
Example one
Referring to fig. 1, a circuit block diagram of a voltage boosting circuit for a CPU to directly drive a MOS transistor in an embodiment of the present invention is shown, which specifically includes: the power supply circuit comprises a power supply input end, a boosting inductor, a CPU, a first MOS (metal oxide semiconductor) tube, a rectification and overshoot suppression circuit and a boosting output end. The power supply input end is connected with one end of the boosting inductor and the input end of the CPU respectively, the other end of the boosting inductor is connected with the boosting output end through the rectification and overshoot suppression circuit, the boosting output end is used for being connected with a load, the other end of the boosting inductor is further connected with the PWM signal output pin of the CPU through the first MOS tube, the other end of the boosting inductor is connected with the drain electrode of the first MOS tube, the PWM signal output pin of the CPU is connected with the grid electrode of the first MOS tube, and the source electrode of the first MOS tube is grounded.
In the embodiment, the pulse with a certain duty ratio is output through the PWM signal output pin of the CPU to directly drive the boost inductor and the first MOS tube, and the boost inductor is electrified to store energy during the conduction period of the first MOS tube; during the turn-off period of the first MOS tube, the stored energy of the boost inductor is changed into self-inductance high-voltage pulse, and the self-inductance high-voltage pulse is converted into direct current with higher voltage after rectification and filtering to supply power to a load.
In this embodiment, a second MOS transistor is further connected between the boost inductor and the rectification and overshoot suppression circuit, a SW pin of the CPU is connected to a gate of the second MOS transistor, the boost inductor is connected to a source of the second MOS transistor, and a drain of the second MOS transistor is connected to an anode of the first diode and a drain of the third MOS transistor, respectively.
In order to prevent the transient surge problem of the boost output voltage under the abnormal conditions of sudden reduction or disappearance of the load current and the like, the rectification and overshoot suppression circuit comprises a first diode (rectifier diode), a third MOS (metal oxide semiconductor) tube and a third capacitor which are responsible for rectification. Specifically, under the conditions that the second MOS transistor is turned on and the boost circuit normally works, the energy generated by boosting and the energy consumed by the load reach a staged balance, and the boost output voltage is kept stable and does not change any more. When the load current suddenly decreases (for example, the external load suddenly changes or is disconnected), the stored energy generated by the boost inductor driven by the original PWM duty ratio is far larger than the energy consumed by the load, the boost output voltage quickly rises, but the grid of the third MOS tube connected in parallel with the two ends of the rectifier diode is connected with the third capacitor, and the initial capacitor voltage is equivalent to the original boost output voltage. Because the capacitor voltage can not be suddenly changed, when the PWM pulse output by the CPU is at a high level, the first MOS tube is conducted, the drain electrode of the third MOS tube is conducted to the ground through the conducted second MOS tube and the first MOS tube, the third MOS tube is conducted because the source electrode (connected with the boosting output end) of the third MOS tube is higher than the grid electrode and the drain electrode voltage, the rectifier diode is short-circuited by the third MOS tube, and the capacitor energy storage of the boosting output end is shunted to the ground through the conducted third MOS tube, the second MOS tube and the first MOS tube to discharge the electric energy; when the boosted output voltage is reduced to a voltage value lower than (the third capacitor voltage + the minimum Vgs of the third MOS transistor), the third MOS transistor is automatically cut off, the boosted output voltage stops continuously reducing, and therefore the energy discharged to the ground through the third MOS transistor is limited; when the PWM pulse output by the CPU is in a low level, the first MOS tube is cut off, the energy stored by the boost inductor is charged to the boost output capacitor through the first diode, and the boost output voltage is increased. Due to the earth leakage discharge effect of the third MOS tube on the boosting output capacitor, the boosting output end loses the transient surge capability of voltage as a result of boosting and discharging.
Example two
Referring to fig. 2, a schematic circuit diagram of a boosting circuit of a CPU directly driving a MOS transistor in an embodiment of the present invention is shown. Wherein Vin is a power supply input end and a power supply end of the CPU, Vout is a boost output end, and L1 is a boost inductor.
The first capacitor C1 and the second capacitor C2 are filter capacitors of the power supply input terminal Vin, the first capacitor C1 is used for keeping the voltage of the power supply input terminal Vin stable, and the second capacitor C2 is used for avoiding EMC (electromagnetic compatibility) problems caused by pulse signals conducted to other lines. The power supply input terminal Vin should not be greater than the maximum operating voltage of the CPU.
The fourth capacitor C4 is a filter and storage capacitor for the boost output terminal Vout, and the fifth capacitor C5 is used to eliminate high frequency noise at the boost output terminal Vout. A PWM port of the CPU outputs PWM high-low level pulses with a certain duty ratio to drive a first MOS tube Q1 to work, and a boosting inductor L1 is electrified to store energy during the conduction period of a first MOS tube Q1; during the turn-off period of the first MOS transistor Q1, the stored energy of the boost inductor L1 becomes a self-induced high voltage pulse, which is rectified by the first diode D1 and filtered by the third capacitor C3 into a higher voltage dc current Vout for supplying power to the load.
The second MOS transistor Q2 is used for controlling the on-off of the boost output. Specifically, the first resistor R1 and the second resistor R2 are bias resistors of the first MOS transistor Q1 and the second MOS transistor Q2, respectively, so as to ensure that the first MOS transistor Q1 and the second MOS transistor Q2 are in a reliable off mode in the shutdown or standby state. The SW pin of the CPU is connected with the grid electrode of the second MOS tube Q2, when the SW pin of the CPU outputs low level, the second MOS tube Q2 is conducted due to the voltage difference between the source electrode and the grid electrode, and the boosting output circuit is switched on; when the SW pin of the CPU outputs a high level, the second MOS transistor Q2 is turned off by a voltage almost equal between the source and the gate, and the boost output circuit is turned off.
The third MOS transistor Q3 is connected in parallel with the first diode D1, and plays a role in suppressing the transient surge of the boost output voltage when the load current suddenly and sharply decreases. Specifically, the gate of the third MOS transistor Q3 is grounded through the third capacitor C3, the third capacitor C3 and the third resistor R3 form a series charging loop, so that after the boost output voltage is stabilized, the voltage across the third capacitor C3 approaches the boost output voltage Vout, and a reference voltage function is provided for subsequently suppressing surge of the boost output voltage Vout due to load change. When the load current suddenly decreases or disappears under the abnormal condition, the energy stored by the boosting inductor L1 driven by the original PWM duty ratio of the CPU is larger than the energy consumed by the load, and the value of the boosting output end Vout rapidly rises. Since the voltage across the third capacitor C3 connected to the gate of the third MOS transistor Q3 cannot suddenly change (initially stays at the original Vout level), when the voltage difference between the boosted output terminal Vout (i.e., the source of the third MOS transistor Q3) and the gate of the third MOS transistor Q3 is greater than the Vgs turn-on threshold of the third MOS transistor Q3, since the drain of the first MOS transistor Q1 is at the low level during the PWM high-level pulse turn-on period of the first MOS transistor Q1, and the drain of the third MOS transistor is conducted through the conducting second MOS transistor and the first MOS transistor, the third MOS transistor Q3 is conducted because its source (boosted output terminal) is higher than the gate and the drain voltage, the fourth capacitor C4 of the boosted output terminal Vout is discharged through the third MOS transistor Q3, the second MOS transistor Q2, the first MOS transistor Q1, but when the boosted output voltage falls below Vout (the voltage across the third capacitor C3 + the third MOS transistor Q3), and the voltage difference between the source of the third MOS transistor Q3583 is automatically turned off because the gate of the third MOS transistor Q3 is smaller than the gate of the first MOS transistor Q3, and the boosted output terminal Therefore, the voltage of the boost output terminal Vout will stop decreasing, so that the energy of the fourth capacitor C4 leaking to the ground through the third MOS transistor Q3 is limited, and the energy of the previous boost pulse generated by the first inductor L1 will not leak. When the PWM pulse output by the CPU is at a low level, the first MOS transistor Q1 is turned off, at this time, the boosted self-induced electromotive force voltage generated by the first inductor L1 is much higher than the boosted output voltage Vout, the third MOS transistor Q3 is turned off because the drain voltage is greater than the source voltage, the boosted pulse generated by the first inductor L1 is rectified by the first diode D1 and then charges the fourth capacitor C4, the boosted output terminal Vout continues to rise, when the load current sharply decreases or disappears, the original charge-discharge balance is broken, the boosted pulse energy of the first inductor L1 is greater than the leakage amount of the fourth capacitor C4 at the boosted output terminal to the ground through the third MOS transistor and the current consumed by the load, the boosted output terminal Vout continues to rise at a certain speed, the third capacitor C3 is charged through the third resistor R3, the voltage across the third capacitor C3 slowly rises, and therefore the threshold required for the fourth capacitor C4 at the boosted output terminal to leak to the ground through the third MOS transistor Q3 (i.e., the MOS transistor Q3 gradually rises the threshold of the third transistor Q3) gradually Thereby causing the boost output Vout to gradually rise. Due to the earth leakage discharge effect of the third MOS tube connected with the first diode D1 in parallel on the boost output fourth capacitor C4, the transient surge capacity of the boost output voltage Vout is restrained, the surge is changed into slow rise, and time is gained for the follow-up CPU to adjust the PWM duty ratio and quickly return the boost output voltage Vout to the original set value.
The fourth resistor R4, the fifth resistor R5 and the sixth capacitor C6 form a voltage detection loop of the boosting output end Vout. The voltage at the boost output terminal Vout is divided by the fourth resistor R4 and the fifth resistor R5, filtered by the sixth capacitor C6, and then sent to the a/D pin of the CPU for detection and digital filtering (averaging operation) to eliminate voltage detection misjudgment possibly caused by load noise signal interference. After the CPU finishes detecting the boosting output voltage Vout, the CPU compares the boosting output voltage Vout with a set value of the Vout. If Vout is larger than the set value, reducing a value of the current PWM duty ratio, detecting and comparing the difference value between the boosted output voltage Vout and the set value, if the difference value does not reach the set value, continuing to reduce the PWM duty ratio, and repeating the steps until the boosted output voltage Vout is adjusted to the set value. If Vout is less than the set point, the PWM duty cycle is gradually incremented until the Vout set point is reached. The CPU has extremely fast operation speed, so that the whole adjustment process of the set value of the boost output Vout can be realized within 0.5 second usually. When the load current suddenly decreases or disappears unexpectedly, on one hand, the hardware circuit firstly forcibly suppresses the instantaneous surge of the boost output voltage Vout, and on the other hand, the CPU rapidly completes the adjustment of the boost output voltage Vout by adjusting the PWM duty ratio, gradually approaches and finally reaches the set value of the Vout.
When the boost circuit starts to shift gears, because the load does not change instantaneously at this time, the CPU sets a change value according to the boost output Vout corresponding to each shift position, and increases or decreases the corresponding PWM duty ratio by the above method until Vout reaches a new set value. When the set value of the boosted output Vout needs to be increased, although the situation that the third MOS transistor Q3 is turned on to leak the fourth capacitor C4 to the ground when the boosted output Vout rises is larger than (the original voltage value of the third capacitor C3 + the minimum Vgs value of the third MOS transistor Q3), the energy of the fourth capacitor C4 leaking to the ground through the third MOS transistor Q3 will be limited because the third MOS transistor Q3 will be turned off to stop the leakage when the boosted output Vout falls below (the voltage across the third capacitor C3 + the minimum Vgs value of the third MOS transistor Q3). With the increasing of the PWM duty ratio of the CPU output, when the energy stored by the boost inductor L1 increases to exceed the leakage generated by the fourth capacitor C4 through the conduction of the third MOS transistor Q3 and the current consumed by the load, the boost output Vout will still gradually increase to the newly set voltage value, so the above-mentioned rectification and overshoot suppression circuit composed of the third resistor R3, the third capacitor C3, the first diode D1 and the third MOS transistor Q3 connected in parallel will not affect the gear-up of the boost output voltage Vout.
It should be noted here that, in the selection of the devices, the CPU needs to select a single chip with an a/D pin, a built-in a/D reference voltage source, and a PWM signal output, and the PWM maximum frequency is greater than 60KHz, so as to prevent the boost inductor L1 from generating audio oscillation noise, the PWM should have at least 8-bit resolution, so as to ensure that the boost output voltage Vout has a fine step adjustment value, and thus, the span of one-step voltage adjustment between each step is not too large, and the CPU can select a chip model such as MDT10F272 that meets the above requirements. The first MOS transistor Q1 should be an NMOS transistor with Vgs <2.5V, the withstand current should be more than 5 times the maximum load operating current, the withstand voltage should be more than 2 times the maximum boost output voltage, and for the application where the boost output voltage is not more than 15V and the boost output current is less than 1.5A, the model of AO3400(30V, 5.8A) packaged by SOT23 can be selected. The second MOS transistor Q2 and the third MOS transistor Q3 should be PMOS transistors, and their withstand current should be more than 3 times of the maximum load operating current, and the third MOS transistor should be a P-channel MOSFET with a turn-on threshold Vgs <1.4V, so as to control the instantaneous surge maximum of the boost output voltage within 1.8V. For the application that the boosted output voltage is not more than 12V and the boosted output current is less than 1.2A, SOT23 with Vgs less than or equal to 1.3V can be used for packaging AO3401(-30V, 4.2A) or NCE2305(-20V, 4.1A) with Vgs less than or equal to 1V. The withstand current of the boost inductor L1 should be 2 times or more the maximum load operating current, and the inductance thereof depends on the PWM frequency for driving the boost, and the higher the PWM frequency is, the smaller the required inductance is, which is more advantageous for reducing the external dimension of the boost inductor. For the boost drive, the PWM frequency of 110-130 KHz is adopted, and the boost inductor L1 recommends an I-shaped winding inductor or a patch power inductor with the inductance of 47 uH. The first resistor R1 and the second resistor R2 can be 10K-100K, and the third resistor R3 is used in cooperation with the third capacitor C3, for example, when the third capacitor C3 selects 1uF/50V, the third resistor R3 selects 47K-100K, but the selection values of the third capacitor C3 and the third resistor R3 cannot be too large, so that the transition time required for reaching the set value of the boost output voltage during shifting is not too long due to an excessively large charging time constant. The selection of the fourth resistor R4 and the fifth resistor R5 depends on the ratio of the maximum boosting output voltage to the CPU built-in A/D reference voltage value, generally from tens of kilohms to hundreds of kilohms, and the voltage of the A/D pin of the maximum boosting output voltage which is divided by the fourth resistor R4 and the fifth resistor R5 and sent to the CPU is lower than 4/5 of the CPU built-in A/D reference voltage value, so that overflow is not generated. Considering that the ripple of the boost circuit directly driven by the CPU is slightly larger than that of the dedicated boost chip, the sixth capacitor C6 for a/D sampling should be 1 uF/50V. The fourth capacitor C4 of the boost output end should be an electrolytic capacitor of 220 uF-470 uF, and the withstand voltage value should be more than 2-3 times of the maximum boost output voltage. The second capacitor C2 at the power supply input end and the fifth capacitor C5 at the boosting output end can be selected to be 100nF/50V for eliminating high-frequency noise. The value of the first capacitor C1 at the power supply input end is determined according to the magnitude of the boost output load current, and the value can be selected from 22 uF-100 uF/16V, so that the principle that the power supply voltage cannot generate large voltage fluctuation when the boost circuit works is ensured.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention. Furthermore, the embodiments of the present invention and the features of the embodiments may be combined with each other without conflict.
Claims (7)
1. A booster circuit of a CPU direct drive MOS tube is characterized by comprising a power supply input end, a booster inductor, a CPU, a first MOS tube, a rectification and overshoot suppression circuit and a booster output end, wherein the power supply input end is respectively connected with one end of the booster inductor and the input end of the CPU;
the rectification and overshoot suppression circuit comprises a third capacitor, a first diode and a third MOS tube which are connected in parallel, the boosting inductor is respectively connected with the anode of the first diode and the drain electrode of the third MOS tube, the cathode of the first diode and the source electrode of the third MOS tube are connected with the boosting output end, and the grid electrode of the third MOS tube is grounded through the third capacitor.
2. The booster circuit of claim 1, wherein a second MOS transistor is further connected between the boost inductor and the rectifying and overshoot suppression circuit, the SW pin of the CPU is connected to the gate of the second MOS transistor, the boost inductor is connected to the source of the second MOS transistor, and the drain of the second MOS transistor is connected to the anode of the first diode and the drain of the third MOS transistor, respectively.
3. The boost circuit of a CPU direct drive MOS transistor according to claim 2, wherein the rectification and overshoot suppression circuit further comprises a third resistor, one end of the third resistor is connected to one end of the third capacitor, and the other end of the third resistor is connected to the source of the third MOS transistor.
4. The boost circuit of a CPU direct drive MOS transistor according to claim 3, wherein the power supply input terminal includes a first capacitor and a second capacitor, an anode of the first capacitor is connected to one end of the boost inductor, a cathode of the first capacitor is grounded, one end of the second capacitor is connected to one end of the boost inductor, and another end of the second capacitor is grounded.
5. The boost circuit of a CPU direct-drive MOS transistor according to claim 4, wherein the boost output terminal includes a fourth capacitor and a fifth capacitor, an anode of the fourth capacitor is connected to the cathode of the first diode and the source of the third MOS transistor, respectively, a cathode of the fourth capacitor is grounded, one end of the fifth capacitor is connected to the cathode of the first diode and the source of the third MOS transistor, respectively, and the other end of the fifth capacitor is grounded.
6. The voltage boost circuit of a CPU direct drive MOS tube according to any one of claims 1 to 5, characterized in that, said voltage boost circuit further comprises a voltage detection circuit, the input end of said voltage detection circuit is connected with said boost output end, the output end of said voltage detection circuit is connected with A/D pin of said CPU.
7. The boost circuit of the MOS transistor directly driven by the CPU as claimed in claim 6, wherein the voltage detection circuit comprises a fourth resistor, a fifth resistor and a sixth capacitor, one end of the fourth resistor is connected to the boost output terminal, the other end of the fourth resistor is respectively connected to one end of the fifth resistor and the A/D pin of the CPU, the other end of the fifth resistor is grounded, and the A/D pin of the CPU is further grounded through the sixth capacitor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911176395.XA CN110798068A (en) | 2019-11-26 | 2019-11-26 | Boosting circuit of CPU direct drive MOS tube |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911176395.XA CN110798068A (en) | 2019-11-26 | 2019-11-26 | Boosting circuit of CPU direct drive MOS tube |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232240A (en) * | 2008-02-28 | 2008-07-30 | 北京创毅视讯科技有限公司 | Boosted circuit |
| US20150189716A1 (en) * | 2013-12-30 | 2015-07-02 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Led backlight driving circuit and liquid crystal device |
| CN205232536U (en) * | 2015-11-26 | 2016-05-11 | 四川长虹电器股份有限公司 | LED drive circuit's boost circuit |
| CN206379887U (en) * | 2017-01-12 | 2017-08-04 | 广东百事泰电子商务股份有限公司 | A kind of intelligent sine voltage change-over circuit based on metal-oxide-semiconductor full-bridge rectification |
| CN210780550U (en) * | 2019-11-26 | 2020-06-16 | 深圳飞安瑞科技股份有限公司 | Boosting circuit of CPU direct drive MOS tube |
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2019
- 2019-11-26 CN CN201911176395.XA patent/CN110798068A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232240A (en) * | 2008-02-28 | 2008-07-30 | 北京创毅视讯科技有限公司 | Boosted circuit |
| US20150189716A1 (en) * | 2013-12-30 | 2015-07-02 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Led backlight driving circuit and liquid crystal device |
| CN205232536U (en) * | 2015-11-26 | 2016-05-11 | 四川长虹电器股份有限公司 | LED drive circuit's boost circuit |
| CN206379887U (en) * | 2017-01-12 | 2017-08-04 | 广东百事泰电子商务股份有限公司 | A kind of intelligent sine voltage change-over circuit based on metal-oxide-semiconductor full-bridge rectification |
| CN210780550U (en) * | 2019-11-26 | 2020-06-16 | 深圳飞安瑞科技股份有限公司 | Boosting circuit of CPU direct drive MOS tube |
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