CN110797400A - Air-gap transistor structure and manufacturing method thereof - Google Patents
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
An air-gap transistor structure and a manufacturing method thereof are provided, the structure comprises a semiconductor substrate, an emitter, a first dielectric layer, a control electrode, an air gap, a second dielectric layer and a collector; the emitter comprises at least one emitter body and connecting parts on two sides of the emitter body, the emitter bodies are positioned on the upper surface of the semiconductor substrate, each emitter body is provided with at least one vertex angle with a preset curvature radius, and the connecting parts are connected with the emitter bodies and arranged around the structural space of the emitter bodies; the first dielectric layer is positioned on the upper surface of the connecting part and isolates the connecting part from the side wall of the emission main body structure space; the control electrode is positioned on the upper surface of the first dielectric layer and is isolated from the connecting part through the first dielectric layer; the air gap is positioned on the control electrode and surrounds the control electrode, and the projection position of the air gap is positioned in the projection position of the emission main body; the second dielectric layer covers the surface of the control electrode; the collector is positioned on the upper surfaces of the second dielectric layer and the air gap; and is isolated from the control electrode by a second dielectric layer.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to an air-gap transistor structure compatible with a Complementary Metal Oxide Semiconductor (CMOS) process and a manufacturing method thereof.
Background
With the continuous development of CMOS technology according to moore's law, scaling of the conventional MOS device encounters more and more technical and cost challenges, for example, how to improve channel carrier mobility, how to achieve a sufficiently large on-state current while voltage scaling, and the like, and technologies such as stress engineering and Fin-Field-effect transistor (FinFET for short) are introduced, and while the device is scaled down, performance of the device needs to be improved.
However, the use of these techniques increases process complexity, process control difficulties, and cost. In addition, the conventional CMOS device also has problems such as a change in device characteristics with temperature, an influence of external radiation on the device, and the like.
Therefore, how to satisfy the above market demands, how to greatly improve the carrier mobility thereof, and how to enhance the emission efficiency of emitter electrons have become an important consideration in the industry for the design of air gap transistor products.
Disclosure of Invention
The invention aims to provide an air-gap transistor structure and a manufacturing method thereof, and in order to achieve the aim, the technical scheme is as follows:
an air gap transistor structure, comprising:
a semiconductor substrate;
the emitter comprises at least one emitter body and connecting parts on two sides of the emitter body, wherein the emitter body is positioned on the upper surface of the semiconductor substrate, and each emitter body is provided with at least one vertex angle with a preset curvature radius; the connecting part is connected with the emitter body; the connecting part is arranged around the structural space of the emission main body; the emitter is made of metal materials, alloy materials and metal compound materials;
a first dielectric layer located on the upper surface and the side surface of the connecting part and isolating the connecting part from the side wall of the emission main body structure space;
a control electrode which is positioned on the upper surface of the first dielectric layer and is isolated from the connecting part through the first dielectric layer;
an air gap located above the emitter with its projected position within the projected position of the emitter body;
the second dielectric layer covers the surface of the control electrode;
the collector is positioned on the upper surfaces of the second medium layer and the air gap; and is isolated from the control electrode by the second dielectric layer; wherein field emission of electrons is achieved by controlling the voltage between the emitter and collector;
when the air gap transistor structure works, the emitter is connected with a negative potential, and the control electrode and the collector are connected with a positive potential; the current from the emitter to the collector is controlled by the control electrode, and the polarity and the magnitude of the voltage of the control electrode are utilized to play a role in enhancing or weakening the current of the collector.
Furthermore, the emission main body internally and locally comprises a tip, and the shape of the emission main body comprises a trapezoid, a rectangle embedded in two sides, a square with two concave sides or convex sides, a triangle, an irregular tip figure and a pointed arc.
Further, the control electrode has a grid-like structure above the emitter body, and the grid-like structure is used for enhancing the electron emission efficiency of the emitter after voltage is applied.
Further, the connecting portion arranged around the air gap is isolated by the first dielectric layer.
Furthermore, the second dielectric layer is provided with a first shielding metal groove, and the first shielding metal groove is isolated from the air gap through the second dielectric layer.
Further, a second shielding metal trench is arranged between the second dielectric layer and the air gap, surrounds the air gap, and is connected with the collector.
Furthermore, the shapes of the left side surface, the right side surface and the top of the air gap are planes, inclined planes, concave or convex circular arcs, convex circular arcs or the combination of the shapes.
Further, the metal height of the at least one emission body is lower than that of the connection portions at both sides thereof.
In order to achieve the above purpose, another technical solution is as follows:
a method for manufacturing an air gap transistor structure is characterized by comprising the following steps:
step S1: depositing an emitter material on a semiconductor substrate, and removing metal on the periphery of the emitter in a patterning mode to form an emitter region; the emitter is made of metal materials, alloy materials and metal compound materials;
step S2: patterning the emitter region to form at least one emitter body and connecting parts on two sides of the emitter body, wherein the height of the at least one emitter body is lower than that of the connecting parts on two sides, and each emitter body is provided with a vertex angle with at least one preset curvature radius; wherein the connection portion is connected with the emitter body, the connection portion being arranged around a structural space of the emitter body;
step S3: depositing a first dielectric layer material, removing the first dielectric layer material on the at least one emission body in a patterning mode, and reserving the first dielectric layer material on the side wall, close to the air gap, of the connecting part on the two sides of the emitter;
step S4: depositing a sacrificial layer, and then flattening, wherein the sacrificial layer only remains in the emitter region and is flush with the upper surface of the first dielectric layer in height;
step S5: depositing a control electrode layer, and forming a grid-shaped structure of the control electrode layer in a patterning mode; wherein the control electrode layer grid-like structure is positioned above the first medium isolation layer in the height direction;
step S6: depositing a second dielectric layer, then depositing a first shielding metal layer, and patterning the first shielding metal layer, wherein the first shielding metal in the air gap area above the emitter is completely removed;
step S7: continuously depositing a second dielectric layer and flattening;
step S8: etching to form grooves of a second shielding metal layer for absorbing secondary electrons on two sides of the device region; depositing collector metal, and only retaining the collector material in the groove through reverse etching or CMP;
step S9: etching to remove the second dielectric layer in the air gap area, depositing a sacrificial layer, enabling the sacrificial layer to be flush with the surface of the second dielectric layer through CMP, and exposing the collector material in the groove;
step S10: depositing a collector metal layer, so that the collector metal layer is connected with the collector metal in the groove and completely covers the air gap area;
step S11: and patterning the collector metal layer to form the collector.
Further, a top angle of the emission main body is subjected to BOSCH etching, wherein gas of the BOSCH etching is HCl and/or HBr metal etching gas.
According to the technical scheme, the air gap three-body tube structure compatible with the CMOS process is provided, and the three-end device of the emitter, the control electrode and the collector is realized by introducing the nano structure. The three-terminal device has the following beneficial effects:
①, field emission of electrons is realized by the voltage between the emitter and the collector, and the ballistic emission of electrons can be realized, so that the carrier mobility can be greatly improved;
②, the emission efficiency of the emitter electrons is further enhanced by controlling the voltage between the electrode and the emitter;
③, the three-terminal device structure is less affected by external influence (such as radiation, etc.), and provides a technical basis for the development of devices in the later CMOS era.
Drawings
FIG. 1 is a schematic diagram of an air-gap transistor structure according to an embodiment of the present invention
Detailed Description
The following describes the present invention in further detail with reference to fig. 1.
The invention provides an air gap 6 transistor structure, in particular to an air gap 6 transistor structure compatible with a CMOS (complementary metal oxide semiconductor) process and a manufacturing method thereof. The air gap 6 transistor structure is a nanoscale three-terminal device structure comprising an emitter 1, a control electrode 2 and a collector 3. The three-terminal device realizes field emission of electrons through the voltage between the emitter 1 and the collector 3, can realize ballistic emission of electrons, can greatly improve the carrier mobility of the three-terminal device, further enhances the emission efficiency of the electrons of the emitter 1 through the voltage between the control electrode 2 and the emitter 1, has small influence from external influence (such as radiation and the like), and provides a technical basis for the development of devices in the later CMOS era.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating an air gap 6 transistor structure according to an embodiment of the present invention. The air-gap 6 transistor structure is a novel device structure, and a high-performance three-terminal device can be realized by introducing the novel nanoscale device structure. The three-terminal device may include a semiconductor substrate, an air gap 6, an emitter 1, a first dielectric layer 4, a control electrode 2, and a collector 3.
As shown, the emitter 1 is located on a semiconductor substrate, and the emitter 1 may include one or more emitter bodies and a connection portion connected with the emitter bodies. The material of the emitter 1 is generally a metal material, an alloy material, a metal compound material, or the like. Each emission body has a vertex angle with at least one preset curvature radius. That is, the number of the transmitting bodies may be plural, and the number of the transmitting bodies may be plural. Furthermore, the emitters may be uniformly distributed on the semiconductor substrate, or may be distributed on the semiconductor substrate in a concentrated manner, which is not limited herein.
In the embodiment of the present invention, the top corner of the emission main body may be formed by etching (side etching) to have a tip structure having a smaller curvature radius, and the curvature radius of the tip structure may be smaller than 10 um.
The connection portions of the emitter 1 are usually arranged around the structural space of one or more emitter bodies; the first dielectric layer 4 is located on the upper surface and the side surface of the connection portion and isolates the connection portion from the sidewall of the structural space of the emission body. Preferably, the metal height of the one or more emission bodies is lower than that of the connection portions at both sides thereof. When the metal height of the emission main body is lower than the height of the metal of the connection part, a structure that the connection parts at the periphery are higher than the emission electrodes can be formed, at the moment, electrons emitted by the emission electrodes can have the probability of being emitted towards the peripheral direction, the connection parts at the periphery and the emission electrodes have the same potential, the repulsion effect can be achieved, the electrons are prevented from being incident on the metal or medium at the periphery of the air gap, and the emission and collection efficiency can be improved.
As shown in fig. 1, the control electrode 2 is located on the upper surface of the first dielectric layer 4 and is isolated from the connection portion by the first dielectric layer 4; an air gap 6 is positioned above the control electrode 2, and the projection position of the air gap is positioned in the projection position of the emission main body; the second dielectric layer 8 covers the surface of the control electrode 2; the collector 3 is positioned on the upper surfaces of the second medium layer 8 and the air gap 6; and is isolated from the control electrode 2 by a second dielectric layer 8; wherein, field emission of electrons is realized by controlling the voltage between the emitter 1 and the collector 3, and ballistic emission of electrons can be realized, so that the carrier mobility can be greatly improved.
In the embodiment of the present invention, the shapes of the left and right side surfaces and the top of the air gap 6 may be a plane, an inclined surface, an inward or outward convex circular arc, a convex circular arc or a combination of the above shapes, and may also be other irregular shapes or a combination of the above shapes (as shown in the figure).
When the three-terminal device works, the emitter 1 is connected with a negative potential, and the control electrode 2 and the collector 3 are connected with a positive potential; because the control electrode 2 is closer to the emitter, when the positive potential of the control electrode 2 is increased, the field emission efficiency of the emitter is enhanced, the current of the collector 3 is increased, and vice versa; the control electrode 2 is similar to the grid electrode of the MOS transistor, and can effectively control the conducting current. The electron emission efficiency of the emitter 1 is further enhanced by controlling the voltage between the electrode 2 and the emitter. I.e. the positive potential of the control stage increases, the field emission efficiency of the emitter stage increases in proportion to the collector current.
Referring again to fig. 1, above the emitter body of the emitter 1 and within the air gap 6 cavity, the control electrode 2 may be present in a grid-like structure 21, whose projected position is located between the emitter 1 structure spaces and whose pattern is sufficiently small. The grid-like structure 21 is like a sieve with holes on the sidewall of the air gap 6, and after applying voltage, the control electrode 2 portion of the grid-like structure 21 is used to ensure that electrons can smoothly pass through and reach the collector 3, which enhances the electron emission efficiency of the emitter 1.
In the embodiment of the present invention, the connection portion of the emitter 1, which is disposed around the structural space of the emitter 1, is isolated by the first dielectric layer 4. Since the emitter 1 is generally connected with a negative voltage, the electrostatic effect can prevent field emission electrons from hitting the first dielectric at the edge, which can strengthen the negative electric field and effectively prevent the further adsorption of the electrons.
Further, a first shielding metal trench 7 may be disposed in the second dielectric layer 8, and the first shielding metal trench 7 is isolated from the emitter 1 structural space by the second dielectric layer 8. The first shield metal trench 7 here is slightly below the emitter 1 voltage, effectively shielding the parasitic capacitance between the collector 3 and the control electrode.
And a second shielding metal trench 5 may be further included between the second dielectric layer 8 and the air gap 6, and the second shielding metal trench 5 surrounds the air gap 6. The second shielding metal trench 5 is connected to the collector 3 for generating secondary electrons after the electrons bombard the collector 3, and the secondary electrons can be absorbed by the second shielding metal trench 5. Meanwhile, since the distance between the metal and the control electrode 2 is small, the parasitic capacitance may be large, and thus a small area is provided. Preferably, the second shielding metal is the same metal as the collector 3.
The method for manufacturing the air gap transistor structure of the present invention is briefly described below.
A method for manufacturing an air gap transistor structure comprises the following steps:
step S1: depositing emitter 1 metal on a semiconductor substrate, and removing the metal on the periphery of the emitter 1 in a patterning mode to form an emitter 1 area; the emitter 1 can be made of metal materials, alloy materials or metal compound materials;
step S2: patterning an emitter 1 region to form at least one emitter body and connecting parts on two sides of the emitter body, wherein the metal height of the at least one emitter body is lower than that of the connecting parts on two sides, and each emitter body is provided with at least one vertex angle with a preset curvature radius; wherein the connecting part is connected with the emitter body, and the connecting part is arranged around the structural space of the emitter body;
step S3: depositing a first dielectric layer 4 material, removing the first dielectric layer 4 material on the at least one emitter body in a patterning mode, and keeping the first dielectric layer 4 material of the metal of the connecting parts at two sides on the side wall of the emitter 1 region;
step S4: depositing a sacrificial layer, and then flattening, wherein the sacrificial layer is only remained in the region of the emitter 1, and the height of the sacrificial layer is flush with the upper surface of the first dielectric layer 4;
step S5: depositing a control electrode layer, and forming a grid-shaped structure 21 of the control electrode layer in a patterning mode; wherein the control electrode layer grid-like structure 21 is located on the first dielectric isolation layer in the height direction;
step S6: depositing a second dielectric layer 8, then depositing a first shielding metal layer, and patterning the first shielding metal layer, wherein the first shielding metal in the air gap area above the emitter 1 is completely removed;
step S7: continuing to deposit a second dielectric layer 8 and flattening by CMP;
step S8: etching to form grooves of a second shielding metal layer for absorbing secondary electrons on two sides of the device region; depositing a collector material, and only retaining the collector material in the groove through reverse etching or CMP;
step S9: etching to remove the second dielectric layer 8 in the air gap 6 area, depositing a sacrificial layer, and enabling the surface of the sacrificial layer to be flush with the surface of the second dielectric layer 8 through CMP, and exposing the collector metal in the groove;
step S10: depositing a collector metal layer, so that the collector metal layer is connected with the collector metal in the groove and completely covers the air gap 6 area;
step S11: and patterning the collector metal layer to form a collector.
In an embodiment of the present invention, a top angle of the emitting body is etched using a BOSCH etch gas, wherein the BOSCH etch gas is a HCl and/or HBr metal etch gas.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. An air-gap transistor structure, comprising:
a semiconductor substrate;
the emitter comprises at least one emitter body and connecting parts on two sides of the emitter body, wherein the emitter body is positioned on the upper surface of the semiconductor substrate, each emitter body is provided with at least one vertex angle with a preset curvature radius, and the connecting parts are connected with the emitter body; the connecting part is arranged around the structural space of the transmitting body; wherein the material of the emitter comprises a metal material, an alloy material and a metal compound material;
a first dielectric layer located on the upper surface and the side surface of the connecting part and isolating the connecting part from the side wall of the emission main body structure space;
a control electrode which is positioned on the upper surface of the first dielectric layer and is isolated from the connecting part through the first dielectric layer;
an air gap located above the emitter with its projected position within the projected position of the emitter body;
the second dielectric layer covers the surface of the control electrode;
the collector is positioned on the upper surfaces of the second dielectric layer and the air gap and is isolated from the control electrode through the second dielectric layer; wherein field emission of electrons is achieved by controlling the voltage between the emitter and collector;
when the air gap transistor structure works, the emitter is connected with a negative potential, and the control electrode and the collector are connected with a positive potential; the current from the emitter to the collector is controlled by the control electrode, and the polarity and the magnitude of the voltage of the control electrode are utilized to play a role in enhancing or weakening the current of the collector.
2. The air gap transistor structure of claim 1 wherein the emitter body includes a tip locally therein, and the shape of the emitter body includes a trapezoid, a rectangle with concave or convex sides, a square with concave or convex sides, a triangle, an irregular tip pattern, and a peaked circular arc.
3. The air gap transistor structure of claim 1, wherein the control electrode presents a grid-like structure above the emitter body, the grid-like structure serving to enhance electron emission efficiency of the emitter upon application of a voltage.
4. The air gap transistor structure of claim 1, wherein the connection portion disposed around the air gap is isolated by the first dielectric layer.
5. The air gap transistor structure of claim 1 wherein the second dielectric layer has a first shield metal trench therein, the first shield metal trench being isolated from the air gap by the second dielectric layer.
6. The air gap transistor structure of claim 4, comprising a second shield metal trench between the second dielectric layer and the air gap, the second shield metal trench surrounding the air gap and connected to the collector.
7. The air gap transistor structure of claim 1, wherein the shapes of the left and right sides and the top of the air gap comprise a plane, a bevel, an inward or outward convex arc, a convex arc, or a combination thereof.
8. The air gap transistor structure of claim 1, characterized in that the height of the at least one emitter body is lower than the height of its two side connections.
9. A method for manufacturing an air gap transistor structure is characterized by comprising the following steps:
step S1: depositing an emitter material layer on a semiconductor substrate, and removing metal on the periphery of an emitter in a patterning mode to form an emitter region; wherein the material of the emitter comprises a metal material, an alloy material and a metal compound material;
step S2: patterning the emitter material layer to form at least one emitter body and connecting parts on two sides of the emitter body, wherein the height of the at least one emitter body is lower than that of the connecting parts on two sides, each emitter body is provided with a vertex angle with at least one preset curvature radius, the connecting parts are connected with the emitter body, and the connecting parts are arranged around the structural space of the emitter body;
step S3: depositing a first dielectric layer, removing the first dielectric layer on the at least one emission main body in a patterning mode, and reserving the first dielectric layer on the side wall of the two side connecting parts of the emitter close to the air gap;
step S4: depositing a sacrificial layer, and then flattening, wherein the sacrificial layer only remains in the emitter region and is flush with the upper surface of the first dielectric layer in height;
step S5: depositing a control electrode material layer, and imaging to form a control electrode grid structure; wherein the control electrode grid structure is positioned above the first dielectric isolation layer in the height direction;
step S6: depositing a second dielectric layer, then depositing a first shielding metal layer, and imaging the first shielding metal layer, wherein the first shielding metal in the air gap area above the emitter is completely removed;
step S7: continuously depositing a second dielectric layer and flattening;
step S8: etching the second dielectric layer on two sides of the device region to form a groove of a second shielding metal layer for absorbing secondary electrons; depositing a collector material, and only retaining the collector material in the groove through reverse etching or CMP;
step S9: etching to remove the second dielectric layer in the air gap area, depositing a sacrificial layer, enabling the sacrificial layer to be flush with the surface of the second dielectric layer through CMP, and exposing the collector material in the groove;
step S10: depositing a collector metal layer, so that the collector metal layer is connected with the collector metal in the groove and completely covers the air gap area;
step S11: and patterning the collector metal layer to form the collector.
10. The method of claim 9, wherein a top corner of the emitter body is BOSCH etched, wherein the BOSCH etching gas is a HCl and/or HBr metal etching gas.
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| CN112103157A (en) * | 2020-08-25 | 2020-12-18 | 中国科学院上海微系统与信息技术研究所 | Planar air channel transistor and preparation method thereof |
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| CN112103157B (en) * | 2020-08-25 | 2021-11-19 | 中国科学院上海微系统与信息技术研究所 | Planar air channel transistor and preparation method thereof |
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