CN110796256A - Quantum chip structure and preparation method - Google Patents
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Abstract
The invention discloses a quantum chip structure and a preparation method thereof, wherein the quantum chip structure comprises the following steps: a first plane comprising a first set of contacts; a second plane comprising a second set of contacts; a plurality of connectors positioned to hold the first and second planes opposite such that the first and second sets of contacts are opposite, each connector having a first end connected to the first set of contacts and a second end connected to the second set of contacts; a qubit module comprising a plurality of qubits arranged on the first plane or the second plane, each qubit having a first coupling end and a second coupling end; the quantum bus is configured on the first plane or the second plane and is positioned on a different plane from the quantum bit module, and the quantum bus is coupled to the first coupling end through a connecting piece; the reading bus is configured on the first plane or the second plane and is coupled to the second coupling end.
Description
Technical Field
The invention belongs to the technical field of quantum chips, and particularly relates to a quantum chip structure and a preparation method thereof.
Background
The Quantum computation is to encode logic information on two Quantum states which can be mutually converted, namely Quantum bit (qubit), construct a highly complex Quantum central processing unit (Quantum CPU), namely a Quantum chip, by using a Quantum bit system, realize controllable programming operation on the information stored in the complex Quantum states, namely a Quantum logic gate and a Quantum algorithm, and finally realize the leading edge science of the Quantum information processing process. The computing power and computing speed potential of quantum computers is much higher than the sum of all classical computers in the world today in solving some specific problems, such as prime factor decomposition.
The quantum chip is generally integrated with a plurality of quantum bits and a measurement and control circuit for operating the quantum bits, each quantum bit is coupled with different measurement and control circuits respectively by utilizing a cross-shaped capacitance structure of the quantum bit to realize signal transmission and interaction, the construction of the quantum chip containing one to two quantum bits is easier to realize at present, and the realization and demonstration of a small number of quantum bits are realized in a plurality of physical systems. But in quantum computers the number of qubits used may be hundreds, tens of thousands, or even hundreds of millions. When a plurality of qubits are processed on the same quantum chip, no matter whether the plurality of qubits are configured by adopting one-dimensional links or two-dimensional arrays, measurement and control lines respectively coupled with each quantum bit are more or less crossed and interfered with each other on a plane, and the design difficulty is self-evident.
Disclosure of Invention
The invention aims to provide a quantum chip structure and a preparation method thereof, which are used for solving the defects in the prior art and can provide the quantum chip structure capable of avoiding cross among interconnection wiring.
The technical scheme adopted by the invention is as follows:
a quantum chip structure, comprising:
a first plane comprising a first set of contacts;
a second plane comprising a second set of contacts;
a plurality of connectors positioned to hold the first and second planes opposite such that the first and second sets of contacts are opposite, each of the connectors having a first end connected to the first set of contacts and having a second end connected to the second set of contacts;
a qubit module comprising a plurality of qubits configured on the first plane or the second plane, each of the qubits having a first coupling end and a second coupling end;
a quantum bus disposed on the first plane or the second plane and located on a different plane than the qubit module, the quantum bus coupled to a first coupling end of the qubit via the connection;
a read bus disposed on the first plane or the second plane, the read bus coupled to a second coupling end of the qubit.
Further, the first set of contacts and the second set of contacts are both aluminum pads.
Further, a first group of grooves are formed in the first plane, and the first group of contact pieces are arranged in the first group of grooves; and a second group of grooves are formed in the second plane, and the second group of contact pieces are arranged in the second group of grooves.
Further, the first plane and the second plane each include a substrate made of a silicon material.
Further, a plurality of the connectors extend vertically between the first set of contacts and the second set of contacts.
Further, the connecting piece is made of superconducting materials.
Further, the connecting piece is an indium column or a silver column.
Further, the read bus and the qubit module are configured on the same plane.
Further, the read bus and the quantum bus are configured on the same plane;
the read bus is coupled to the second coupling terminal of the qubit via the connection.
Further, the read bus comprises resonators with the same number as the qubits and a read signal bus coupled to the same end of all the resonators, and the other ends of all the resonators are coupled to the second coupling end of each qubit respectively.
A preparation method for preparing a quantum chip structure comprises the following steps:
providing the first plane comprising the first set of contacts and the second plane comprising the second set of contacts;
providing a plurality of said connectors;
configuring the qubit module on the first plane or the second plane;
configuring the quantum bus on the first plane or the second plane, wherein: the quantum bus and the qubit module are located on different planes;
configuring the read bus on the first plane or the second plane;
the first plane and the second plane are oppositely arranged, the connecting piece is arranged between the first plane and the second plane, and the first end part of the connecting piece is connected with the first group of contact pieces, and the second end part of the connecting piece is connected with the second group of contact pieces.
Compared with the prior art, the invention provides a quantum chip structure, which comprises: a first plane comprising a first set of contacts; a second plane comprising a second set of contacts; a plurality of connectors positioned to hold the first and second planes opposite such that the first and second sets of contacts are opposite, each of the connectors having a first end connected to the first set of contacts and having a second end connected to the second set of contacts; a qubit module comprising a plurality of qubits configured on the first plane or the second plane, each of the qubits having a first coupling end and a second coupling end; a quantum bus disposed on the first plane or the second plane and located on a different plane than the qubit, the quantum bus coupled to a first coupling end of the qubit via the connection; the invention sets the quantum bit module and the quantum bus on two different planes respectively, and then couples and connects the two in the opposite direction along the first plane and the second plane through the connecting piece, because the quantum bit module and the quantum bus are respectively positioned on different board layers, the quantum bit module can carry out two-dimensional array in the same board layer when wiring is set, so that the wiring of the quantum bit module and the quantum bus, the quantum bit module and the read bus can realize non-crossing through design on the premise of providing stable control signals and read signals for the quantum bit module and ensuring the close coupling of the quantum bits, thereby weakening the signal interference problem caused by wiring, providing a basis for later increasing the number of qubits on a quantum chip.
Drawings
FIG. 1 is a schematic diagram of a prior art two-dimensional array arrangement of 6 qubits;
FIG. 2 is a schematic diagram of a quantum chip structure according to an embodiment of the present invention;
FIG. 3 is a schematic view of the first planar structure of FIG. 2;
FIG. 4 is a schematic view of the second planar structure of FIG. 2;
fig. 5 is a schematic structural diagram of a quantum chip according to another embodiment of the present invention;
FIG. 6 is a schematic perspective view of the quantum chip structure of FIG. 5;
FIG. 7 is a schematic view of the first planar structure of FIG. 5;
FIG. 8 is a schematic view of the second planar structure of FIG. 5;
fig. 9 is a second planar configuration of fig. 5.
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
Quantum computation is a gate that encodes logic information on two Quantum states that can be transformed into each other, namely Quantum bit, a highly complex Quantum central processing unit (Quantum CPU), namely a Quantum chip, is constructed by using a Quantum bit system, and controllable programming operation, namely a Quantum logic gate and a Quantum algorithm, of the information stored in the complex Quantum states is realized by using the Quantum chip, so that the leading edge science of the Quantum information processing process is finally realized.
Quantum computing can exert far more computing power than classical computers in specific fields, for example, a large 100-bit number is decomposed by large prime factorization based on the RSA encryption principle, and if all the classical computers around the world are used, the result can be obtained by operating for billions of years, but if a quantum computer with 50-bit quantum bits is used, the computing result can be obtained in a few minutes, so that quantum computing is now the focus of research in various countries.
In the field of quantum computing, a quantum chip is a core structure, the type of the quantum chip has various forms according to the formation mode of a qubit (or qubit), such as common superconducting qubits, semiconductor qubits, ion well qubits and the like, the superconducting qubits are constructed by using parallel josephson junctions and capacitors based on circuit quantum electrodynamics, and a resonator is constructed by using a coplanar waveguide.
Because quantum computation depends on high coherence among quantum bits, controllable quantum computation only involves a small number of quantum bits, and the number of quantum bits is small, the structure and circuit of a quantum chip are easy to design, that is, the quantum bits arranged in a one-dimensional link, a required reading circuit and a required control circuit can be arranged on one plane, but internationally known, in order to realize the real capability of quantum computation, the number of the quantum bits needs at least 50, and when the number of the quantum bits is increased, the difficulty of configuring the quantum bits, the control circuit and the reading circuit on one plane is increased sharply, because the arrangement of the quantum bits usually adopts a one-dimensional link or a two-dimensional array, the design is facilitated by adopting a one-dimensional link method under the condition that the number of the quantum bits is small, but once the number is increased, the length and the size of the quantum chip in a certain direction are not controllable, in order to input necessary control signals, reading signals and adjacent coupling among qubits, a control line and a reading line connected with the qubits are necessarily crossed, specifically, as shown in fig. 1, the control line and the reading line are a 6-bit quantum chip, 6 qubits are two-dimensionally arrayed in a manner of 2 rows and 3 columns, as can be seen from the figure, under the condition of only arranging one control signal feeder line, a cross region is generated by the connection lead of the control signal feeder line and the resonant cavity and the adjacent coupling among the qubits, and the crossing means that interference is generated during signal transmission, so that the coherence is greatly reduced, therefore, the design requirements of a large number of qubits cannot be met by adopting a one-dimensional link or a two-dimensional array, and a technology called Air-bridge (Air-bridge) is generally adopted when the signal line is crossed in the field of circuit design at present, but the actual effect is very slight.
Accordingly, embodiments of the present invention provide a quantum chip structure, as shown in fig. 2-4, including: a first plane 100 comprising a first set of contacts 110; a second plane 200 comprising a second set of contacts 210; a plurality of connectors 300 positioned to hold the first plane 100 and the second plane 200 opposite such that the first set of contacts 110 and the second set of contacts 210 are opposite, each of the connectors 300 having a first end 310 connected to the first set of contacts 110 and having a second end 320 connected to the second set of contacts 210; qubit module 400 comprising a plurality of qubits 410 arranged in the first plane 100 or the second plane 200, each of the qubits 410 having a first coupling end 411 and a second coupling end 412; a quantum bus 500 disposed on the first plane 100 or the second plane 200 and located on a different plane from the qubit module 400, the quantum bus 500 being coupled to a first coupling terminal 411 of the qubit 410 via the connection 300; a read bus 600 disposed on the first plane 100 or the second plane 200, the read bus 500 coupled to the second coupling end 412 of the qubit 410.
Compared with the prior art, the invention provides a quantum chip structure, which comprises: a first plane 100 comprising a first set of contacts 110; a second plane 200 comprising a second set of contacts 210; a plurality of connectors 300 positioned to hold the first plane 100 and the second plane 200 opposite such that the first set of contacts 110 and the second set of contacts 210 are opposite, each of the connectors 300 having a first end 310 connected to the first set of contacts 110 and having a second end 320 connected to the second set of contacts 210; qubit module 400 comprising a plurality of qubits 410 arranged in the first plane 100 or the second plane 200, each of the qubits 410 having a first coupling end 411 and a second coupling end 412; a quantum bus 500 disposed on the first plane 100 or the second plane 200 and located on a different plane from the qubit module 400, the quantum bus 500 being coupled to a first coupling terminal 411 of the qubit 410 via the connection 300; the invention sets the qubit module 400 and the qubit bus 500 on two different planes respectively, and then couples and connects them in the opposite direction along the first plane 100 and the second plane 200 through the connection piece 300, because the qubit module 400 and the qubit bus 500 are located on different board layers respectively, when wiring is set, the qubit module 400 can perform two-dimensional array in the same board layer, so that the wiring of the qubit module 400 and the qubit bus 500, the qubit module 400 and the readout bus 600 can be designed to be non-crossed on the premise of providing stable control signals and readout signals for the qubit module and ensuring the qubit close coupling, therefore, the signal interference problem caused by wiring is reduced, and a basis is provided for increasing the number of quantum bits on a quantum chip later.
It should be noted that quantum bus 500 includes various interconnection wires for coupling with qubits 410 and providing various control signals. The read bus 600 at least comprises a resonator 610 and a read signal bus 620, the resonator 610 is used for interacting with the signals in the qubits, the read signal bus 620 is used for inputting the read signal and outputting the read signal according to the effect in the resonator 610, and in the embodiment 1, the qubits in the same row can be closely coupled through the connecting element 300 and the connecting lead between the connecting elements 300.
Furthermore, the resonator 610 is a coplanar waveguide microwave resonant cavity made of coplanar waveguide microstrip lines, and the quantum bus 500 is made of coplanar waveguide microstrip lines, it should be noted that, in the microwave field, a coplanar waveguide microstrip line is three parallel metal thin film conductive tape layers prepared on the surface of a dielectric layer, wherein the conductive tape layer located at the center is used for transmitting microwave signals, and the conductive tape layers at both sides are connected to a ground plane, the largest difference with a general circuit is that a coplanar waveguide is a distributed circuit element, and capacitance/inductance/reactance/impedance of the distributed circuit element are uniformly distributed along the propagation direction of coplanar waveguide signals, the coplanar waveguide propagates TEM waves, along the propagation direction of signals, the impedance of the waveguide is equal at all positions, so there is no signal reflection, and signals can pass through almost without loss; in addition, coplanar waveguides have no cutoff frequency, while common lumped circuits have cutoff frequencies. For a section of uniform coplanar waveguide, most microwave signals in the frequency band can be transmitted smoothly, and the section of uniform coplanar waveguide is called a transmission line, namely a coplanar waveguide transmission line (microstrip line).
As shown in fig. 2, a specific quantum chip structure is shown, in which: the qubit module 400 is arranged on a first plane 100, the quantum bus 500 is arranged on a second plane 200, a first end 310 of the plurality of connections 300 is connected with the first set of contacts 110 on the first plane 100, and a second end 320 is connected with the second set of contacts 210 on the second plane 200, such that the quantum bus 500 on the second plane 200 can be coupled to a first coupling end 411 of the qubit 410 via the connections 300; the read bus 600 is also disposed on the second plane 200, and similarly, in order to couple the read bus 600 and the second coupling end 412 of the qubit 410, a connection 300 may still be provided and implemented via the connection 300.
It should be noted that, in order to better arrange the first set of contacts 110, the second set of contacts 210, and the connector 300, a first set of grooves and a second set of grooves may be respectively arranged on the first plane 100 and the second plane 200, and the first set of contacts 110 may be arranged in the first set of grooves of the first plane 100, the second set of contacts 210 may be arranged in the second set of grooves of the second plane 200, and fixed, and the first set of grooves and the second set of grooves may be respectively configured to have the same size as the first end portion 310 and the second end portion 320 of the connector 300, so that the first end portion 310 and the second end portion 320 of the connector 300 may well form a clearance fit with the first set of grooves and the second set of grooves, respectively, thereby achieving a stable connection.
Further, the first plane 100 and the second plane 200 are both substrates made of silicon materials, the first plane 100 and the second plane 200 with stable signal transmission can be made by using the stability of the silicon element structure, meanwhile, the first group of contacts 110 and the second group of contacts 210 are both aluminum pads, and the connector 300 adopts indium columns or silver columns made of superconducting materials such as indium or silver, so that lossless signal transmission is performed by using the superconductivity of the indium columns or silver columns at low temperature, and the design requirements of the quantum chip are met.
It should be noted that, because the structure of the qubit 410 is small, in order to enable the qubit 410 to be coupled with different structures, respectively, it is common knowledge of those skilled in the art that the end portion for coupling on the qubit 410 can be extended to other positions by using the necessary connection lead 800, such as a coplanar waveguide transmission line, and this embodiment 1 is also shown in fig. 3.
In order to verify that the quantum chip structure of this embodiment can implement multi-qubit wiring and not generate cross-interference, in this embodiment 1, 4 qubits are designed on the first plane 100 and arranged in a two-dimensional array, as shown in fig. 2, the first coupling end 411 of the 4 qubits 410 can be coupled to the quantum bus 500 through the first set of contacts 110 and the second set of contacts 210 on the second plane 200 via the connection 300, the second coupling end 412 of the 4 qubits 410 can be led to the same side through a lead wire first and continue to be coupled with the read bus 600 on the second plane 200 through the connection 300, wherein it should be noted that currently, the close proximity coupling between the qubits on the integrated quantum chip and the coupling between the control feed line and the qubits are mostly coupled through a coplanar microwave cavity and are coupled through a coplanar waveguide microwave cavity, are spatially separated. Qubits 310 in the same row may be coupled in close proximity via a qubit bus between the second set of contacts 210 to which they are respectively coupled, as in the illustrated design, with no crossover between qubit module 400 and connection lines of qubit bus 500 and read bus 600, provided that control signal input, read signal input, and close-proximity coupling of qubits 410 are ensured.
Because of the vulnerability of qubits, which makes it difficult to read information of qubits, a coupler connected to the qubit is usually used to read information of the qubit, and in the present invention, the coupler is a coplanar waveguide microwave resonator, and in order to more accurately obtain information in the qubit, the distance between the coupler and the qubit is preferably close enough to avoid decoherence caused by too far space, so that the present invention further provides another embodiment, as shown in fig. 5 to 8, which is different from the previous embodiments in that the read bus 600 is disposed on the first plane 100 so as to be located on the same plane as the qubit module 400, and the read bus 600 is disposed very close to the second coupling end 412 of the qubit 410, so as to improve the stability of reading of the qubit signal.
Specifically, the read bus 600 includes resonators 610 whose number is the same as the number of the qubits 410, and a read signal bus 620 coupled to all the resonators 610 at the same end, and the other ends of all the resonators 610 are coupled to the second coupling end 412 of each qubit 410, respectively, and the read bus 600 and the qubit module 400 are disposed on the same surface, so that the distance between the resonators 610 for reading qubit information and the qubits 410 is closer, and no additional connecting lead 800 is required, thereby improving the read stability, and the read bus 600 and the qubit bus 500 are disposed on different board layers, and since both include multiple kinds of wirings, the difficulty of wiring can be further reduced by separately disposing the two.
It should be noted that, for a single qubit 410, the quantum bus 500 may need to provide more than 1 control input, for example, two control signal inputs may be needed for implementing xy regulation and z regulation on the single qubit, as shown in fig. 9, another second plane 200 with different wiring structure is shown, and for the single contact 210, the first signal lead 810 and the second signal lead 820 are further included, so that for the single qubit 410, an additional control signal input is provided, and from the view of illustration, all wirings do not generate a cross phenomenon, and thus, it is further confirmed that the quantum chip structure of the present invention can implement wiring of multiple qubits and does not generate cross interference. Wherein, it is required to be noted that: the xy regulation and the z regulation refer to that for the regulation of a single quantum bit, the initial state of the single quantum bit can be abstracted to be a pointer with a starting point positioned at the center of a sphere and an end point positioned at the sphere on a Bloch sphere, and the operation can be decomposed into the xy regulation and the z regulation, wherein the regulation of the state of the single quantum bit is the position of the starting point which is kept still and the end point of the pointer which is moved on the sphere.
Further, the invention also provides a preparation method of the quantum chip structure, which comprises the following steps:
providing the first plane 100 comprising the first set of contacts 110 and the second plane 200 comprising the second set of contacts 210;
providing a plurality of said connectors 300;
configuring the qubit module 300 on the first plane 100 or the second plane 200;
configuring the quantum bus 500 on the first plane 100 or the second plane 200, wherein: the quantum bus 500 is located on a different plane than the qubit module 300;
configuring the read bus 600 on the first plane 100 or the second plane 200;
the first plane 100 and the second plane 200 are oppositely arranged, the connector 300 is arranged between the first plane 100 and the second plane 200, and the first end 310 of the connector 300 is connected with the first group of contacts 110 and the second end 320 is connected with the second group of contacts 210.
The quantum chip structure in the foregoing embodiment can be conveniently manufactured by the above steps, because the qubit module 400 and the quantum bus 500 are respectively disposed on two different planes, and then coupled and connected in the opposite direction along the two planes through the connection member 300, because the qubit module 400 and the quantum bus 500 are respectively disposed on different board layers, when wiring is disposed, the qubit module 400 can perform a two-dimensional array in the same board layer, and the wiring of the qubit module 400 and the quantum bus 500 can be designed to be non-crossed, thereby reducing the signal interference problem caused by wiring
A specific quantum chip structure fabrication step is provided as follows:
step 1, providing the first plane 100 comprising the first set of contacts 110 and the second plane 200 comprising the second set of contacts 210; wherein, the first plane 100 and the second plane 200 are both substrates made of silicon material;
it should be noted that the connection member 300 may be not only a provided entity, but also an indium column that may be manufactured through a growth process;
step 3, configuring the qubit module 300 in the first plane 100;
step 4, configuring the quantum bus 500 on the second plane 200;
step 5, configuring the read bus 600 on the first plane 100 or the second plane 200; specifically, the read bus 600 may be configured on the first plane 100 as in the second embodiment, see fig. 4;
and 6, arranging the first plane 100 and the second plane 200 oppositely, arranging the connecting piece 300 between the first plane 100 and the second plane 200, and connecting the first end part 310 of the connecting piece 300 with the first group of contacts 110 and connecting the second end part 320 with the second group of contacts 210.
The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.
Claims (11)
1. A quantum chip structure, comprising:
a first plane (100) comprising a first set of contacts (110);
a second plane (200) comprising a second set of contacts (210);
a plurality of connectors (300) positioned to hold the first plane (100) and the second plane (200) opposite such that the first set of contacts (110) and the second set of contacts (210) are opposite, each of the connectors (300) having a first end (310) connected to the first set of contacts (110) and having a second end (320) connected to the second set of contacts (210);
a qubit module (400) comprising a plurality of qubits (410) configured on the first plane (100) or the second plane (200), each qubit (410) having a first coupling end (411) and a second coupling end (412);
a quantum bus (500) disposed on the first plane (100) or the second plane (200) and located on a different plane than the qubit module (400), the quantum bus (500) coupled to a first coupling terminal (412) of the qubit (410) via the connection (300);
a read bus (600) configured on the first plane (100) or the second plane (200), the read bus (600) being coupled to a second coupling terminal (412) of the qubit (410).
2. The quantum chip structure of claim 1, wherein the first set of contacts (110) and the second set of contacts (210) are each aluminum pads.
3. The quantum chip structure of claim 1, wherein a first set of recesses are provided in the first plane (100), the first set of contacts (110) being disposed in the first set of recesses; and a second group of grooves are arranged on the second plane (200), and the second group of contact pieces (210) are arranged in the second group of grooves.
4. The quantum chip structure of claim 1, wherein the first plane (100) and the second plane (200) each comprise a substrate made of silicon material.
5. The quantum chip structure of claim 1, wherein a plurality of the connections (300) extend vertically between the first set of contacts (110) and the second set of contacts (210).
6. The quantum chip structure of claim 1, wherein the connection (300) is made of a superconducting material.
7. The quantum chip structure of claim 6, wherein the connection (300) is an indium or silver pillar.
8. The quantum chip structure of claim 1, wherein the read bus (600) and the qubit module (400) are configured on the same plane.
9. The quantum chip structure of claim 1, wherein the read bus (600) and the quantum bus (500) are configured on the same plane;
the read bus (600) is coupled to the second coupling terminal (412) of the qubit (410) via the connection (300).
10. The quantum chip structure of claim 1, wherein the read bus (600) comprises a number of resonators (610) corresponding to the number of qubits (410) and a read signal bus (620) coupled to all the resonators at a same end, the other ends of all the resonators (610) being respectively coupled to the second coupling end (412) of each of the qubits (410).
11. A method of making a quantum chip structure according to any of claims 1 to 10, comprising the steps of:
-providing the first plane (100) comprising the first set of contacts (110) and the second plane (200) comprising the second set of contacts (210);
-providing a plurality of said connectors (300);
configuring the qubit module (400) on the first plane (100) or the second plane (200);
configuring the quantum bus (500) on the first plane (100) or the second plane (200), wherein: the quantum bus (500) is located on a different plane than the qubit module (400);
-configuring the read bus (600) on the first plane (100) or the second plane (200);
-providing the first plane (100) and the second plane (200) opposite each other, -providing the connector (300) between the first plane (100) and the second plane (200), and-providing the first end (310) of the connector (300) in connection with the first set of contacts (110) and the second end (320) in connection with the second set of contacts (210).
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| CN115271081A (en) * | 2022-08-17 | 2022-11-01 | 合肥本源量子计算科技有限责任公司 | Control circuit, layout structure and flip chip |
| CN116187461A (en) * | 2023-02-16 | 2023-05-30 | 合肥本源量子计算科技有限责任公司 | Bit structure, quantum chip, manufacturing method of quantum chip and quantum computer |
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