CN110788029A - Method and device for testing chip - Google Patents
Method and device for testing chip Download PDFInfo
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- CN110788029A CN110788029A CN201911150434.9A CN201911150434A CN110788029A CN 110788029 A CN110788029 A CN 110788029A CN 201911150434 A CN201911150434 A CN 201911150434A CN 110788029 A CN110788029 A CN 110788029A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/34—Sorting according to other particular properties
- B07C5/344—Sorting according to other particular properties according to electric or electromagnetic properties
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
- G01R31/287—Procedures; Software aspects
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Abstract
The invention provides a method and a device for testing a chip, wherein the method comprises the following steps: determining a plurality of sample chips from a plurality of chips to be tested; determining the value of the current performance index of each sample chip; determining the average value and standard deviation of the current performance index values of a plurality of sample chips, and generating the test range of the current performance index, wherein the test range is (mu)1‑3σ1，μ1+3σ1)，μ1Is the mean value, σ1Is the standard deviation; for each non-sample chip, performing: determining the value of the current performance index of the current non-sample chip, judging whether the value of the current performance index of the current non-sample chip is in the test range of the current performance index, if so, determining that the current performance index of the current non-sample chip is qualified, otherwise, determining that the current performance index of the current non-sample chip is unqualified; the chips other than the sample chip among the plurality of chips are non-sample chips. The inventionThe method and the device for testing the chips are provided, and the consistency of qualified chips can be improved.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a method and a device for testing a chip.
Background
The chips need to be tested before leaving the factory, and unqualified chips can be eliminated.
In the prior art, the testing of the chip is performed by compiling a test program, manipulating the test resources of an automatic tester, screening and characterizing the functions and characteristics of the chip to be tested, and verifying the production quality and the design performance. On a chip test production line, various performance indexes of the chips can be tested in batches, and the purpose is to screen the chips which meet the requirements better. A screening range is empirically set for each performance indicator, and chips within the screening range are left behind. These screening ranges can only roughly distinguish between defective and non-defective chips in the chips produced in the same batch, where the difference in the same performance index between different non-defective chips is also large, and the consistency of the chips of these non-defective chips is poor.
Disclosure of Invention
The embodiment of the invention provides a method and a device for testing chips, which can improve the consistency of qualified chips.
In a first aspect, an embodiment of the present invention provides a method for testing a chip, including:
determining a plurality of sample chips from a plurality of chips to be tested;
determining a value of a current performance index of each sample chip;
determining the average value and the standard deviation of the current performance index values of the plurality of sample chips according to the current performance index value of each sample chip;
generating a test range of the current performance index according to the average value and the standard deviation of the value of the current performance index, wherein the test range of the current performance index is (mu)1-3σ1，μ1+3σ1)，μ1Is the average, σ, of the values of the current performance indicator1Is the standard deviation of the value of the current performance indicator;
for each non-sample chip of the plurality of chips, performing: determining the value of the current performance index of the current non-sample chip, judging whether the value of the current performance index of the current non-sample chip is in the test range of the current performance index, if so, determining that the current performance index of the current non-sample chip is qualified, otherwise, determining that the current performance index of the current non-sample chip is unqualified;
wherein a chip of the plurality of chips that is not the sample chip is the non-sample chip.
Alternatively,
after the determining a plurality of sample chips from the plurality of chips to be tested, further comprising:
determining that the current performance metric for each of the sample chips is acceptable.
In a second aspect, an embodiment of the present invention provides a method for testing a chip, including:
s0: n individual performance indexes are predetermined and are divided into key indexes and non-key indexes, wherein n is a positive integer;
s1: taking a plurality of chips to be tested as chips to be tested of the 1 st individual performance index;
s2: i is 1, i is a positive integer;
s3: determining the value of the ith individual performance index of each chip to be tested of the ith individual performance index;
s4: determining a plurality of sample chips of the ith individual performance index and at least one chip to be screened from the chips to be tested of the ith individual performance index;
s5: determining the average value and the standard deviation of the ith individual performance index value of the sample chip of the ith individual performance index according to the ith individual performance index value of each sample chip of the ith individual performance index;
s6: generating a test range of the ith individual performance index according to the average value and the standard deviation of the value of the ith individual performance index, wherein the test range of the ith individual performance index is (mu)2-3σ2，μ2+3σ2)，μ2Is the average value, σ, of the values of the ith individual performance indicator2Is the standard deviation of the value of the ith individual performance indicator;
s7: for each chip to be screened, performing: judging whether the value of the ith individual performance index of the current chip to be screened is in the test range of the ith individual performance index, if so, determining that the ith individual performance index of the current chip to be screened is qualified, otherwise, determining that the ith individual performance index of the current chip to be screened is unqualified;
s8: whether i is equal to n, if not, S9 is executed;
s9: and judging whether the ith individual performance index is a key index, if so, taking the chip to be tested, of which the ith individual performance index is qualified, as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, otherwise, taking the chip to be tested of the ith individual performance index as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, wherein i is i + 1.
Alternatively,
the method of testing a chip further comprises:
setting an initial range for each performance index;
the method for determining a plurality of sample chips of the ith individual performance indexes and at least one chip to be screened from the chips to be tested of the ith individual performance indexes comprises the following steps:
aiming at each chip to be tested of the ith individual performance index, executing the following steps: judging whether the value of the ith individual performance index of the current chip to be tested is within the initial range of the ith individual performance index, and if so, determining that the current chip to be tested passes the primary screening;
determining a plurality of sample chips of the ith individual performance indexes from the chips to be tested of the ith individual performance indexes which pass the primary screening, and taking the chips which are not the sample chips in the chips to be tested of the ith individual performance indexes which pass the primary screening as the chips to be screened;
further comprising:
and when the ith individual performance index value of the current chip to be tested is judged not to be in the initial range of the ith individual performance index, determining that the ith individual performance index of the current chip to be tested is unqualified.
Alternatively,
after the determining a plurality of sample chips of the ith performance index and at least one chip to be screened from the chips to be tested of the ith performance index, the method further comprises the following steps:
determining that the ith performance indicator of each sample chip of the ith performance indicator is qualified.
In a third aspect, an embodiment of the present invention provides an apparatus for testing a chip, including:
a sample determination unit for determining a plurality of sample chips from a plurality of chips to be tested;
the index determining unit is used for determining the value of the current performance index of each sample chip;
the statistical unit is used for determining the average value and the standard deviation of the current performance index values of the plurality of sample chips according to the current performance index value of each sample chip;
a range determination unit, configured to generate a test range of the current performance indicator according to a mean value and a standard deviation of the value of the current performance indicator, where the test range of the current performance indicator is (μ:)1-3σ1，μ1+3σ1)，μ1Is the average, σ, of the values of the current performance indicator1Is the standard deviation of the value of the current performance indicator;
a non-sample screening unit for performing, for each non-sample chip of the plurality of chips: determining the value of the current performance index of the current non-sample chip, judging whether the value of the current performance index of the current non-sample chip is in the test range of the current performance index, if so, determining that the current performance index of the current non-sample chip is qualified, otherwise, determining that the current performance index of the current non-sample chip is unqualified;
wherein a chip of the plurality of chips that is not the sample chip is the non-sample chip.
Alternatively,
the apparatus for testing a chip further comprises:
a sample screening unit for determining that the current performance index of each of the sample chips is qualified.
In a fourth aspect, an embodiment of the present invention provides an apparatus for testing a chip, including:
the device comprises a first storage unit, a second storage unit and a third storage unit, wherein the first storage unit is used for storing n individual performance indexes, and the n individual performance indexes are divided into key indexes and non-key indexes;
a test unit to perform:
s1: taking a plurality of chips to be tested as chips to be tested of the 1 st individual performance index, wherein n is a positive integer;
s2: i is 1, i is a positive integer;
s3: determining the value of the ith individual performance index of each chip to be tested of the ith individual performance index;
s4: determining a plurality of sample chips of the ith individual performance index and at least one chip to be screened from the chips to be tested of the ith individual performance index;
s5: determining the average value and the standard deviation of the ith individual performance index value of the sample chip of the ith individual performance index according to the ith individual performance index value of each sample chip of the ith individual performance index;
s6: generating a test range of the ith individual performance index according to the average value and the standard deviation of the value of the ith individual performance index, wherein the test range of the ith individual performance index is (mu)2-3σ2，μ2+3σ2)，μ2Is the average value, σ, of the values of the ith individual performance indicator2Is the standard deviation of the value of the ith individual performance indicator;
s7: for each chip to be screened, performing: judging whether the value of the ith individual performance index of the current chip to be screened is in the test range of the ith individual performance index, if so, determining that the ith individual performance index of the current chip to be screened is qualified, otherwise, determining that the ith individual performance index of the current chip to be screened is unqualified;
s8: whether i is equal to n, if not, S9 is executed;
s9: and judging whether the ith individual performance index is a key index, if so, taking the chip to be tested, of which the ith individual performance index is qualified, as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, otherwise, taking the chip to be tested of the ith individual performance index as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, wherein i is i + 1.
Alternatively,
the apparatus for testing a chip further comprises: the second storage unit is used for storing an initial range corresponding to each performance index;
the test unit, when executing the sample chip and the at least one chip to be screened that determine a plurality of ith performance indexes from the chips to be tested of the ith performance index, is specifically configured to:
aiming at each chip to be tested of the ith individual performance index, executing the following steps: judging whether the value of the ith individual performance index of the current chip to be tested is within the initial range of the ith individual performance index, and if so, determining that the current chip to be tested passes the primary screening;
determining a plurality of sample chips of the ith individual performance indexes from the chips to be tested of the ith individual performance indexes which pass the primary screening, and taking the chips which are not the sample chips in the chips to be tested of the ith individual performance indexes which pass the primary screening as the chips to be screened;
the test unit is further configured to:
and when the ith individual performance index value of the current chip to be tested is judged not to be in the initial range of the ith individual performance index, determining that the ith individual performance index of the current chip to be tested is unqualified.
Alternatively,
the testing unit is further used for determining that the ith performance index of each sample chip of the ith performance index is qualified.
In the embodiment of the invention, the average value and the standard deviation of the value of the current performance index are determined based on the sample chip in the plurality of chips to be tested, and the testing range of the current performance index is determined to be (mu) based on the average value and the standard deviation of the value of the current performance index1-3σ1，μ1+3σ1) Only the chips with the current performance indexes within the test range are qualified, the current performance indexes of the qualified chips can be limited within a smaller range through the test range, the current performance indexes of the qualified chips are relatively close, and the consistency of the qualified chips is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a method for testing a chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of another method for testing a chip according to an embodiment of the invention;
FIG. 3 is a flow chart of yet another method for testing a chip according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an apparatus for testing a chip according to an embodiment of the present invention;
fig. 5 is a schematic diagram of another apparatus for testing a chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a method for testing a chip, including:
step 101: determining a plurality of sample chips from a plurality of chips to be tested;
step 102: determining a value of a current performance index of each sample chip;
step 103: determining the average value and the standard deviation of the current performance index values of the plurality of sample chips according to the current performance index value of each sample chip;
step 104: generating a test range of the current performance index according to the average value and the standard deviation of the value of the current performance index,wherein the test range of the current performance index is (mu)1-3σ1，μ1+3σ1)，μ1Is the average, σ, of the values of the current performance indicator1Is the standard deviation of the value of the current performance indicator;
step 105: for each non-sample chip of the plurality of chips, performing: determining the value of the current performance index of the current non-sample chip, judging whether the value of the current performance index of the current non-sample chip is in the test range of the current performance index, if so, determining that the current performance index of the current non-sample chip is qualified, otherwise, determining that the current performance index of the current non-sample chip is unqualified;
wherein a chip of the plurality of chips that is not the sample chip is the non-sample chip.
In the embodiment of the invention, the average value and the standard deviation of the value of the current performance index are determined based on the sample chip in the plurality of chips to be tested, and the testing range of the current performance index is determined to be (mu) based on the average value and the standard deviation of the value of the current performance index1-3σ1，μ1+3σ1) Only the chips with the current performance indexes within the test range are qualified, the current performance indexes of the qualified chips can be limited within a smaller range through the test range, the current performance indexes of the qualified chips are relatively close, and the consistency of the qualified chips is improved.
In the embodiment of the invention, the chip can be a radio frequency power amplifier chip or other chips.
When determining the plurality of sample chips, the determination may be performed according to a preset ratio, for example: the preset ratio is 20%, and then, from all chips to be tested, 20% of the chips are randomly extracted as sample chips.
The current performance indicators may include: saturation power, steady state operating voltage, steady state operating current, gain, etc.
The plurality of chips to be tested are divided into sample chips and non-sample chips, and the rest are non-sample chips except for the chips determined as the sample chips.
The plurality of chips in the embodiment of the invention may be chips of the same batch. (mu.) a1-3σ1，μ1+3σ1) Is a very small range, since the test range is determined by the value of the performance index of the sample chip, the test range is closer to the value of the performance index of the batch of chips, and is more suitable for the batch of chips.
In an embodiment of the present invention, after determining a plurality of sample chips from a plurality of chips to be tested, the method further includes:
determining that the current performance metric for each of the sample chips is acceptable.
Since the test range is determined based on the average and standard deviation of the values of the current performance index of the sample chips, the probability that the value of the current performance index of each sample chip is within the test range is as high as 99.7%, and in order to reduce the workload of the test, it may be determined that the current performance index of each sample chip is qualified.
It can be seen that, in the plurality of chips to be tested, the current performance index of each sample chip is qualified, and the non-sample chips with the current performance index values within the test range are also qualified.
As shown in fig. 2, an embodiment of the present invention provides a method for testing a chip, including:
s0: n individual performance indexes are predetermined and are divided into key indexes and non-key indexes, wherein n is a positive integer;
s1: taking a plurality of chips to be tested as chips to be tested of the 1 st individual performance index;
s2: i is 1, i is a positive integer;
s3: determining the value of the ith individual performance index of each chip to be tested of the ith individual performance index;
s4: determining a plurality of sample chips of the ith individual performance index and at least one chip to be screened from the chips to be tested of the ith individual performance index;
s5: determining the average value and the standard deviation of the ith individual performance index value of the sample chip of the ith individual performance index according to the ith individual performance index value of each sample chip of the ith individual performance index;
s6: generating a test range of the ith individual performance index according to the average value and the standard deviation of the value of the ith individual performance index, wherein the test range of the ith individual performance index is (mu)2-3σ2，μ2+3σ2)，μ2Is the average value, σ, of the values of the ith individual performance indicator2Is the standard deviation of the value of the ith individual performance indicator;
s7: for each chip to be screened, performing: judging whether the value of the ith individual performance index of the current chip to be screened is in the test range of the ith individual performance index, if so, determining that the ith individual performance index of the current chip to be screened is qualified, otherwise, determining that the ith individual performance index of the current chip to be screened is unqualified;
s8: whether i is equal to n, if not, S9 is executed;
s9: and judging whether the ith individual performance index is a key index, if so, taking the chip to be tested, of which the ith individual performance index is qualified, as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, otherwise, taking the chip to be tested of the ith individual performance index as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, wherein i is i + 1.
A chip may need to pass multiple performance level tests, and for each performance level, the value of the performance level of the qualified chip needs to be in (mu)2-3σ2，μ2+3σ2) In the test range of (2), namely, the values of all the performance indexes are relatively close among all the chips with qualified performance indexes, so that the consistency of the qualified chips is improved.
In addition, in the embodiment of the present invention, the performance index is divided into a key index and a non-key index. The n performance indexes of the plurality of chips are tested in sequence, and a production line can be formed in the testing process. And after each key index test is finished, eliminating chips with unqualified key indexes, not carrying out subsequent tests, and reserving chips with qualified key indexes for subsequent tests. After each non-key index test is completed, the chips with qualified non-key indexes are reserved for subsequent tests, the chips with unqualified non-key indexes are also reserved for subsequent tests, but the non-key indexes of the chips are marked to be unqualified. After all performance indexes are tested, all chips marked with unqualified performance indexes can be eliminated, namely, as long as one performance index of the chip is unqualified, the chip can be eliminated, and finally, only the chips with all the qualified performance indexes are reserved.
In the embodiment of the invention, for a performance index, if the performance index of a chip is unqualified, the unqualified chip may affect the normal use of the test equipment in the test process, even damage the test equipment, and then the performance index is divided into key indexes; if the performance index of the chip is unqualified, the unqualified chip in the test process cannot influence the normal use of the test equipment, and the test equipment is not damaged, the performance index is divided into non-key indexes.
For example, for the performance index of open/short circuit, if the performance index of the chip is not qualified, it indicates that the chip is not operated well during packaging, which may cause damage to the test fixture, so the performance index of open/short circuit is divided into key indexes. For the performance index of the saturation power, whether the saturation power of the chip is qualified or not does not affect the normal use of the testing equipment, and the performance index of the saturation power is divided into non-key indexes.
In the embodiment of the invention, in order to avoid causing the fault of the test equipment, the chip with the unqualified key index is not subjected to subsequent test, and in order to obtain some index parameters of the chip with the unqualified non-key index, the chip with the unqualified non-key index can also be subjected to subsequent test.
In the embodiment of the invention, the chip to be tested of the ith performance index is a chip which needs to test the ith performance index. Because a part of chips may be eliminated after testing the key indexes of the chips, the chips to be tested with different performance indexes may be different.
In the embodiment of the invention, the chip to be screened of the ith performance index refers to a test range (mu) needing to pass through the ith performance index2-3σ2，μ2+3σ2) The tested chip of (1).
In the embodiment of the invention, if i is equal to n, the last performance index is tested, and the current process is ended.
In an embodiment of the present invention, the method for testing a chip further includes:
setting an initial range for each performance index;
the method for determining a plurality of sample chips of the ith individual performance indexes and at least one chip to be screened from the chips to be tested of the ith individual performance indexes comprises the following steps:
aiming at each chip to be tested of the ith individual performance index, executing the following steps: judging whether the value of the ith individual performance index of the current chip to be tested is within the initial range of the ith individual performance index, and if so, determining that the current chip to be tested passes the primary screening;
determining a plurality of sample chips of the ith individual performance indexes from the chips to be tested of the ith individual performance indexes which pass through the primary screening, and taking the chips which are not the sample chips in the chips to be tested of the ith individual performance indexes which pass through the primary screening as the chips to be screened.
Further comprising:
and when the ith individual performance index value of the current chip to be tested is judged not to be in the initial range of the ith individual performance index, determining that the ith individual performance index of the current chip to be tested is unqualified.
In the embodiment of the invention, each performance index is tested through a preset initial range before passing through the test range, and if the value of the performance index of the chip is not in the corresponding initial range, the chip is marked as unqualified. The sample chip and the chip to be screened which needs to pass the test range for secondary screening are both from the chip to be screened which passes the primary screening.
That is to say, a plurality of chips to be tested need to pass twice screening for each performance index, firstly pass the test of the initial range of the performance index, and then pass the test of the test range of the performance index, so that the qualified chips screened out are better in quality and more stable in performance.
For example, the performance indicator is saturation power, the initial range of saturation power is (45dB, 50 dB); the performance index is a steady-state operating voltage, and the initial range of the steady-state operating voltage is (-10v, 5 v); the performance indicator is the steady state operating current, which is initially in the range of (50mA, 300 mA).
In an embodiment of the present invention, after determining a plurality of sample chips of the ith performance index and at least one chip to be screened from the chips to be tested of the ith performance index, the method further includes:
determining that the ith performance indicator of each sample chip of the ith performance indicator is qualified.
Since the test range of the ith performance index is determined based on the average value and the standard deviation of the values of the ith performance index of the sample chip, the probability that the value of the ith performance index of each sample chip is within the test range is as high as 99.7%, and in order to reduce the workload of the test, the ith performance index of each sample chip can be determined to be qualified.
It can be seen that, in the plurality of chips to be tested, the ith performance index of each sample chip is qualified, and the non-sample chips with the value of the ith performance index within the test range are also qualified.
As shown in fig. 3, the method for testing a chip according to the embodiment of the present invention is described in detail below by taking a performance index of saturation power as an example:
step 301: an initial range is set for the saturation power, which is (45dB, 50 dB).
Step 302: and determining the value of the saturation power of each chip to be tested of the saturation power.
For example, there may be 1000 chips to be tested with saturation power, and the saturation power value of the 1000 chips to be tested is determined.
Step 303: for each chip to be tested with saturated power, executing the following steps: judging whether the current saturation power value of the chip to be tested is in the initial range of the saturation power, if so, determining that the current chip to be tested passes the primary screening, otherwise, determining that the current saturation power of the chip to be tested is unqualified.
Specifically, whether the saturation power value of the current chip to be tested is (45dB, 50dB) or not is determined, if yes, the initial screening is passed, and otherwise, the saturation power of the current chip to be tested is determined to be unqualified.
Step 304: determining a plurality of sample chips of the saturation power from the chips to be tested of the saturation power which passes the primary screening, and taking the chips which are not the sample chips in the chips to be tested of the saturation power which passes the primary screening as the chips to be screened.
Specifically, it is assumed that there are 800 chips that pass the primary screening, 200 chips are randomly selected from the 800 chips as sample chips, and then 600 chips remaining after removing the 200 sample chips from the 800 chips are chips to be screened.
Step 305: and determining the average value and the standard deviation of the saturated power values of the sample chips of the saturated power according to the saturated power value of each sample chip of the saturated power.
Specifically, the average value of the values of the saturation power of the sample chips for which the saturation power was determined was 48dB, and the standard deviation was 1.5 dB.
Step 306: generating a test range of the saturation power according to the average value and the standard deviation of the value of the saturation power, wherein the test range of the saturation power is (mu)2-3σ2，μ2+3σ2)，μ2Is the average, σ, of the values of the ith individual Performance indicator2Is the standard deviation of the value of the ith performance indicator.
In particular, based on μ2Is 48dB, sigma2At 1.5dB, the test range for saturation power was determined to be (46.5dB, 49.5 dB).
Step 307: for each chip to be screened, performing: judging whether the current saturation power value of the chip to be screened is in the saturation power test range, if so, determining that the current saturation power of the chip to be screened is qualified, otherwise, determining that the current saturation power of the chip to be screened is unqualified.
Specifically, 600 chips to be screened of the saturation power are tested by using the test range.
Step 308: the saturation power of each sample chip for which the saturation power is determined is qualified.
Specifically, 200 sample chips of the saturation power were all determined to be eligible.
As shown in fig. 4, an embodiment of the present invention provides an apparatus for testing a chip, including:
a sample determination unit 401 for determining a plurality of sample chips from a plurality of chips to be tested;
an index determining unit 402, configured to determine a value of a current performance index of each sample chip;
a statistical unit 403, configured to determine an average value and a standard deviation of the values of the current performance indexes of the multiple sample chips according to the value of the current performance index of each sample chip;
a range determining unit 404, configured to generate a test range of the current performance indicator according to a mean value and a standard deviation of the value of the current performance indicator, where the test range of the current performance indicator is (μ:)1-3σ1，μ1+3σ1)，μ1Is the average, σ, of the values of the current performance indicator1Is the standard deviation of the value of the current performance indicator;
a non-sample screening unit 405 configured to, for each non-sample chip of the plurality of chips, perform: determining the value of the current performance index of the current non-sample chip, judging whether the value of the current performance index of the current non-sample chip is in the test range of the current performance index, if so, determining that the current performance index of the current non-sample chip is qualified, otherwise, determining that the current performance index of the current non-sample chip is unqualified;
wherein a chip of the plurality of chips that is not the sample chip is the non-sample chip.
In an embodiment of the present invention, the apparatus for testing a chip further includes:
a sample screening unit for determining that the current performance index of each of the sample chips is qualified.
As shown in fig. 5, an embodiment of the present invention provides an apparatus for testing a chip, including:
the first saving unit 501 is configured to save n performance indicators, where the n performance indicators are divided into a key indicator and a non-key indicator;
a test unit 502 for performing:
s1: taking a plurality of chips to be tested as chips to be tested of the 1 st individual performance index, wherein n is a positive integer;
s2: i is 1, i is a positive integer;
s3: determining the value of the ith individual performance index of each chip to be tested of the ith individual performance index;
s4: determining a plurality of sample chips of the ith individual performance index and at least one chip to be screened from the chips to be tested of the ith individual performance index;
s5: determining the average value and the standard deviation of the ith individual performance index value of the sample chip of the ith individual performance index according to the ith individual performance index value of each sample chip of the ith individual performance index;
s6: generating a test range of the ith individual performance index according to the average value and the standard deviation of the value of the ith individual performance index, wherein the test range of the ith individual performance index is (mu)2-3σ2，μ2+3σ2)，μ2Is the average value, σ, of the values of the ith individual performance indicator2Is the standard deviation of the value of the ith individual performance indicator;
s7: for each chip to be screened, performing: judging whether the value of the ith individual performance index of the current chip to be screened is in the test range of the ith individual performance index, if so, determining that the ith individual performance index of the current chip to be screened is qualified, otherwise, determining that the ith individual performance index of the current chip to be screened is unqualified;
s8: whether i is equal to n, if not, S9 is executed;
s9: and judging whether the ith individual performance index is a key index, if so, taking the chip to be tested, of which the ith individual performance index is qualified, as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, otherwise, taking the chip to be tested of the ith individual performance index as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, wherein i is i + 1.
In an embodiment of the present invention, the apparatus for testing a chip further includes: the second storage unit is used for storing an initial range corresponding to each performance index;
the test unit, when executing the sample chip and the at least one chip to be screened that determine a plurality of ith performance indexes from the chips to be tested of the ith performance index, is specifically configured to:
aiming at each chip to be tested of the ith individual performance index, executing the following steps: judging whether the value of the ith individual performance index of the current chip to be tested is within the initial range of the ith individual performance index, and if so, determining that the current chip to be tested passes the primary screening;
determining a plurality of sample chips of the ith individual performance indexes from the chips to be tested of the ith individual performance indexes which pass the primary screening, and taking the chips which are not the sample chips in the chips to be tested of the ith individual performance indexes which pass the primary screening as the chips to be screened;
the test unit is further configured to:
and when the ith individual performance index value of the current chip to be tested is judged not to be in the initial range of the ith individual performance index, determining that the ith individual performance index of the current chip to be tested is unqualified.
In an embodiment of the invention, the testing unit is further configured to determine that the ith performance indicator of each sample chip of the ith performance indicator is qualified.
It is to be understood that the illustrated structure of the embodiments of the present invention does not constitute a specific limitation on the apparatus for testing a chip. In other embodiments of the invention, the means for testing the chip may include more or fewer components than shown, or some components may be combined, some components may be separated, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
Because the information interaction, execution process, and other contents between the units in the device are based on the same concept as the method embodiment of the present invention, specific contents may refer to the description in the method embodiment of the present invention, and are not described herein again.
The present invention also provides a computer readable medium storing instructions for causing a computer to perform a method of testing a chip as described herein. Specifically, a system or an apparatus equipped with a storage medium on which software program codes that realize the functions of any of the above-described embodiments are stored may be provided, and a computer (or a CPU or MPU) of the system or the apparatus is caused to read out and execute the program codes stored in the storage medium.
In this case, the program code itself read from the storage medium can realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.
Examples of the storage medium for supplying the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (e.g., CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW), a magnetic tape, a nonvolatile memory card, and a ROM. Alternatively, the program code may be downloaded from a server computer via a communications network.
Further, it should be clear that the functions of any one of the above-described embodiments may be implemented not only by executing the program code read out by the computer, but also by causing an operating system or the like operating on the computer to perform a part or all of the actual operations based on instructions of the program code.
Further, it is to be understood that the program code read out from the storage medium is written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion unit connected to the computer, and then causes a CPU or the like mounted on the expansion board or the expansion unit to perform part or all of the actual operations based on instructions of the program code, thereby realizing the functions of any of the above-described embodiments.
It should be noted that not all steps and modules in the above flows and system structure diagrams are necessary, and some steps or modules may be omitted according to actual needs. The execution order of the steps is not fixed and can be adjusted as required. The system structure described in the above embodiments may be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by a plurality of physical entities, or some components in a plurality of independent devices may be implemented together.
In the above embodiments, the hardware unit may be implemented mechanically or electrically. For example, a hardware element may comprise permanently dedicated circuitry or logic (such as a dedicated processor, FPGA or ASIC) to perform the corresponding operations. The hardware elements may also comprise programmable logic or circuitry, such as a general purpose processor or other programmable processor, that may be temporarily configured by software to perform the corresponding operations. The specific implementation (mechanical, or dedicated permanent, or temporarily set) may be determined based on cost and time considerations.
While the invention has been shown and described in detail in the drawings and in the preferred embodiments, it is not intended to limit the invention to the embodiments disclosed, and it will be apparent to those skilled in the art that various combinations of the code auditing means in the various embodiments described above may be used to obtain further embodiments of the invention, which are also within the scope of the invention.
Claims (10)
1. A method of testing a chip, comprising:
determining a plurality of sample chips from a plurality of chips to be tested;
determining a value of a current performance index of each sample chip;
determining the average value and the standard deviation of the current performance index values of the plurality of sample chips according to the current performance index value of each sample chip;
generating a test range of the current performance index according to the average value and the standard deviation of the value of the current performance index, wherein the test range of the current performance index is (mu)1-3σ1，μ1+3σ1)，μ1Is the average, σ, of the values of the current performance indicator1Is the standard deviation of the value of the current performance indicator;
for each non-sample chip of the plurality of chips, performing: determining the value of the current performance index of the current non-sample chip, judging whether the value of the current performance index of the current non-sample chip is in the test range of the current performance index, if so, determining that the current performance index of the current non-sample chip is qualified, otherwise, determining that the current performance index of the current non-sample chip is unqualified;
wherein a chip of the plurality of chips that is not the sample chip is the non-sample chip.
2. The method of testing a chip according to claim 1,
after the determining a plurality of sample chips from the plurality of chips to be tested, further comprising:
determining that the current performance metric for each of the sample chips is acceptable.
3. A method of testing a chip, comprising:
s0: n individual performance indexes are predetermined and are divided into key indexes and non-key indexes, wherein n is a positive integer;
s1: taking a plurality of chips to be tested as chips to be tested of the 1 st individual performance index;
s2: i is 1, i is a positive integer;
s3: determining the value of the ith individual performance index of each chip to be tested of the ith individual performance index;
s4: determining a plurality of sample chips of the ith individual performance index and at least one chip to be screened from the chips to be tested of the ith individual performance index;
s5: determining the average value and the standard deviation of the ith individual performance index value of the sample chip of the ith individual performance index according to the ith individual performance index value of each sample chip of the ith individual performance index;
s6: generating a test range of the ith individual performance index according to the average value and the standard deviation of the value of the ith individual performance index, wherein the test range of the ith individual performance index is (mu)2-3σ2，μ2+3σ2)，μ2Is the average value, σ, of the values of the ith individual performance indicator2Is the standard deviation of the value of the ith individual performance indicator;
s7: for each chip to be screened, performing: judging whether the value of the ith individual performance index of the current chip to be screened is in the test range of the ith individual performance index, if so, determining that the ith individual performance index of the current chip to be screened is qualified, otherwise, determining that the ith individual performance index of the current chip to be screened is unqualified;
s8: whether i is equal to n, if not, S9 is executed;
s9: and judging whether the ith individual performance index is a key index, if so, taking the chip to be tested, of which the ith individual performance index is qualified, as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, otherwise, taking the chip to be tested of the ith individual performance index as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, wherein i is i + 1.
4. The method of testing a chip according to claim 3,
further comprising:
setting an initial range for each performance index;
the method for determining a plurality of sample chips of the ith individual performance indexes and at least one chip to be screened from the chips to be tested of the ith individual performance indexes comprises the following steps:
aiming at each chip to be tested of the ith individual performance index, executing the following steps: judging whether the value of the ith individual performance index of the current chip to be tested is within the initial range of the ith individual performance index, and if so, determining that the current chip to be tested passes the primary screening;
determining a plurality of sample chips of the ith individual performance indexes from the chips to be tested of the ith individual performance indexes which pass the primary screening, and taking the chips which are not the sample chips in the chips to be tested of the ith individual performance indexes which pass the primary screening as the chips to be screened;
further comprising:
and when the ith individual performance index value of the current chip to be tested is judged not to be in the initial range of the ith individual performance index, determining that the ith individual performance index of the current chip to be tested is unqualified.
5. The method of testing a chip according to claim 3 or 4,
after the determining a plurality of sample chips of the ith performance index and at least one chip to be screened from the chips to be tested of the ith performance index, the method further comprises the following steps:
determining that the ith performance indicator of each sample chip of the ith performance indicator is qualified.
6. An apparatus for testing a chip, comprising:
a sample determination unit for determining a plurality of sample chips from a plurality of chips to be tested;
the index determining unit is used for determining the value of the current performance index of each sample chip;
the statistical unit is used for determining the average value and the standard deviation of the current performance index values of the plurality of sample chips according to the current performance index value of each sample chip;
a range determination unit, configured to generate a test range of the current performance indicator according to a mean value and a standard deviation of the value of the current performance indicator, where the test range of the current performance indicator is (μ:)1-3σ1，μ1+3σ1)，μ1For the current performance indexAverage value of values, σ1Is the standard deviation of the value of the current performance indicator;
a non-sample screening unit for performing, for each non-sample chip of the plurality of chips: determining the value of the current performance index of the current non-sample chip, judging whether the value of the current performance index of the current non-sample chip is in the test range of the current performance index, if so, determining that the current performance index of the current non-sample chip is qualified, otherwise, determining that the current performance index of the current non-sample chip is unqualified;
wherein a chip of the plurality of chips that is not the sample chip is the non-sample chip.
7. The apparatus for testing chips according to claim 6,
further comprising:
a sample screening unit for determining that the current performance index of each of the sample chips is qualified.
8. An apparatus for testing a chip, comprising:
the device comprises a first storage unit, a second storage unit and a third storage unit, wherein the first storage unit is used for storing n individual performance indexes, and the n individual performance indexes are divided into key indexes and non-key indexes;
a test unit to perform:
s1: taking a plurality of chips to be tested as chips to be tested of the 1 st individual performance index, wherein n is a positive integer;
s2: i is 1, i is a positive integer;
s3: determining the value of the ith individual performance index of each chip to be tested of the ith individual performance index;
s4: determining a plurality of sample chips of the ith individual performance index and at least one chip to be screened from the chips to be tested of the ith individual performance index;
s5: determining the average value and the standard deviation of the ith individual performance index value of the sample chip of the ith individual performance index according to the ith individual performance index value of each sample chip of the ith individual performance index;
s6: generating a test range of the ith individual performance index according to the average value and the standard deviation of the value of the ith individual performance index, wherein the test range of the ith individual performance index is (mu)2-3σ2，μ2+3σ2)，μ2Is the average value, σ, of the values of the ith individual performance indicator2Is the standard deviation of the value of the ith individual performance indicator;
s7: for each chip to be screened, performing: judging whether the value of the ith individual performance index of the current chip to be screened is in the test range of the ith individual performance index, if so, determining that the ith individual performance index of the current chip to be screened is qualified, otherwise, determining that the ith individual performance index of the current chip to be screened is unqualified;
s8: whether i is equal to n, if not, S9 is executed;
s9: and judging whether the ith individual performance index is a key index, if so, taking the chip to be tested, of which the ith individual performance index is qualified, as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, otherwise, taking the chip to be tested of the ith individual performance index as the chip to be tested of the (i + 1) th individual performance index, and returning to S3, wherein i is i + 1.
9. The apparatus for testing chips according to claim 8,
further comprising: the second storage unit is used for storing an initial range corresponding to each performance index;
the test unit, when executing the sample chip and the at least one chip to be screened that determine a plurality of ith performance indexes from the chips to be tested of the ith performance index, is specifically configured to:
aiming at each chip to be tested of the ith individual performance index, executing the following steps: judging whether the value of the ith individual performance index of the current chip to be tested is within the initial range of the ith individual performance index, and if so, determining that the current chip to be tested passes the primary screening;
determining a plurality of sample chips of the ith individual performance indexes from the chips to be tested of the ith individual performance indexes which pass the primary screening, and taking the chips which are not the sample chips in the chips to be tested of the ith individual performance indexes which pass the primary screening as the chips to be screened;
the test unit is further configured to:
and when the ith individual performance index value of the current chip to be tested is judged not to be in the initial range of the ith individual performance index, determining that the ith individual performance index of the current chip to be tested is unqualified.
10. The apparatus for testing chips according to claim 8 or 9,
the testing unit is further used for determining that the ith performance index of each sample chip of the ith performance index is qualified.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112775030A (en) * | 2020-12-02 | 2021-05-11 | 华灿光电(苏州）有限公司 | Light emitting diode chip sorting method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101750552A (en) * | 2008-12-10 | 2010-06-23 | 中国科学院自动化研究所 | Benchmark testing system and method for consistency of RFID label antenna |
| US20110181337A1 (en) * | 2010-01-25 | 2011-07-28 | Renesas Electronics Corporation | Semiconductor integrated circuit and electronic device |
| US10118200B2 (en) * | 2009-07-06 | 2018-11-06 | Optimal Plus Ltd | System and method for binning at final test |
| CN109085485A (en) * | 2017-06-14 | 2018-12-25 | 新唐科技股份有限公司 | Semiconductor product test macro and method |
| CN110346704A (en) * | 2019-07-02 | 2019-10-18 | 广州视源电子科技股份有限公司 | Determination method, apparatus, equipment and the storage medium of test file in board test |
-
2019
- 2019-11-21 CN CN201911150434.9A patent/CN110788029B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101750552A (en) * | 2008-12-10 | 2010-06-23 | 中国科学院自动化研究所 | Benchmark testing system and method for consistency of RFID label antenna |
| US10118200B2 (en) * | 2009-07-06 | 2018-11-06 | Optimal Plus Ltd | System and method for binning at final test |
| US20110181337A1 (en) * | 2010-01-25 | 2011-07-28 | Renesas Electronics Corporation | Semiconductor integrated circuit and electronic device |
| CN109085485A (en) * | 2017-06-14 | 2018-12-25 | 新唐科技股份有限公司 | Semiconductor product test macro and method |
| CN110346704A (en) * | 2019-07-02 | 2019-10-18 | 广州视源电子科技股份有限公司 | Determination method, apparatus, equipment and the storage medium of test file in board test |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112775030A (en) * | 2020-12-02 | 2021-05-11 | 华灿光电(苏州）有限公司 | Light emitting diode chip sorting method |
| CN112775030B (en) * | 2020-12-02 | 2022-06-17 | 华灿光电(苏州）有限公司 | Light emitting diode chip sorting method |
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|---|---|
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