CN110784197A - Load matching circuit of double-pulse solid-state modulator and control method thereof - Google Patents
Load matching circuit of double-pulse solid-state modulator and control method thereof Download PDFInfo
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- CN110784197A CN110784197A CN201911110637.5A CN201911110637A CN110784197A CN 110784197 A CN110784197 A CN 110784197A CN 201911110637 A CN201911110637 A CN 201911110637A CN 110784197 A CN110784197 A CN 110784197A
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- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims abstract description 88
- 238000004804 winding Methods 0.000 claims abstract description 21
- 239000007787 solid Substances 0.000 claims description 8
- 230000009977 dual effect Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/02—Amplitude modulation, i.e. PAM
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
Abstract
The invention relates to the field of double-pulse flat top leveling, in particular to a load matching circuit of a double-pulse solid-state modulator and a control method thereof, wherein the load matching circuit comprises at least i matching capacitors, at least n variable capacitor units and at least one matching resistor, i is an integer, n is a positive integer, i is more than or equal to 0, and n is more than or equal to 1; the variable capacitor unit comprises a capacitor and a controlled switch, the input end of the load matching circuit is used for being connected with a first output winding of the pulse transformer, the output end of the load matching circuit is grounded, at least n variable capacitor units are connected with i matching capacitors in series or in parallel and then connected with a matching resistor in series, n + i is larger than or equal to 2, and the equivalent capacitor of the load matching circuit can be adjusted by adjusting the on-off of the controlled switch. According to the invention, the controlled switch is added on the load matching circuit, and the capacitance parameter is adjusted through the controlled switch, so that the problem that two pulse currents cannot be leveled simultaneously when the double-pulse modulator alternately outputs at different pulse amplitudes can be effectively solved, and the output stability can be improved.
Description
Technical Field
The invention relates to the technical field of double-pulse flat top leveling, in particular to a load matching circuit of a double-pulse solid-state modulator and a control method thereof.
Background
The traditional solid-state modulator mostly outputs single pulse intensity, and two different pulse intensities which need to be output by the modulator to work alternately are gradually generated along with the change of the actual application requirements, namely the double-pulse output solid-state modulator.
The pulse output solid-state modulator has high output pulse power, high voltage and high current, and a user system particularly concerns the rising edge time of a pulse waveform, whether the flat top of pulse current and other key technical parameters. Whether the pulse current flat top is flat or not has an important influence on whether the output of the later stage is stable or not.
For the adjustment of the pulse current flat top of the solid-state modulator, it is currently common practice to perform load matching by a parallel RC on the load side, and level the pulse current flat top by changing the value of a capacitor C. When the modulator outputs different voltages or currents, the pulse current flat top can be leveled by changing the capacitance parameters for matching. For a double-pulse output solid-state modulator, since the output pulse current intensity changes at intervals and the working frequency reaches hundreds of hertz originally, one matching parameter cannot simultaneously satisfy two output currents, only one of the output currents can be leveled, and the other output current cannot be leveled, as shown in fig. 9, when the matching circuit outputs a low-energy pulse current as I1, the matching circuit is leveled; however, when a high-energy pulse is sent, the pulse current varies from I2 to I3, and the two pulse waveforms cannot be simultaneously leveled. Therefore, it is necessary to provide a novel matching circuit to achieve leveling of the pulse current plateau when the system alternately outputs different pulse intensities.
Disclosure of Invention
The invention aims to: aiming at the problems in the prior art, the load matching circuit of the double-pulse solid-state modulator and the control method thereof are provided, wherein when the double-pulse modulator alternately outputs different pulse amplitudes, two pulse currents can be simultaneously leveled.
In order to achieve the purpose, the invention adopts the technical scheme that:
a load matching circuit of a double-pulse solid-state modulator comprises at least i matching capacitors, at least n variable capacitor units and at least one matching resistor, wherein i is an integer, n is a positive integer, and i is more than or equal to 0 and n is more than or equal to 1; the variable capacitor unit comprises a capacitor and a controlled switch, the input end of the load matching circuit is used for being connected with a first output winding of the pulse transformer, the output end of the load matching circuit is grounded, at least n variable capacitor units are connected with i matching capacitors in series or in parallel and then connected with a matching resistor in series, n + i is larger than or equal to 2, the equivalent capacitor of the load matching circuit can be adjusted by adjusting the on-off of the controlled switch, and the matching resistor can be one or formed by connecting a plurality of matching resistors in series and/or in parallel.
Preferably, the variable capacitance unit is formed by connecting the controlled switch and the capacitor in series, the i matching capacitors and the n variable capacitance units are connected in parallel to form a variable capacitance module, and the variable capacitance module is connected in series with the matching resistor.
Preferably, the i matching capacitors, i ═ 1, and the n variable capacitance units, n ═ 1.
Preferably, the i matching capacitors, wherein i is 0; the n variable capacitance units are provided, wherein n is more than or equal to 2.
Preferably, the variable capacitance unit is formed by connecting the controlled switch and the capacitor in parallel, the i matching capacitors and the n variable capacitance units are connected in series to form a variable capacitance module, and the variable capacitance module is connected in series with the matching resistor.
Preferably, the i matching capacitors, i ═ 1, and the n variable capacitance units, n ═ 1.
Preferably, the i matching capacitors, wherein i is 0; the n variable capacitance units are provided, wherein n is more than or equal to 2.
Preferably, the controlled switch comprises at least one IGBT, and all the IGBTs are connected in series; or at least one MOSFET, all connected in series.
The invention also provides a control method of the load matching circuit of the double-pulse solid-state modulator, which utilizes the load matching circuit of the double-pulse solid-state modulator to carry out circuit control and comprises the following steps: when the double-pulse solid-state modulator outputs a low-energy pulse signal, at least one controlled switch is switched off, so that the equivalent capacitance of the load matching circuit is matched with the low-energy pulse signal, and the pulse current flat top of the low-energy pulse signal is leveled; when the double-pulse solid-state modulator outputs high-energy pulses, at least one controlled switch is closed, so that the equivalent capacitance of the load matching circuit is matched with the high-energy pulse signals, and the pulse current flat top of the high-energy pulses is leveled.
Preferably, the controlled switch is closed before or at the time when the double-pulse solid-state modulator outputs the high pulse signal, the controlled switch is opened after or at the time when the double-pulse solid-state modulator outputs the high pulse signal, and the on time of the controlled switch is greater than or equal to the time when the double-pulse solid-state modulator outputs the high pulse signal.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. according to the invention, the controlled switch is added on the load matching circuit, and the capacitance parameter is adjusted through the controlled switch, so that the problem that two pulse currents cannot be leveled simultaneously when the double-pulse modulator alternately outputs at different pulse amplitudes can be effectively solved, and meanwhile, the output stability can be improved.
2. According to the invention, by adding a plurality of variable capacitance units, the capacitance parameters required when a matching circuit needs a large matching capacitance can be met.
3. According to the invention, a plurality of IGBTs or MOSFETs are connected in series, and the controlled switch can bear higher voltage.
Drawings
FIG. 1 is a circuit diagram of embodiment 1 of the present invention;
FIG. 2 is a circuit diagram of embodiment 2 of the present invention;
FIG. 3 is a waveform diagram of the control pulses and resulting pulse current of the present invention;
fig. 4 is a circuit diagram of a capacitor C0 and a plurality of variable capacitor units connected in series according to embodiment 3 of the present invention;
FIG. 5 is a circuit diagram of a plurality of variable capacitor units connected in series according to embodiment 4 of the present invention;
FIG. 6 is a circuit diagram according to embodiment 5 of the present invention;
fig. 7 is a circuit diagram of a capacitor C0 connected in parallel with a plurality of variable capacitance units according to embodiment 6 of the present invention;
FIG. 8 is a circuit diagram of multiple parallel variable capacitor units according to embodiment 7 of the present invention;
fig. 9 is a waveform diagram formed by a load matching circuit of the prior art.
The labels in the figure are: 101-pulse switch, 102-pulse transformer, 103-load matching circuit.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1
As shown in fig. 1, a load matching circuit of a dual-pulse solid-state modulator includes a matching capacitor C0, a matching capacitor C1, a controlled switch K1 and a matching resistor R1, wherein a first end of the capacitor C0 is connected to a first output winding of a pulse transformer 102, and a second end of the capacitor C0 is connected to a first end of the capacitor C1; the second end of the capacitor C1 is connected with the first end of the resistor R; the second end of the resistor R is grounded; the controlled switch K1 and the capacitor C1 are connected in parallel to form a variable capacitor unit. When the pulse switch 101 is turned on to output double pulses, the double pulses are output to the load matching circuit 103 through the pulse transformer 102, and the output double pulses are adjusted, the control logic of the switch K1 is as shown in fig. 3, at the time t0, the double-pulse solid-state modulator outputs low-energy pulses, at this time, the controlled switch K1 has no control pulse signal, the controlled switch K1 is not closed, the load matching capacitors are C0 and C1 connected in series, and the equivalent matching capacitance value is
At the time t1, the double-pulse solid-state modulator stops outputting low-energy pulses; at the time t2, before the double-pulse solid-state modulator sends out a high-energy pulse, the controlled switch K1 receives a control pulse, the controlled switch K1 is closed, the controlled switch K1 bypasses the capacitor C1, and at the time t3, the modulator outputs the high-energy pulse, and the load matching capacitance value is C0; at the time t4, the double-pulse solid-state modulator stops outputting high-energy pulses; at time t5, the switch K1 is open; at time t6, the modulator sends out a low-energy pulse; so as to work alternately, the load matching circuit 103 can provide different matching capacitance values for the high-energy pulse and the low-energy pulse respectively, so as to realize that the current waveforms of the high-energy pulse and the low-energy pulse are flat.
Example 2
As shown in fig. 2, the difference between this embodiment and embodiment 1 is that the pulse transformer 102 of this embodiment further includes a second output winding of the pulse transformer and a capacitor Cm, a first end of the capacitor Cm is connected to the first output winding of the pulse transformer, a second end of the capacitor Cm is connected to the second output winding of the pulse transformer, the pulse transformer can enable two windings to output double pulses simultaneously, the two windings are connected together by a capacitor, the load matching circuit 103 can level high and low pulses of the two output windings simultaneously, and this embodiment can output high and low pulses on the two output windings.
Example 3
As shown in fig. 4, the present embodiment is different from embodiment 2 in that the load matching circuit of the present embodiment includes a plurality of variable capacitance units, a capacitor C0 is connected in series with the plurality of variable capacitance units, and the plurality of controlled switches of the plurality of variable capacitance units use the same control signal, and the present embodiment can provide a higher capacitance parameter compared to embodiment 2.
Example 4
As shown in fig. 5, the present embodiment is different from embodiment 3 in that the load matching circuit of the present embodiment eliminates the capacitor C0, the first terminals of the plurality of variable capacitance units are connected to the first output winding of the pulse transformer 102, and the second terminals of the plurality of variable capacitance units are connected to the resistor R.
Example 5
As shown in fig. 6, a load matching circuit of a dual-pulse solid-state modulator includes a capacitor C0, a matching resistor R, and a variable capacitor unit, wherein a first end of the capacitor C0 is connected to a first output winding of a pulse transformer 102, and a second end of the capacitor C0 is connected to a first end of the resistor R; the second end of the resistor R is grounded, the variable capacitor unit is formed by serially connecting a capacitor C1 and a controlled switch K1, and the variable capacitor unit is connected with the capacitor C0 in parallel. As shown in fig. 3, at time t0, the dual-pulse solid-state modulator outputs a low-energy pulse, at this time, the controlled switch K1 has no control pulse, the controlled switch K1 is not closed, the capacitor C1 is not in the matching circuit, the load matching capacitor only has the capacitor C0, and the equivalent matching capacitance value is C0; at the time t1, the double-pulse solid-state modulator stops outputting low-energy pulses; at a time t2, before the double-pulse solid-state modulator sends out a high-energy pulse, the controlled switch K1 receives a control pulse, the controlled switch K1 is closed, at this time, the controlled switch K1 puts the capacitor C1 into the matching circuit, at a time t3, the modulator outputs the high-energy pulse, at this time, the load matching capacitance value is equivalent to that the capacitor C0 is connected with the capacitor C1 in parallel, and the value is C0+ C1; at the time t4, the modulator stops outputting high-energy pulses; at time t5 the controlled switch K1 is open; at time t6, the dual pulse solid state modulator sends out a low energy pulse; so work in turn, load matching circuit can provide different matching capacitance values for high energy and low energy pulse respectively to it is all level and smooth to realize high energy and low energy pulse.
In this embodiment, the pulse transformer 102 further includes a second output winding of the pulse transformer and a capacitor Cm, a first end of the capacitor Cm is connected to the first output winding of the pulse transformer, a second end of the capacitor Cm is connected to the second output winding of the pulse transformer, the pulse transformer can enable the two windings to output double pulses at the same time, the two windings are connected together by a capacitor, the load matching circuit can level high and low pulses of the two output windings at the same time, and this embodiment can output high and low pulses at the two output windings.
Example 6
As shown in fig. 7, the present embodiment is different from embodiment 5 in that the load matching circuit of the present embodiment includes a plurality of variable capacitance units, the variable capacitance units are connected in parallel to form a variable capacitance module, and the variable capacitance module is connected in parallel to a capacitor C0, so that the present embodiment can provide a higher capacitance parameter.
Example 7
As shown in fig. 8, the present embodiment is different from embodiment 6 in that the load matching circuit of the present embodiment eliminates the capacitor C0, the first terminal of the variable capacitor module is connected to the first output winding of the pulse transformer 102, and the second terminal is connected to the resistor R.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A load matching circuit of a double-pulse solid-state modulator is characterized by comprising at least i matching capacitors, at least n variable capacitor units and at least one matching resistor, wherein i is an integer, n is a positive integer, and i is not less than 0 and n is not less than 1; the variable capacitor unit comprises a capacitor and a controlled switch, the input end of the load matching circuit is used for being connected with a first output winding of the pulse transformer, the output end of the load matching circuit is grounded, at least n variable capacitor units are connected with i matching capacitors in series or in parallel and then connected with a matching resistor in series, n + i is larger than or equal to 2, and the equivalent capacitor of the load matching circuit can be adjusted by adjusting the on-off of the controlled switch.
2. The load matching circuit of a dual-pulse solid-state modulator according to claim 1, wherein the variable capacitor unit is formed by connecting the controlled switch and the capacitor in series, the i matching capacitors and the n variable capacitor units are connected in parallel to form a variable capacitor module, and the variable capacitor module is connected in series with the matching resistor.
3. The load matching circuit of a dipulse solid state modulator according to claim 2, wherein said i matching capacitors, where i-1, said n variable capacitor units, where n-1.
4. The load matching circuit of a dual-pulse solid-state modulator of claim 2, wherein said i matching capacitances, where i is 0; the n variable capacitance units are provided, wherein n is more than or equal to 2.
5. The load matching circuit of a dual-pulse solid-state modulator according to claim 1, wherein the variable capacitor unit is formed by connecting the controlled switch and the capacitor in parallel, the i matching capacitors and the n variable capacitor units are connected in series to form a variable capacitor module, and the variable capacitor module is connected in series with the matching resistor.
6. The load matching circuit of a dipulse solid state modulator according to claim 5, wherein said i matching capacitors, where i-1, said n variable capacitor units, where n-1.
7. The load matching circuit of a dual-pulse solid-state modulator of claim 5, wherein said i matching capacitances, where i is 0; the n variable capacitance units are provided, wherein n is more than or equal to 2.
8. The load matching circuit of a dual pulse solid state modulator according to any of claims 1-7, wherein said controlled switch comprises at least one IGBT, all said IGBTs being connected in series; or at least one MOSFET, all connected in series.
9. A method for controlling a load matching circuit of a dual pulse solid state modulator, the method for controlling the load matching circuit of the dual pulse solid state modulator according to any one of claims 1 to 8, comprising: when the double-pulse solid-state modulator outputs a low-energy pulse signal, at least one controlled switch is switched off, so that the equivalent capacitance of the load matching circuit is matched with the low-energy pulse signal, and the pulse current flat top of the low-energy pulse signal is leveled; when the double-pulse solid-state modulator outputs high-energy pulses, at least one controlled switch is closed, so that the equivalent capacitance of the load matching circuit is matched with the high-energy pulse signals, and the pulse current flat top of the high-energy pulses is leveled.
10. The method as claimed in claim 9, wherein the controlled switch is closed before or at the time when the dual pulse solid state modulator outputs the high pulse signal, the controlled switch is opened after or at the end of outputting the high pulse signal, and the on time of the controlled switch is greater than or equal to the time when the dual pulse solid state modulator outputs the high pulse signal.
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| CN201911110637.5A CN110784197A (en) | 2019-11-14 | 2019-11-14 | Load matching circuit of double-pulse solid-state modulator and control method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111355474A (en) * | 2020-03-16 | 2020-06-30 | 四川英杰电气股份有限公司 | Control method of solid-state modulator |
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Application publication date: 20200211 |