CN110783357B - CMOS image sensor with time delay integration and forming method thereof - Google Patents
CMOS image sensor with time delay integration and forming method thereof Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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Abstract
A time delay integrated CMOS image sensor and method of forming the same, the time delay integrated CMOS image sensor comprising: the substrate comprises a plurality of unit areas arranged along a first direction; the first photoelectric region, the second photoelectric region and the source drain region are mutually separated and positioned in the substrate, the source drain region is positioned between the first photoelectric region and the second photoelectric region, and the first photoelectric region and the second photoelectric region respectively cross the plurality of unit regions; and the first gate structure, the second gate structure, the third gate structure and the fourth gate structure are positioned on the substrate in the unit area. Thus, the performance of the time delay integrated CMOS image sensor can be improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a CMOS image sensor with time delay integration and a forming method thereof.
Background
Image sensors have been widely used in digital cameras, mobile phones, medical devices, automobiles, and other applications. The rapid development of image sensor technology has made people have higher requirements on the performance of image sensors.
Time Delay Integration (TDI) image sensors are an evolution of linear image sensors. The imaging mechanism of the time delay integral image sensor is to expose the pixels passing through the object line by line and accumulate the exposure results, thereby solving the problem of weak imaging signals caused by insufficient exposure time of a high-speed moving object. The time delay integral image sensor can increase effective exposure time and improve the signal-to-noise ratio of an image.
The time delay integration image sensor is classified into a CCD and a CMOS. One method is to manufacture a TDI image sensor on a CCD process, and due to the particularity of the CCD process, other processing circuits cannot be integrated on the TDI image sensor, so that the universality and the flexibility are poor. Another type of TDI image sensor is a CMOS type, which is based on a general CMOS manufacturing process, and a device having a CCD-like function, i.e., eccd (embedded CCD), is embedded, thereby forming a TDI-CMOS image sensor.
However, the existing time delay integrated CMOS image sensors still need to have improved performance.
Disclosure of Invention
The invention provides a CMOS image sensor with time delay integration and a forming method thereof, which can improve the performance of the CMOS image sensor with time delay integration.
In order to solve the above technical problem, an embodiment of the present invention provides a CMOS image sensor with time delay integration, including: the substrate comprises a plurality of unit areas arranged along a first direction; the first photoelectric region, the second photoelectric region and the source drain region are separated from each other and located in the substrate, the first photoelectric region and the second photoelectric region are arranged along a second direction, the second direction is perpendicular to the first direction, the source drain region is located between the first photoelectric region and the second photoelectric region, and the first photoelectric region and the second photoelectric region respectively cross the plurality of unit regions; a first gate structure on the substrate in the cell region, the first gate structure being on the first photovoltaic region; a second gate structure on the substrate in the cell region, the second gate structure on the second photovoltaic region; a third gate structure, wherein part or all of the third gate structure is located on the substrate in the cell region, and the third gate structure is located on the surface of the substrate between the first photovoltaic region and the source/drain region; and part or all of the fourth gate structure is positioned on the substrate in the unit region, and the fourth gate structure is positioned on the surface of the substrate between the second photoelectric region and the source-drain region.
Optionally, at least one third gate structure and at least one fourth gate structure are located on the substrate surface of the cell region, and at least 1 source drain region is located in the cell region.
Optionally, the first photovoltaic region has first ions therein, the second photovoltaic region has first ions therein, and the source drain region also has first ions therein.
Optionally, the first gate structure further extends to a surface of the substrate outside the source drain region between the first photovoltaic region and the second photovoltaic region in the cell region.
Optionally, the second gate structure further extends to a surface of the substrate outside the source/drain region between the first photovoltaic region and the second photovoltaic region in the cell region.
Optionally, the method further includes: the second doped regions are arranged in the substrate between the adjacent source and drain regions, second ions are arranged in the second doped regions, the conductivity type of the second ions is opposite to that of the first ions, the second doped regions are arranged along the first direction, and the first grid structure extends to the second doped regions.
Optionally, the method further includes: the second doped regions are arranged in the substrate between the adjacent source and drain regions, second ions are arranged in the second doped regions, the conductivity type of the second ions is opposite to that of the first ions, the second doped regions are arranged along the first direction, and the second grid structures extend onto the second doped regions.
Optionally, the number of the source-drain regions, the third gate structures and the fourth gate structures is 1, and the source-drain regions, the third gate structures and the fourth gate structures all span the plurality of unit regions.
Optionally, the first gate structure further extends to the substrate surface between the projection of the third gate structure on the substrate surface and the first photovoltaic region.
Optionally, the second gate structure further extends to the substrate surface between the projection of the fourth gate structure on the substrate surface and the second photovoltaic region.
Optionally, the substrate further includes more than 1 isolation structure, and the isolation structure is located on one or both of the first photovoltaic region and the second photovoltaic region on a side opposite to the source/drain region.
Correspondingly, the technical scheme of the invention also provides a method for forming the CMOS image sensor with any time delay integration.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the CMOS image sensor with time delay integration, due to the fact that each unit region is provided with the first grid structure, the second grid structure, the partial or all third grid structure and the partial or all fourth grid structure, the third grid structure is located on the surface of the substrate between the first photoelectric region and the source drain region, and the fourth grid structure is located on the surface of the substrate between the second photoelectric region and the source drain region. Therefore, when the channel under the third gate structure is opened, electrons overflowing after the channel under the first gate structure reaches the full well, and when the channel under the fourth gate structure is opened, electrons overflowing after the channel under the second gate structure reaches the full well can be transmitted to the same source-drain region, transmitted from the source-drain region to the interconnection layer electrically interconnected with the source-drain region, and absorbed by the interconnection layer. Therefore, one source drain region can correspond to overflow electrons of 2 photoelectric regions, so that the image sensor can reduce the number of the source drain regions while having an anti-diffusion structure, thereby providing space for increasing the areas of the first photoelectric region and the second photoelectric region, namely increasing the pixel filling factor of the time delay integral CMOS image sensor, enabling the time delay integral CMOS image sensor to obtain higher sensitivity and dynamic range, and improving the performance of the time delay integral CMOS image sensor.
Furthermore, the first gate structure also extends to the surface of the substrate between the first photoelectric region and the second photoelectric region in the cell region and outside the source-drain region, so that the photosensitive surface corresponding to the first photoelectric region can be increased, and the number of charges when the channel under the first gate structure reaches the full-well capacity can be increased, thereby improving the sensitivity and dynamic range of the time delay integration CMOS image sensor, and improving the performance of the time delay integration CMOS image sensor.
Further, since the conductivity type of the second ions is opposite to that of the first ions, and at least 1 first gate structure extends onto the second doped region, a counter doped region is provided between the first photoelectric region and the second photoelectric region, so that dark current between the first photoelectric region and the second photoelectric region can be isolated, and the performance of the time delay integrated CMOS image sensor is improved.
Drawings
FIG. 1 is a schematic diagram of a top view of a time delay integrated CMOS image sensor;
FIG. 2 is a schematic cross-sectional view taken along line A-B of FIG. 1;
fig. 3 to 4 are schematic structural diagrams of a time delay integration CMOS image sensor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a CMOS image sensor with time delay integration according to another embodiment of the present invention;
fig. 6 to 7 are schematic structural diagrams of a time delay integration CMOS image sensor according to another embodiment of the present invention.
Detailed Description
As described in the background, a time delay integrated CMOS image sensor is required to improve performance.
Under the condition of strong light, electrons in a channel below a gate structure overflow into an adjacent channel after reaching a full well, which is called as a dispersion phenomenon, the dispersion phenomenon can cause the adjacent channel to be subjected to charge crosstalk, so that pixel signals subjected to the crosstalk cannot reflect real illumination, the number of saturated pixels is increased compared with the actual number, image color distortion is caused, and the defects of halation and the like of an output image occur, so that the quality of the output image of the CMOS image sensor with time delay integration is reduced.
Fig. 1 is a schematic diagram of a top view structure of a time delay integration CMOS image sensor, and fig. 2 is a schematic diagram of a cross-sectional structure of fig. 1 along a tangential direction of a-B.
Referring to fig. 1 and 2, the time delay integrated CMOS image sensor includes: the photoelectric diode comprises a substrate 10, the substrate 10 is a P-type silicon substrate, the substrate 10 comprises a plurality of photoelectric regions I and isolation regions II which are arranged at intervals, a photoelectric doping region 11 located in the photoelectric region I, source and drain regions 13 and an isolation trench structure 12 located in the isolation regions II are arranged in the substrate, N-type ions with the conductivity type opposite to that of the substrate 10 are doped in the photoelectric doping region 11, so that a photoelectric diode is formed, and the source and drain regions 13 are doped with the N-type ions; a plurality of first gate structures 21 positioned on the surface of the photoelectric region I; the second gate structures 22 are located on the surface of the isolation region II, and projections of the second gate structures 22 on the surface of the substrate 10 are located between projections of the photoelectric doped region 11 on the surface of the substrate 10 and projections of the source drain region 13 on the surface of the substrate 10.
In the above embodiment, a channel under the second gate structure 22 can be opened by applying a fixed positive voltage to the second gate structure 22, and a channel can be formed in the source-drain region 13 by applying a fixed positive voltage to the source-drain region 13, so that electrons in the photoelectric doped region 11 can be transmitted into the channel of the source-drain region 13, and transmitted from the channel of the source-drain region 13 to the interconnect layer electrically interconnected with the source-drain region 13, and absorbed by the interconnect layer, so that when electrons in the channel of the first gate structure 21 overflow after reaching a full well, the overflowing electrons can be absorbed by the interconnect layer, and an anti-blooming effect is achieved.
However, in order to achieve the above-mentioned anti-blooming effect, a source/drain region 13 and a second gate structure 22 need to be separately arranged to correspond to a first gate structure 21, and in order to avoid the problem of electron crosstalk between the photovoltaic regions I, an isolation structure 12 needs to be disposed in each isolation region II to prevent crosstalk of electrons in the channels under the first gate structures 21 in the adjacent photovoltaic regions I, so that the area occupied by the isolation region II is large, which results in a reduction in the proportion of the area of the photovoltaic region I, and a reduction in the pixel fill factor of the time delay integrated CMOS image sensor, thereby reducing the sensitivity and dynamic range of the time delay integrated CMOS image sensor, i.e., reducing the performance of the time delay integrated CMOS image sensor.
In order to solve the technical problems, the technical scheme of the invention provides the time delay integration CMOS image sensor, and one source drain region simultaneously corresponds to two photoelectric regions, so that the number of the source drain region and the isolation structure is reduced, the occupied area of the isolation region is reduced, and the performance of the time delay integration CMOS image sensor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 4 are schematic structural diagrams of a time delay integration CMOS image sensor according to an embodiment of the present invention.
Referring to fig. 3 and 4, fig. 3 is a schematic top view of a time delay integration CMOS image sensor according to an embodiment of the present invention, fig. 4 is a schematic cross-sectional view of fig. 3 along a tangential direction of M-N, and a method for forming the image sensor includes: providing a substrate 100, wherein the substrate 100 comprises a plurality of unit areas V arranged along a first direction Y; a first photovoltaic region 110, a second photovoltaic region 120, and a plurality of source/drain regions 130, which are separated from each other, are formed in the substrate 100.
The material of the substrate 100 is a semiconductor material.
In this embodiment, the material of the substrate 100 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In this embodiment, the substrate 100 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) located on a surface of the substrate, a surface of the substrate 100 is a surface of the silicon epitaxial layer, and the substrate 100 is doped with third ions.
In this embodiment, the first photovoltaic region 110 and the second photovoltaic region 120 are arranged along a second direction X, the second direction X is perpendicular to the first direction Y, the source drain region 130 is located between the first photovoltaic region 110 and the second photovoltaic region 120, and the first photovoltaic region 110 and the second photovoltaic region 120 respectively cross over the plurality of cell regions V.
In this embodiment, the method for forming the first photovoltaic region 110 includes: first ions are doped in the substrate 100. The conductivity type of the third ions is opposite to that of the first ions, that is, the conductivity type of the first ions of the first photovoltaic region 110 is opposite to that of the third ions of the substrate 100, and thus, the photodiode is configured so that the incident light can be converted into electrons.
In this embodiment, the method for forming the second photovoltaic region 120 includes: first ions are doped in the substrate 100. The conductivity type of the third ions is opposite to that of the first ions, that is, the conductivity type of the first ions of the second photovoltaic region 120 is opposite to that of the third ions of the substrate 100, and thus, the photodiode is configured so that the incident light can be converted into electrons.
In this embodiment, the first ions are N-type ions, and the third ions are P-type ions.
In other embodiments, the first ions are P-type ions and the third ions are N-type ions. The P-type ions comprise boron ions or BF2+Ions, the N-type ions comprising phosphorus ions or arsenic ions.
In this embodiment, each of the cell regions V includes 1 of the source/drain regions 130.
The method for forming the source and drain regions 130 includes: in a portion of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 of the cell region V, first ions are doped.
In this embodiment, the method for forming a time delay integrated CMOS image sensor further includes: forming an isolation structure 170 in the substrate, where the isolation structure 170 is located on a side of one or both of the first photovoltaic region 110 and the second photovoltaic region 120 opposite to the source/drain region 130, and the isolation structure 170 spans the cell regions V.
In this embodiment, the method for forming the isolation structure 170 includes: forming a groove (not shown) in the substrate 100, wherein the groove is exposed on the surface of the substrate 100; forming a layer of spacer structure material (not shown) within the grooves and on the surface of the substrate 100; the isolation structure material layer is planarized until the surface of the substrate 100 is exposed, so as to form the isolation structure 170.
With continued reference to fig. 3 and 4, a first gate structure 140 is formed on the substrate 100 in the cell region V, and the first gate structure 140 is located on the first photovoltaic region 110; forming a second gate structure 150 on the substrate 100 in the cell region V, wherein the second gate structure 150 is located on the first photovoltaic region 120; forming a third gate structure 161 on the substrate 100 in the cell region V, wherein the third gate structure 161 is located on the surface of the substrate 100 between the first photovoltaic region 110 and the source/drain region 130; a fourth gate structure 162 is formed on the substrate 100 in the cell region V, and the fourth gate structure 162 is located on the surface of the substrate 100 between the second photovoltaic region 120 and the source/drain region 130.
In this embodiment, the first gate structure 140 includes a first gate dielectric layer (not shown) formed on the surface of the substrate 100, and a first gate electrode layer formed on the surface of the first gate dielectric layer.
In this embodiment, the second gate structure 150 includes a second gate dielectric layer (not shown) formed on the surface of the substrate 100, and a second gate electrode layer formed on the surface of the second gate dielectric layer.
In this embodiment, the third gate structure 161 includes a third gate dielectric layer (not shown) formed on the surface of the substrate 100, and a third gate electrode layer formed on the surface of the third gate dielectric layer.
In this embodiment, the fourth gate structure 162 includes a fourth gate dielectric layer (not shown) formed on the surface of the substrate 100, and a fourth gate electrode layer formed on the surface of the fourth gate dielectric layer.
In this embodiment, a plurality of the first gate structures 140 further extend to the surface of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V and outside the source/drain region 130.
In another embodiment, some of the first gate structures 340 (shown in fig. 5) do not extend to the surface of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V and outside the source drain region 330 (shown in fig. 5).
In the present embodiment, a plurality of the first gate structures 140 further extend to the surface of the isolation structure 170 in the cell region V.
In another embodiment, the first gate structures do not extend to the surface of the isolation structure in the cell region.
In this embodiment, a plurality of the second gate structures 150 further extend to the surface of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V and outside the source/drain region 130.
In another embodiment, the second gate structure 350 (shown in fig. 5) does not extend to the surface of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V and outside the source drain region 330 (shown in fig. 5).
In the present embodiment, a plurality of the second gate structures 150 further extend to the surface of the isolation structure 170 in the cell region V.
In another embodiment, the second gate structures do not extend to the surface of the isolation structure in the cell region.
In this embodiment, the method for forming a time delay integrated CMOS image sensor further includes: a plurality of second doped regions 180 are formed in the substrate 100 between the adjacent source and drain regions 130, the second doped regions 180 are arranged along the first direction Y, and the second doped regions 180 are further located between the first photovoltaic region 110 and the second photovoltaic region 120.
In another embodiment, the second doped region is not formed.
In this embodiment, the method for forming the second doped region 180 includes: second ions are doped in the substrate 100, and the conductivity type of the second ions is opposite to that of the first ions, so that the conductivity type of the second doped region 180 is opposite to that of the first photovoltaic region 110.
In this embodiment, the secondThe ions are P-type ions. In other embodiments, the second ions are N-type ions. The P-type ions comprise boron ions or BF2+Ions, the N-type ions comprising phosphorus ions or arsenic ions.
In the present embodiment, a plurality of the first gate structures 140 extend onto the second doped region 180.
In the present embodiment, a plurality of the second gate structures 150 extend onto the second doped region 180.
In other embodiments, the first gate structures or the second gate structures extend onto the second doped region.
Accordingly, an embodiment of the present invention further provides a CMOS image sensor with time delay integration, please refer to fig. 3 and fig. 4, including: a substrate 100, wherein the substrate 100 includes a plurality of unit regions V arranged along a first direction Y; a first photovoltaic region 110, a second photovoltaic region 120 and a plurality of source drain regions 130 which are separated from each other and located in the substrate 100; a first gate structure 140, a second gate structure 150, a third gate structure 161 and a fourth gate structure 162 on the substrate of the cell region V.
The material of the substrate 100 is a semiconductor material.
In this embodiment, the material of the substrate 100 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In this embodiment, the substrate 100 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) located on a surface of the substrate, a surface of the substrate 100 is a surface of the silicon epitaxial layer, and the substrate 100 has third ions therein.
In this embodiment, the first photovoltaic region 110 and the second photovoltaic region 120 are arranged along a second direction X, the second direction X is perpendicular to the first direction Y, the plurality of source/drain regions 130 are located between the first photovoltaic region 110 and the second photovoltaic region 120, and the first photovoltaic region 110 and the second photovoltaic region 120 respectively cross over the plurality of cell regions V.
In the present embodiment, the first photovoltaic region 110 has first ions therein. The conductivity type of the third ions is opposite to that of the first ions, that is, the conductivity type of the first ions of the first photovoltaic region 110 is opposite to that of the third ions of the substrate 100, and thus, the photodiode is configured so that the incident light can be converted into electrons.
In this embodiment, the second photovoltaic region 120 has first ions therein. The conductivity type of the third ions is opposite to that of the first ions, that is, the conductivity type of the first ions of the second photovoltaic region 120 is opposite to that of the third ions of the substrate 100, and thus, the photodiode is configured so that the incident light can be converted into electrons.
In this embodiment, the first ions are N-type ions, and the third ions are P-type ions.
In other embodiments, the first ions are P-type ions and the third ions are N-type ions. The P-type ions comprise boron ions or BF2+Ions, the N-type ions comprising phosphorus ions or arsenic ions.
In this embodiment, each of the cell regions V includes 1 source drain region 130, and the source drain region 130 has first ions therein.
In this embodiment, the time delay integrated CMOS image sensor further includes: an isolation structure 170 located in the substrate 100, wherein the isolation structure 170 is located on a side of one or both of the first photovoltaic region 110 and the second photovoltaic region 120 opposite to the source/drain region 130, and the isolation structure 170 spans the plurality of cell regions V.
Since the isolation structure 170 is disposed on the opposite side of one or both of the first photovoltaic region 110 and the second photovoltaic region 120 from the source/drain region 130, the image sensor can improve the isolation effect of the current crosstalk and the light crosstalk to the first photovoltaic region 110 and the second photovoltaic region 120, thereby improving the performance of the time delay integrated CMOS image sensor.
In this embodiment, the first gate structure 140 includes a first gate dielectric layer (not shown) on the surface of the substrate 100, and a first gate electrode layer on the surface of the first gate dielectric layer.
In this embodiment, the second gate structure 150 includes a second gate dielectric layer (not shown) on the surface of the substrate 100, and a second gate electrode layer on the surface of the second gate dielectric layer.
In this embodiment, the third gate structure 161 includes a third gate dielectric layer (not shown) on the surface of the substrate 100, and a third gate electrode layer on the surface of the third gate dielectric layer.
In this embodiment, the fourth gate structure 162 includes a fourth gate dielectric layer (not shown) on the surface of the substrate 100, and a fourth gate electrode layer on the surface of the fourth gate dielectric layer.
In this embodiment, the first gate structure 140 is located on the first photovoltaic region 110, the second gate structure 150 is located on the first photovoltaic region 120, the third gate structure 161 is located on the surface of the substrate 100 between the first photovoltaic region 110 and the source/drain region 130, the fourth gate structure 162 is located on the surface of the substrate 100 between the second photovoltaic region 120 and the source/drain region 130, and the fourth gate structure 162 is located on the surface of the substrate 100 between the second photovoltaic region 120 and the source/drain region 130.
Since each cell region V has a first gate structure 140, a second gate structure 150, a third gate structure 161, and a fourth gate structure 162 therein, the third gate structure 161 is located on the surface of the substrate 100 between the first photovoltaic region 110 and the source drain region 130, and the fourth gate structure 162 is located on the surface of the substrate 100 between the second photovoltaic region 120 and the source drain region 130, when opening a channel under the third gate structure 161, electrons overflowing after the channel under the first gate structure 161 reaches a full well can be transmitted to the source drain region 130 in the same cell region V, and when opening a channel under the fourth gate structure 162, electrons overflowing after the channel under the second gate structure 162 reaches a full well can be transmitted to the source drain region 130 in the same cell region V, so that the source drain region 130 can simultaneously correspond to the overflowing electrons generated by the first photovoltaic region 110 and the second photovoltaic region 120, the CMOS image sensor with the time delay integration has an anti-dispersion structure, and meanwhile, the number of the source and drain regions can be reduced, so that a space is provided for increasing the areas of the first photoelectric region 110 and the second photoelectric region 120, that is, the pixel filling factor of the CMOS image sensor with the time delay integration can be increased, the CMOS image sensor with the time delay integration can obtain higher sensitivity and dynamic range, and the performance of the CMOS image sensor with the time delay integration is improved.
Moreover, when the source-drain region 130 and the interconnection layer are electrically interconnected, electrons entering the source-drain region 130 can also be transmitted from the source-drain region 130 to the interconnection layer electrically interconnected with the source-drain region 130, and absorbed by the interconnection layer, so that the source-drain region 130 is not filled with well overflow electrons, and thus, the source-drain region 130 can always receive overflow electrons from the first photoelectric region 110 and the second photoelectric region 120, the stability of the time delay integration CMOS image sensor is improved, and the interference of the overflow electrons of the source-drain region 130 on the time delay integration CMOS image sensor is reduced.
In this embodiment, a plurality of the first gate structures 140 further extend to the surface of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V and outside the source/drain region 130.
Since the first gate structure 140 further extends to the surface of the substrate 100 outside the source/drain region 130 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V, the photosensitive surface corresponding to the first photovoltaic region 110 can be increased, and the number of charges when the channel under the first gate structure 140 reaches the full well capacity can be increased, so that the sensitivity and the dynamic range of the time delay integration CMOS image sensor are improved, and the performance of the time delay integration CMOS image sensor is improved.
In another embodiment, some of the first gate structures 340 (shown in fig. 5) do not extend to the surface of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V and outside the source drain region 330 (shown in fig. 5).
In the present embodiment, a plurality of the first gate structures 140 further extend to the surface of the isolation structure 170 in the cell region V.
Since the first gate structure 140 further extends to the surface of the isolation structure 170 in the cell region V, the photosensitive surface corresponding to the first photoelectric region 110 can be further increased, and the number of charges when the channel under the first gate structure 140 reaches the full well capacity can be increased, so that the sensitivity and the dynamic range of the time delay integration CMOS image sensor can be improved, and the performance of the time delay integration CMOS image sensor can be improved.
In another embodiment, the first gate structures do not extend to the surface of the isolation structure in the cell region.
In this embodiment, a plurality of the second gate structures 150 further extend to the surface of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V and outside the source/drain region 130.
Since the second gate structure 150 further extends to the surface of the substrate 100 outside the source/drain region 130 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V, the photosensitive surface corresponding to the second photovoltaic region 120 can be increased, and the number of charges when the channel under the second gate structure 150 reaches the full well capacity can be increased, so that the sensitivity and the dynamic range of the time delay integration CMOS image sensor are improved, and the performance of the time delay integration CMOS image sensor is improved.
In another embodiment, a plurality of the second gate structures 350 (shown in fig. 5) do not extend to the surface of the substrate 100 between the first photovoltaic region 110 and the second photovoltaic region 120 in the cell region V and outside the source drain region 330 (shown in fig. 5).
In the present embodiment, a plurality of the second gate structures 150 further extend to the surface of the isolation structure 170 in the cell region V.
Since the second gate structure 150 further extends to the surface of the isolation structure 170 in the cell region V, the photosensitive surface corresponding to the second photovoltaic region 120 can be further increased, and the number of charges when the channel under the second gate structure 150 reaches the full well capacity can be increased, so that the sensitivity and the dynamic range of the time delay integrated CMOS image sensor can be improved, and the performance of the time delay integrated CMOS image sensor can be improved.
In another embodiment, the second gate structures do not extend to the surface of the isolation structure in the cell region.
In this embodiment, the time delay integrated CMOS image sensor further includes: in the substrate 100 between the adjacent source and drain regions 130, the second doped regions 180 are arranged along the first direction Y, and the second doped region 180 is further located between the first photovoltaic region 110 and the second photovoltaic region 120. The second doped region 180 has second ions therein, and the conductivity type of the second ions is opposite to the conductivity type of the first ions, such that the conductivity type of the second doped region 180 is opposite to the conductivity type of the first photovoltaic region 110.
In another embodiment, the substrate between the adjacent source and drain regions does not have a plurality of second doped regions.
In this embodiment, the second ions are P-type ions. In other embodiments, the second ions are N-type ions. The P-type ions comprise boron ions or BF2+Ions, the N-type ions comprising phosphorus ions or arsenic ions.
In the present embodiment, a plurality of the first gate structures 140 extend onto the second doped region 180.
Since the conductivity type of the second ions is opposite to that of the first ions, and at least 1 of the first gate structures 140 extends onto the second doped region 180, there is a counter-doped region between the first photo-electric region 110 and the second photo-electric region 120, so that the dark current between the first photo-electric region 110 and the second photo-electric region 120 can be isolated, and the performance of the time delay integrated CMOS image sensor is improved.
In the present embodiment, a plurality of the second gate structures 150 extend onto the second doped region 180.
Since the conductivity type of the second ions is opposite to that of the first ions, and at least 1 second gate structure 150 extends onto the second doped region 180, there is a counter-doped region between the first photovoltaic region 110 and the second photovoltaic region 120, so that the dark current between the first photovoltaic region 110 and the second photovoltaic region 120 can be isolated, and the performance of the time delay integrated CMOS image sensor is improved.
In other embodiments, the first gate structures or the second gate structures extend onto the second doped region.
In this embodiment, in a direction perpendicular to the surface of the substrate 100, the depth of the second doped region 180 is smaller than the depth of the source/drain region 130.
Fig. 6 to 7 are schematic structural diagrams of a time delay integration CMOS image sensor according to another embodiment of the present invention.
Referring to fig. 6 and 7, fig. 6 is a schematic top view of a time delay integration CMOS image sensor according to another embodiment of the present invention, fig. 7 is a schematic cross-sectional view taken along a direction of a U-W tangent in fig. 6, and the method for forming the time delay integration CMOS image sensor includes: providing a substrate 200, wherein the substrate 200 comprises a plurality of unit regions P arranged along a first direction Y; a first photovoltaic region 210, a second photovoltaic region 220 and a source drain region 230 are formed in the substrate 200, wherein the first photovoltaic region, the second photovoltaic region and the source drain region are separated from each other.
The material of the substrate 200 is a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In this embodiment, the substrate 200 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) located on a surface of the substrate, a surface of the substrate 200 is a surface of the silicon epitaxial layer, and the substrate 200 is doped with third ions.
In this embodiment, the first photovoltaic region 210 and the second photovoltaic region 220 are arranged along a second direction X, the second direction X is perpendicular to the first direction Y, the source drain region 230 is located between the first photovoltaic region 210 and the second photovoltaic region 220, and the first photovoltaic region 210 and the second photovoltaic region 220 respectively cross over the plurality of cell regions P.
In this embodiment, the method for forming the first photovoltaic region 210 includes: first ions are doped in the substrate 200. The conductivity type of the third ions is opposite to that of the first ions, that is, the conductivity type of the first ions of the first photovoltaic region 210 is opposite to that of the third ions of the substrate 200, and thus, the photodiode is configured so that the incident light can be converted into electrons.
In this embodiment, the method for forming the second photovoltaic region 220 includes: first ions are doped in the substrate 200. The conductivity type of the third ions is opposite to that of the first ions, i.e., the conductivity type of the first ions of the second photovoltaic region 220 is opposite to that of the third ions of the substrate 200, and thus, the photodiode is constructed so as to be able to convert incident light into electrons.
In this embodiment, the first ions are N-type ions, and the third ions are P-type ions.
In other embodiments, the first ions are P-type ions and the third ions are N-type ions. The P-type ions comprise boron ions or BF2+Ions, the N-type ions comprising phosphorus ions or arsenic ions.
In this embodiment, the method for forming the source and drain regions 230 includes: first ions are doped in a portion of the substrate 100 crossing the cell regions P between the first photovoltaic region 110 and the second photovoltaic region 120, thereby forming source and drain regions 230 crossing the cell regions P.
In this embodiment, the method for forming a time delay integrated CMOS image sensor further includes: forming an isolation structure 270 in the substrate, where the isolation structure 270 is located on one side of one or both of the first photovoltaic region 210 and the second photovoltaic region 220 opposite to the source/drain region 230, and the isolation structure 270 spans the cell regions P.
In this embodiment, the method for forming the isolation structure 270 includes: forming a groove (not shown) in the substrate 200, wherein the groove is exposed on the surface of the substrate 200; forming a layer of spacer structure material (not shown) within the grooves and on the surface of the substrate 200; the isolation structure material layer is planarized until the surface of the substrate 200 is exposed, so as to form the isolation structure 270.
With continued reference to fig. 6 and 7, a first gate structure 240 is formed on the substrate 200 in the cell region P, and the first gate structure 240 is located on the first photovoltaic region 210; forming a second gate structure 250 on the substrate 200 in the cell region P, wherein the second gate structure 250 is located on the second photovoltaic region 220; forming a third gate structure 261 on the substrate 200, where the third gate structure 261 is located on the surface of the substrate 200 between the first photovoltaic region 210 and the source/drain region 230, and the third gate structure 261 spans a plurality of the cell regions P; a fourth gate structure 262 is formed on the substrate 200, the fourth gate structure 262 is located on the surface of the substrate 200 between the second photovoltaic region 220 and the source/drain region 230, and the fourth gate structure 262 spans a plurality of the cell regions P.
In this embodiment, the first gate structure 240 includes a first gate dielectric layer (not shown) formed on the surface of the substrate 200, and a first gate electrode layer formed on the surface of the first gate dielectric layer.
In this embodiment, the second gate structure 250 includes a second gate dielectric layer (not shown) formed on the surface of the substrate 200, and a second gate electrode layer formed on the surface of the second gate dielectric layer.
In this embodiment, the third gate structure 261 includes a third gate dielectric layer (not shown) formed on the surface of the substrate 200, and a third gate electrode layer formed on the surface of the third gate dielectric layer.
In this embodiment, the fourth gate structure 262 includes a fourth gate dielectric layer (not shown) formed on the surface of the substrate 200, and a fourth gate electrode layer formed on the surface of the fourth gate dielectric layer.
In this embodiment, a plurality of the first gate structures 240 further extend to a portion of the third gate structure 261 in the cell region P on the surface of the substrate 200 between the projection of the surface of the substrate 200 and the first photovoltaic region 210.
In another embodiment, a portion of the third gate structure that does not extend into the cell region is on the substrate surface between a projection of the substrate surface and the first photovoltaic region.
In this embodiment, a plurality of the first gate structures 240 further extend to the surface of the isolation structure 270 in the cell region P.
In another embodiment, the first gate structures do not extend to the surface of the isolation structure in the cell region.
In this embodiment, a plurality of the second gate structures 250 further extend to a portion of the fourth gate structure 262 in the cell region P on the surface of the substrate 200 between the projection of the surface of the substrate 200 and the second photovoltaic region 220.
In another embodiment, the plurality of second gate structures do not extend to the portion of the fourth gate structure in the cell region on the substrate surface between the projection of the substrate surface and the second photovoltaic region.
In the present embodiment, a plurality of the second gate structures 250 also extend to the surface of the isolation structure 270 in the cell region P.
In another embodiment, the second gate structures do not extend to the surface of the isolation structure in the cell region.
Accordingly, another embodiment of the present invention further provides a CMOS image sensor with time delay integration, please refer to fig. 6 to 7, which includes: a substrate 200, wherein the substrate 200 includes a plurality of unit regions P arranged along a first direction Y; a first photovoltaic region 210, a second photovoltaic region 220 and a source drain region 230 which are located in the substrate 200 and are separated from each other; the first gate structure 240 and the second gate structure 250 are located on the substrate 200 of the cell region V, the third gate structure 261 is located on the surface of the substrate 200 between the first photovoltaic region 210 and the source-drain region 230, and the fourth gate structure 262 is located on the surface of the substrate 200 between the second photovoltaic region 220 and the source-drain region 230.
The material of the substrate 200 is a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In this embodiment, the substrate 200 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) located on a surface of the substrate, a surface of the substrate 200 is a surface of the silicon epitaxial layer, and the substrate 200 has third ions therein.
In this embodiment, the first photovoltaic region 210 and the second photovoltaic region 220 are arranged along a second direction X, the second direction X is perpendicular to the first direction Y, the source drain region 230 is located between the first photovoltaic region 210 and the second photovoltaic region 220, and the first photovoltaic region 210, the second photovoltaic region 220, and the source drain region 230 respectively cross over the plurality of cell regions P.
In the present embodiment, the first photovoltaic region 210 has first ions therein. The conductivity type of the third ions is opposite to that of the first ions, that is, the conductivity type of the first ions of the first photovoltaic region 210 is opposite to that of the third ions of the substrate 200, and thus, the photodiode is configured so that the incident light can be converted into electrons.
In the present embodiment, the second photovoltaic region 220 has first ions therein. The conductivity type of the third ions is opposite to that of the first ions, i.e., the conductivity type of the first ions of the second photovoltaic region 220 is opposite to that of the third ions of the substrate 200, and thus, the photodiode is constructed so as to be able to convert incident light into electrons.
In the present embodiment, the source drain region 230 has first ions therein.
In this embodiment, the first ions are N-type ions, and the third ions are P-type ions.
In other embodiments, the first ions are P-type ions and the third ions are N-type ions. The P-type ions comprise boron ions or BF2+Ions, the N-type ions comprising phosphorus ions or arsenic ions.
In this embodiment, the time delay integrated CMOS image sensor further includes: an isolation structure 270 located in the substrate, wherein the isolation structure 270 is located on a side of one or both of the first photovoltaic region 210 and the second photovoltaic region 220 opposite to the source drain region 230, and the isolation structure 270 spans the cell regions P.
Since the isolation structure 270 is disposed on the opposite side of one or both of the first photovoltaic region 210 and the second photovoltaic region 220 from the source/drain region 230, the image sensor can improve the isolation effect of the current crosstalk and the light crosstalk to the first photovoltaic region 210 and the second photovoltaic region 220, thereby improving the performance of the CMOS image sensor with time delay integration.
In this embodiment, the first gate structure 240 includes a first gate dielectric layer (not shown) on the surface of the substrate 200, and a first gate electrode layer on the surface of the first gate dielectric layer.
In this embodiment, the second gate structure 250 includes a second gate dielectric layer (not shown) on the surface of the substrate 200, and a second gate electrode layer on the surface of the second gate dielectric layer.
In this embodiment, the third gate structure 261 includes a third gate dielectric layer (not shown) on the surface of the substrate 200, and a third gate electrode layer on the surface of the third gate dielectric layer.
In this embodiment, the fourth gate structure 262 includes a fourth gate dielectric layer (not shown) on the surface of the substrate 200, and a fourth gate electrode layer on the surface of the fourth gate dielectric layer.
In this embodiment, the first gate structure 240 is located on the first photovoltaic region 210, the second gate structure 250 is located on the second photovoltaic region 220, the third gate structure 261 is located on the surface of the substrate 100 between the first photovoltaic region 210 and the source/drain region 230, the third gate structure 261 spans a plurality of the cell regions P, the fourth gate structure 262 is located on the surface of the substrate 200 between the second photovoltaic region 220 and the source/drain region 230, and the fourth gate structure 262 spans a plurality of the cell regions P.
Because each cell region P has a first gate structure 240 and a second gate structure 250 therein, the third gate structure 261 is located on the surface of the substrate 200 between the first photovoltaic region 210 and the source drain region 230, the fourth gate structure 262 is located on the surface of the substrate 200 between the second photovoltaic region 220 and the source drain region 230, and each cell region P has a portion of the third gate structure 261 and a portion of the fourth gate structure 262 therein, when a channel under the third gate structure 261 is opened, electrons overflowing after the channel under the first gate structure 261 reaches a full well, and when a channel under the fourth gate structure 262 is opened, electrons overflowing after the channel under the second gate structure 262 reaches a full well can be transmitted into the source drain region 230. Therefore, the source-drain regions 230 can simultaneously correspond to the overflow electrons generated by the first photovoltaic region 210 and the second photovoltaic region 220, so that the CMOS image sensor with time delay integration has an anti-dispersion structure and can reduce the number of the source-drain regions, thereby providing a space for increasing the areas of the first photovoltaic region 210 and the second photovoltaic region 220, that is, increasing the pixel filling factor of the CMOS image sensor with time delay integration, so that the CMOS image sensor with time delay integration obtains higher sensitivity and dynamic range, and the performance of the CMOS image sensor with time delay integration is improved.
Moreover, when the source-drain region 230 and the interconnect layer are electrically interconnected, electrons entering the source-drain region 230 can also be transmitted from the source-drain region 230 to the interconnect layer electrically interconnected with the source-drain region 230, and absorbed by the interconnect layer, so that the source-drain region 230 does not fill a well with overflow electrons, and thus the source-drain region 230 can always receive overflow electrons from the first photoelectric region 210 and the second photoelectric region 220, thereby improving the stability of the CMOS image sensor with time delay integration, and reducing interference of the overflow electrons of the source-drain region 230 on the CMOS image sensor with time delay integration.
In this embodiment, a plurality of the first gate structures 240 further extend to a portion of the third gate structure 261 in the cell region P on the surface of the substrate 200 between the projection of the surface of the substrate 200 and the first photovoltaic region 210.
Since the first gate structure 240 further extends to the portion of the third gate structure 261 in the cell region P on the surface of the substrate 200 between the projection of the surface of the substrate 200 and the first photovoltaic region 210, the photosensitive surface corresponding to the first photovoltaic region 210 can be increased, and the number of charges when the channel under the first gate structure 240 reaches the full well capacity can be increased, so that the sensitivity and the dynamic range of the time delay integrated CMOS image sensor are improved, and the performance of the time delay integrated CMOS image sensor is improved.
In another embodiment, a portion of the third gate structure that does not extend into the cell region is on the substrate surface between a projection of the substrate surface and the first photovoltaic region.
In this embodiment, a plurality of the first gate structures 240 further extend to the surface of the isolation structure 270 in the cell region P.
Since the first gate structure 240 further extends to the surface of the isolation structure 270 in the cell region P, the photosensitive surface corresponding to the first photoelectric region 210 can be further increased, and the number of charges when the channel under the first gate structure 240 reaches the full well capacity can be increased, so that the sensitivity and the dynamic range of the time delay integrated CMOS image sensor are improved, and the performance of the time delay integrated CMOS image sensor is improved.
In another embodiment, the first gate structures do not extend to the surface of the isolation structure in the cell region.
In this embodiment, a plurality of the second gate structures 250 further extend to a portion of the fourth gate structure 262 in the cell region P on the surface of the substrate 200 between the projection of the surface of the substrate 200 and the second photovoltaic region 220.
Since the second gate structure 250 further extends to the portion of the fourth gate structure 262 in the cell region P on the surface of the substrate 200 between the projection of the surface of the substrate 200 and the second photovoltaic region 220, the photosensitive surface corresponding to the second photovoltaic region 220 can be increased, and the number of charges when the channel under the second gate structure 250 reaches the full well capacity can be increased, so that the sensitivity and the dynamic range of the time delay integrated CMOS image sensor are improved, and the performance of the time delay integrated CMOS image sensor is improved.
In another embodiment, the second gate structures 450 do not extend to the portion of the fourth gate structure in the cell region on the substrate surface between the projection of the substrate surface and the second photovoltaic region.
In the present embodiment, a plurality of the second gate structures 250 also extend to the surface of the isolation structure 270 in the cell region P.
Since the second gate structure 250 further extends to the surface of the isolation structure 270 in the cell region P, the photosensitive surface corresponding to the second photovoltaic region 220 can be further increased, and the number of charges when the channel under the second gate structure 250 reaches the full well capacity can be increased, so that the sensitivity and the dynamic range of the time delay integrated CMOS image sensor are improved, and the performance of the time delay integrated CMOS image sensor is improved.
In another embodiment, the second gate structures do not extend to the surface of the isolation structure in the cell region.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A time delay integrated CMOS image sensor, comprising:
the substrate comprises a plurality of unit areas arranged along a first direction;
the first photoelectric region, the second photoelectric region and the source drain region are separated from each other and located in the substrate, the first photoelectric region and the second photoelectric region are arranged along a second direction, the second direction is perpendicular to the first direction, the source drain region is located between the first photoelectric region and the second photoelectric region, and the first photoelectric region and the second photoelectric region respectively cross the plurality of unit regions;
a first gate structure on the substrate in the cell region, the first gate structure being on the first photovoltaic region;
a second gate structure on the substrate in the cell region, the second gate structure on the second photovoltaic region;
a third gate structure, wherein part or all of the third gate structure is located on the substrate in the cell region, and the third gate structure is located on the surface of the substrate between the first photovoltaic region and the source/drain region;
and part or all of the fourth gate structure is positioned on the substrate in the unit region, and the fourth gate structure is positioned on the surface of the substrate between the second photoelectric region and the source-drain region.
2. The time delay integrated CMOS image sensor of claim 1, wherein at least one third gate structure and at least one fourth gate structure are located on a substrate surface of the cell region, and at least 1 of the source drain regions are located within the cell region.
3. The time delay integrated CMOS image sensor of claim 2, wherein the first photo-electric region has first ions therein, the second photo-electric region has first ions therein, and the source and drain regions also have first ions therein.
4. The time delay integrated CMOS image sensor of claim 3, wherein the first gate structure further extends to a substrate surface outside the source drain regions between the first and second photo-electric regions within the cell region.
5. The time delay integrated CMOS image sensor of claim 3 or 4, wherein the second gate structure further extends to a substrate surface outside the source drain regions between the first photovoltaic region and the second photovoltaic region within the cell region.
6. The time delay integrated CMOS image sensor of claim 4, further comprising: the second doped regions are arranged in the substrate between the adjacent source and drain regions, second ions are arranged in the second doped regions, the conductivity type of the second ions is opposite to that of the first ions, the second doped regions are arranged along the first direction, and the first grid structure extends to the second doped regions.
7. The time delay integrated CMOS image sensor of claim 5, further comprising: the second doped regions are arranged in the substrate between the adjacent source and drain regions, second ions are arranged in the second doped regions, the conductivity type of the second ions is opposite to that of the first ions, the second doped regions are arranged along the first direction, and the second grid structures extend onto the second doped regions.
8. The time delay integrated CMOS image sensor of claim 1, wherein the number of the source drain regions, the third gate structures, and the fourth gate structures is 1, and the source drain regions, the third gate structures, and the fourth gate structures all span the plurality of cell regions.
9. The time delay integrated CMOS image sensor of claim 8, wherein the first gate structure further extends to a substrate surface between a projection of the third gate structure onto the substrate surface and the first photovoltaic region.
10. The time delay integrated CMOS image sensor of claim 8, wherein the second gate structure further extends to the substrate surface between a projection of the fourth gate structure onto the substrate surface and the second photovoltaic region.
11. The time delay integrated CMOS image sensor of claim 1, further comprising more than 1 isolation structure in the substrate, the isolation structure being located on a side of one or both of the first and second photovoltaic regions opposite the source and drain regions.
12. A method of forming a time delay integrated CMOS image sensor as claimed in any one of claims 1 to 11.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005461A (en) * | 2009-08-28 | 2011-04-06 | 索尼公司 | Solid-state imaging device, manufacturing method thereof, and electronic apparatus |
| CN103811512A (en) * | 2014-03-17 | 2014-05-21 | 北京思比科微电子技术股份有限公司 | Image sensor pixel structure for preventing image diffusion and manufacture method thereof |
| CN109273477A (en) * | 2018-10-31 | 2019-01-25 | 昆山锐芯微电子有限公司 | CMOS-TDI imaging sensor and forming method thereof |
| CN109950265A (en) * | 2019-03-25 | 2019-06-28 | 德淮半导体有限公司 | Imaging sensor and its manufacturing method, control method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7605415B2 (en) * | 2004-06-07 | 2009-10-20 | Canon Kabushiki Kaisha | Image pickup device comprising photoelectric conversation unit, floating diffusion region and guard ring |
| KR101352436B1 (en) * | 2012-10-31 | 2014-01-20 | 주식회사 동부하이텍 | An image sensor |
-
2019
- 2019-11-11 CN CN201911095808.1A patent/CN110783357B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005461A (en) * | 2009-08-28 | 2011-04-06 | 索尼公司 | Solid-state imaging device, manufacturing method thereof, and electronic apparatus |
| CN103811512A (en) * | 2014-03-17 | 2014-05-21 | 北京思比科微电子技术股份有限公司 | Image sensor pixel structure for preventing image diffusion and manufacture method thereof |
| CN109273477A (en) * | 2018-10-31 | 2019-01-25 | 昆山锐芯微电子有限公司 | CMOS-TDI imaging sensor and forming method thereof |
| CN109950265A (en) * | 2019-03-25 | 2019-06-28 | 德淮半导体有限公司 | Imaging sensor and its manufacturing method, control method |
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