CN110782938B

CN110782938B - Nonvolatile memory device, operating method and memory controller operating method

Info

Publication number: CN110782938B
Application number: CN201910645034.9A
Authority: CN
Inventors: 金成骏; 尹恩振; 蒋尚焕
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2018-07-24
Filing date: 2019-07-17
Publication date: 2023-06-16
Anticipated expiration: 2039-07-17
Also published as: KR20200011136A; US20200035278A1; CN110782938A; US10818328B2; KR102650603B1

Abstract

Provided are a nonvolatile memory device, an operating method thereof, and an operating method of a memory controller, the nonvolatile memory device including: a control logic circuit that receives a read command from outside the nonvolatile memory device; a memory cell array including a plurality of memory cells connected to a plurality of word lines; an address generator that generates a plurality of addresses based on read information from outside the nonvolatile memory device; an address decoder sequentially selecting a plurality of pages in at least one word line corresponding to a plurality of addresses; a page buffer circuit connected to the memory cell array through a plurality of bit lines, preparing a plurality of sequential data from the memory cells connected to the page selected by the address decoder; and an input/output circuit that continuously outputs the plurality of sequential data from the page buffer circuit to the outside of the nonvolatile memory device through the data line.

Description

Nonvolatile memory device, operating method and memory controller operating method

The present application claims priority from korean patent application No. 10-2018-0085868 filed in the korean intellectual property office on 24 th 7 of 2018, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Embodiments of the inventive concept relate to a semiconductor memory, and more particularly, to a nonvolatile memory device, a method of operating the nonvolatile memory device, and a method of operating a memory controller controlling the nonvolatile memory device.

Background

Semiconductor memories are classified into volatile memory devices such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM) and nonvolatile memory devices such as flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or Ferroelectric RAM (FRAM), in which data stored in the volatile memory devices disappears when power is turned off, and in which data stored in the nonvolatile memory devices remains even when power is turned off.

Flash memory devices are being widely used as storage media in computing devices. In general, flash memory devices manage data on a page basis. For example, flash memory devices operate in response to page-based read commands or write commands from a memory controller. That is, since command calls or address calls are used on a page basis for the purpose of controlling the flash memory device, overhead due to the command calls or address calls when a large amount of data is transferred occurs.

Disclosure of Invention

Embodiments of the inventive concept provide a nonvolatile memory device having improved reliability, a method of operating the nonvolatile memory device, and a method of operating a memory controller controlling the nonvolatile memory device.

According to an exemplary embodiment, a nonvolatile memory device includes: a control logic circuit that receives a sequential read command from outside the nonvolatile memory device; a memory cell array including a plurality of memory cells connected to a plurality of word lines; a sequential address generator that generates a plurality of sequential addresses based on read information received from outside the nonvolatile memory device under control of a control logic circuit that receives a sequential read command; an address decoder connected to the memory cell array through a plurality of word lines and sequentially selecting a plurality of pages in at least one word line corresponding to a plurality of sequential addresses from the plurality of word lines under control of a control logic circuit receiving a sequential read command; a page buffer circuit connected to the memory cell array through a plurality of bit lines and preparing a plurality of sequential data from memory cells connected to a page selected by the address decoder under the control of a control logic circuit receiving a sequential read command; and an input/output circuit that continuously outputs the plurality of sequential data from the page buffer circuit to the outside of the nonvolatile memory device through the data line under the control of the control logic circuit. A plurality of sequential data are stored in memory cells connected to the selected page. The input/output circuit continuously outputs a plurality of sequential data without receiving an additional read command from outside the nonvolatile memory device while continuously outputting the plurality of sequential data.

According to an exemplary embodiment, a method of operating a non-volatile memory device includes: during a first command input interval, receiving a first sequential read command from outside the non-volatile memory device through the data line; sequentially reading information from outside the nonvolatile memory device through the data line during an address input section subsequent to the first command input section; receiving a second sequential read command from outside the nonvolatile memory device through the data line during a second command input section subsequent to the address input section; and after the second command input section, sequentially outputting a plurality of sequential data based on the sequential read information. The plurality of sequential data corresponds to the plurality of physical pages, respectively. When a plurality of sequential data are output, the nonvolatile memory device does not receive an additional read command from outside the nonvolatile memory device through the data line.

According to an exemplary embodiment, a method of operating a memory controller that controls a nonvolatile memory device includes: transmitting a first sequential read command to the nonvolatile memory device through the data line during a first command input interval; transmitting sequential read information to the nonvolatile memory device through the data line during an address input section subsequent to the first command input section; transmitting a second sequential read command to the nonvolatile memory device through the data line during a second command input interval subsequent to the address input interval; and after the second command input interval, providing a read enable signal to the non-volatile memory device to continuously receive a plurality of sequential data from the non-volatile memory device. The plurality of sequential data is stored in a plurality of selected physical pages of memory cells of a memory cell array connected to the nonvolatile memory device.

Drawings

The above objects and features, and other objects and features of the inventive concept will become apparent by the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a memory system according to an example embodiment of the inventive concepts.

Fig. 2 is a block diagram illustrating a memory controller of fig. 1 according to an example embodiment.

Fig. 3 is a block diagram illustrating the nonvolatile memory device of fig. 1 according to an example embodiment.

Fig. 4A to 4C are timing charts showing the operation of the nonvolatile memory device.

Fig. 5A is a flowchart illustrating a sequential read operation of the non-volatile memory device of fig. 1 according to an example embodiment.

Fig. 5B is a flowchart illustrating sequential read operations of the non-volatile memory device of fig. 1 according to other example embodiments.

Fig. 6 is a timing diagram illustrating operation of the non-volatile memory device according to the flowcharts of fig. 5A and 5B according to example embodiments.

Fig. 7A to 7D are diagrams for describing various sequential read modes of the nonvolatile memory device of fig. 1 according to example embodiments.

Fig. 8 is a diagram for describing information about the size of sequential data shown in fig. 6 according to an example embodiment.

Fig. 9A and 9B are diagrams for describing information about the number of sequential data shown in fig. 6 according to example embodiments.

Fig. 10 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the inventive concept.

Fig. 11 is a diagram illustrating the lookup table of fig. 10 according to an example embodiment.

Fig. 12A is a flowchart illustrating an operation of the nonvolatile memory device of fig. 10 according to an example embodiment.

Fig. 12B is a flowchart illustrating an operation of the nonvolatile memory device of fig. 10 according to an example embodiment.

Fig. 13 is a block diagram illustrating a memory system according to an embodiment of the inventive concept.

Fig. 14 is a flowchart illustrating an operation of the nonvolatile memory device of fig. 13 according to an example embodiment.

Fig. 15A and 15B are block diagrams illustrating a memory system according to an embodiment of the inventive concept.

Fig. 16A is a diagram illustrating information managed by a sequential address generator included in the memory controller of fig. 15A according to an example embodiment.

Fig. 16B is a diagram illustrating information managed by a sequential data manager included in the memory controller of fig. 15B according to an example embodiment.

Fig. 17 is a block diagram illustrating a solid state drive system to which a nonvolatile memory device according to the inventive concept is applied.

Detailed Description

Hereinafter, embodiments of the inventive concept may be described in detail and clearly to such an extent that those skilled in the art easily implement the inventive concept.

Fig. 1 is a block diagram illustrating a memory system according to an example embodiment of the inventive concepts. Referring to fig. 1, a memory system 100 may include a memory controller 110 and a nonvolatile memory device 120. In an embodiment, the memory system 100 may be a high-capacity storage medium such as a Solid State Drive (SSD) or a memory card for use in a computing device.

The memory controller 110 may be configured to control the nonvolatile memory device 120 in response to a request of an external device (e.g., a host, a Central Processing Unit (CPU), or an Application Processor (AP)) or under the control of the external device. For example, in order to control the nonvolatile memory device 120, the memory controller 110 may transmit and receive various signals through the control signal line CTRL, the data line DQx, and the data strobe line.

In an exemplary embodiment, various signals, such as a command latch enable signal CLE, an address latch enable signal ALE, a read enable signal RE, and/or a write enable signal WE, may be provided to the nonvolatile memory device 120 through the control signal line CTRL. Various information such as a command CMD, an address ADDR, and data DT may be transmitted and received between the memory controller 110 and the nonvolatile memory device 120 through the data line DQx. In an exemplary embodiment, the memory controller 110 and the nonvolatile memory device 120 may distinguish and recognize the command CMD, the address ADDR, and the data DT provided through the data line DQx based on various signals provided through the control signal line CTRL and the data strobe line.

In response to various signals from the memory controller 110, the nonvolatile memory device 120 may store the data DT received from the memory controller 110 or may transmit the stored data DT to the memory controller 110. In an example embodiment, in the case where the nonvolatile memory device 120 performs a program operation or a read operation under the control of the memory controller 110, the nonvolatile memory device 120 may provide a ready/busy signal R/B to the memory controller 110, and the memory controller 110 may recognize whether the nonvolatile memory device 120 is operating in response to the ready/busy signal R/B. In an exemplary embodiment, the memory controller 110 may not exchange information (e.g., commands, addresses, or data) with the nonvolatile memory device 120 in the case where the ready/busy signal R/B indicates a busy state.

In an exemplary embodiment, the nonvolatile memory device 120 may include an address generator 121 (hereinafter referred to as a "sequential address generator"). According to example embodiments of the inventive concepts, the sequential address generator 121 may be configured to generate a plurality of addresses based on advanced read information SQRI (hereinafter referred to as "sequential read information") in an advanced read operation (hereinafter referred to as "sequential read operation"). The nonvolatile memory device 120 may perform a sequential read operation by outputting a plurality of sequential data based on a plurality of sequential addresses generated thereby.

In an example embodiment, the sequential address generator 121 may generate a plurality of sequential addresses or a plurality of random addresses based on the sequential read information SQRI in the sequential read operation.

In an exemplary embodiment, the sequential read operation according to an exemplary embodiment of the inventive concept may refer to a read operation that outputs a plurality of sequential data without a call or issuance of a separate command or address from a page unit of the memory controller 110. Here, the command or address of the page unit may be used to read data of one page (or one page of data) or data of N pages (N is an integer equal to or less than the number of bits stored in one memory unit). For example, a word line may include one page or N pages. The terms "page-based command or address", and "page unit command or address" will be interchangeable. Through the sequential read operation, the nonvolatile memory device 120 may generate a plurality of sequential addresses based on the sequential read information SQRI supplied from the memory controller 110, and may output a plurality of sequential data based on the plurality of sequential addresses thus generated. In an exemplary embodiment, the plurality of sequential addresses may correspond to different physical pages or different logical pages, respectively.

That is, the conventional nonvolatile memory device requires a command or address of a page unit to be called from a memory controller in order to perform a sequential cache read operation or a random cache read operation. In contrast, the nonvolatile memory device 120 according to the inventive concept may output a plurality of sequential data (i.e., a large amount of data) by generating a plurality of sequential addresses based on the sequential read information SQRI without an additional call of a command or address of a page unit. This may mean that the performance of the non-volatile memory device 120 is improved. Sequential read operations of the nonvolatile memory device 120 according to the inventive concept will be described with reference to the accompanying drawings.

Fig. 2 is a block diagram illustrating a memory controller of fig. 1 according to an example embodiment. Referring to fig. 1 and 2, the memory controller 110 may include a processor 111, a Static RAM (SRAM) 112, a Read Only Memory (ROM) 113, a host interface 114, and a flash memory interface 115.

The processor 111 may control the overall operation of the memory controller 110. SRAM112 may be used as a buffer memory, cache memory, or working memory for memory controller 110. The ROM113 may store various information required for the operation of the memory controller 110 in the form of firmware.

In an exemplary embodiment, various information (e.g., flash translation layer FTL and mapping table) required to control the nonvolatile memory device 120 may be stored in the SRAM112 or a separate buffer memory and may be managed or driven by the processor 111.

The memory controller 110 may communicate with external devices (e.g., hosts) through a host interface 114. In an exemplary embodiment, host interface 114 may include at least one of a variety of interfaces, such as a Double Data Rate (DDR) interface, a Universal Serial Bus (USB) interface, a multimedia card (MMC) interface, a Peripheral Component Interconnect (PCI) interface, a PCI-express (PCI-e) interface, an Advanced Technology Attachment (ATA) interface, a serial ATA (SATA) interface, a parallel ATA (PATA) interface, a Small Computer System Interface (SCSI), an enhanced compact disc interface (ESDI), an Integrated Drive Electronics (IDE) interface, a Mobile Industrial Processor Interface (MIPI), and a high-speed nonvolatile memory (NVM-e) interface.

The memory controller 110 may communicate with the nonvolatile memory device 120 through the flash interface 115. In an example embodiment, the memory controller 110 may provide the various signals (e.g., CLE, ALE, RE/, WE/, CMD, ADDR, SQRI, and DT) described with reference to fig. 1 to the non-volatile memory device 120 based on the flash interface 115. In an exemplary embodiment, the flash interface 115 may include a NAND interface such as a switched NAND interface (toggle NAND interface) or an open source NAND flash interface (open NAND flash interface, ONFI).

The memory controller 110 shown in fig. 2 is an example, and the inventive concept is not limited thereto. Memory controller 110 may also include various components such as an Error Correction Code (ECC) engine, randomizer, and buffer management circuitry.

Fig. 3 is a block diagram illustrating the nonvolatile memory device of fig. 1 according to an example embodiment. Referring to fig. 1 and 3, the nonvolatile memory device 120 may include a sequential address generator 121, a memory cell array 122, an address decoder 123, a page buffer circuit 124, an input/output circuit 125, and a control logic circuit 126.

In the embodiment, the command CMD, the address ADDR, the sequential read information SQRI, and the data DT are separately shown for simplicity of explanation and for convenience of description, but the inventive concept is not limited thereto. For example, as described above, the command CMD, the address ADDR, the sequential read information SQRI, and the data DT may be received from the memory controller 110 through the data line DQx, and may be distinguished from one another based on the control signal CTRL (e.g., CLE, ALE, RE/and WE /).

The sequential address generator 121 may generate the sequential address addr_sq based on the sequential read information SQRI received from the memory controller 110. For example, the nonvolatile memory device 120 may perform sequential read operations in response to sequential read commands (SQRD) and sequential read information SQRI from the memory controller 110. The sequential read operation refers to an operation of sequentially outputting a plurality of sequential data without a separate command from the memory controller 110. In this case, the sequential address generator 121 may generate a plurality of sequential addresses addr_sq for sequential read operations based on the sequential read information SQRI. For example, one of the plurality of sequential addresses addr_sq may be a combination of one or more row addresses and one or more column addresses specifying a particular word line and a particular page among the selected word lines.

In an exemplary embodiment, the sequential read information SQRI may include information about a read mode (hereinafter, referred to as a "sequential read mode"), information about a size of sequential data, the number of sequential data, and the like. The sequential address generator 121 may generate a plurality of sequential addresses addr_sq based on information about the sequential read mode. The number of sequential addresses addr_sq thus generated may correspond to the number of sequential data described above.

In an exemplary embodiment, the plurality of sequential addresses addr_sq may correspond to a plurality of different pieces of page data, respectively. Multiple pieces of different page data may refer to physical page data stored in memory cells connected to different word lines. Alternatively, a plurality of different pieces of page data may refer to a plurality of different pieces of logical page data, respectively. That is, the plurality of sequential addresses addr_sq may refer to addresses of different pages.

The memory cell array 122 may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings connected to the bit line BL, and each of the plurality of cell strings includes a plurality of cell transistors connected in series. The plurality of cell transistors may be connected to a string selection line SSL, a word line WL, or a ground selection line GSL.

The address decoder 123 may be connected to the memory cell array 122 through a string selection line SSL, a word line WL, and a ground selection line GSL. The address decoder 123 may decode the address ADDR received from the memory controller 110 or the plurality of sequential addresses addr_sq received from the sequential address generator 121, and may control the string selection line SSL, the word line WL, and the ground selection line GSL based on the decoded result. For example, the address decoder 123 may sequentially select and control word lines corresponding to a plurality of sequential addresses addr_sq from a plurality of word lines of the memory cell array 122.

The address decoder 123 may select a plurality of pages in one or more word lines of the memory cell array 122 through a string selection line SSL, a word line WL, and a ground selection line GSL.

The page buffer circuit 124 is connected to the memory cell array 122 through a bit line BL. The page buffer circuit 124 may be configured to temporarily store data to be stored to the memory cell array 122 or data read from the memory cell array 122.

The input/output circuit 125 may provide the data DT received from the memory controller 110 to the page buffer circuit 124. The input/output circuit 125 may provide the data DT received from the page buffer circuit 124 to the memory controller 110.

The control logic 126 may receive a command CMD from the memory controller 110 and may control components of the nonvolatile memory device 120 such that operations corresponding to the received command CMD are performed.

In an exemplary embodiment, in the case where the command CMD received from the memory controller 110 is a sequential read command, the control logic circuit 126 may allow the sequential address generator 121 to generate the sequential address addr_sq based on the sequential read information SQRI. In this case, the generated sequential address addr_sq may be a start address to read data from the memory cell.

Fig. 4A to 4C are timing charts showing the operation of the nonvolatile memory device. The page read operation of the nonvolatile memory device 120 will be described with reference to fig. 4A, the sequential cache read operation of the nonvolatile memory device 120 will be described with reference to fig. 4B, and the random cache read operation of the nonvolatile memory device 120 will be described with reference to fig. 4C. In fig. 4B and 4C, some control signals (e.g., CLE, ALE, WE/, RE/and DQS) are omitted for simplicity of illustration. In the following, reference numerals for some commands, some addresses, and some data are briefly labeled for simplicity of explanation.

Referring to fig. 1, 3 and 4A, the nonvolatile memory device 120 may receive the first read command RD1 during the command Input interval CMD Input. Thereafter, the nonvolatile memory device 120 may receive the address AD during the address Input section ADDR Input. The nonvolatile memory device 120 may receive the second read command RD2 during a command Input section CMD Input following the address Input section ADDR Input.

In an exemplary embodiment, the first read command RD1 and the second read command RD2 may be command sets (e.g., 00h and 30 h) for a page read operation. In an exemplary embodiment, the address AD may be received during some cycles (or loops) (e.g., 5 cycles (or loops)) of the write enable signal WE. As an example, 3 addresses AD may be received as row addresses and page addresses in 3 cycles, and 2 addresses AD may be received as column addresses in another 2 cycles. A combination of 3 addresses AD may be used to select one word line and one page in the selected one word line, and a combination of 2 addresses AD may be used to select a position to start data output in the selected page. However, the inventive concept is not limited thereto. The address AD refers to a row address or a column address of a physical page corresponding to a page in which read data is stored.

In response to the second read command RD2, the nonvolatile memory device 120 may read the data DT corresponding to the received address AD from the memory cell array 122. For example, the nonvolatile memory device 120 may read the data DT corresponding to the received address AD, and may prepare the read data DT in the page buffer circuit 124 or the input/output circuit 125. The read data DT may be prepared during the period tR. In an exemplary embodiment, during the period of tR, the nonvolatile memory device 120 may provide a ready/busy signal R/B of logic low (i.e., busy state) to the memory controller 110.

In the following exemplary embodiments, the term "data preparation operation" or "preparation data" is used for convenience of description. The term "data preparation operation" or "preparation data" refers to an operation of storing or setting read data stored in the memory cell array to a page buffer circuit (e.g., a cache latch) or an input/output circuit so that the data can be output to the memory controller 110.

After the data preparation operation is completed, the nonvolatile memory device 120 may respond to the read enable signal RE/generate the data strobe signal DQS received from the memory controller 110 and may output the data DT in synchronization with the generated data strobe signal DQS through the data line DQx.

In an exemplary embodiment, the data DT Output during the page read operation (i.e., the data Output during the data Output interval DT Output) based on the timing diagram of fig. 4A may be single page data (e.g., 8KB or 16 KB). That is, the nonvolatile memory device 120 may output a single page of data based on the timing chart shown in fig. 4A.

In an exemplary embodiment, table 1 below shows control signals in each of a command Input section CMD Input, an address Input section ADDR Input, and a data Output section DT Output.

TABLE 1

	CLE	ALE	RE/	WE/	DQS
						CMD Input	H	L	H	↑	X
ADDR Input	L	H	H	↑	X
						DT Output	L	L	↓↑	H	↓↑

Referring to table 1, in the command Input section CMD Input, the command latch enable signal CLE and the read enable signal RE/are logic high "H", and the address latch enable signal ALE is logic low "L". During the command Input interval CMD Input, the nonvolatile memory device 120 latches a signal received through the data line DQx as a command CMD at a rising edge ∈ of the write enable signal WE. In the address Input section ADDR Input, the address latch enable signal ALE and the read enable signal RE/are logic high "H", and the command latch enable signal CLE is logic low "L". During the address Input section ADDR Input, the nonvolatile memory device 120 latches a signal received through the data line DQx at the rising edge +.f. of the write enable signal WE/as the address AD. In this case, the address may be information corresponding to a page in which read data is stored.

In the data Output section DT Output, the command latch enable signal CLE and the address latch enable signal ALE are logic low "L", and the write enable signal WE is logic high "H". In the data Output section DT Output, the nonvolatile memory device 120 generates the data strobe signal DQS based on the read enable signal RE, and outputs the data DT in synchronization with the rising edge ∈ and the falling edge ∈ of the data strobe signal DQS through the data line DQx.

In the exemplary embodiment, the signal levels of table 1 are examples, and the inventive concept is not limited thereto. In the following figures, control signals (e.g., CLE, ALE, RE/and WE /) are omitted for simplicity of illustration. However, the control signals may be controlled as shown in table 1 in the command Input section CMD Input, the address Input section ADDR Input, and the data Output section DT Output.

Referring to fig. 1, 3, and 4B, the nonvolatile memory device 120 may perform sequential cache read operations based on the timing diagram of fig. 4B. For example, the nonvolatile memory device 120 may receive the first cache read command CRD1 during the command Input interval CMD Input. Thereafter, the nonvolatile memory device 120 may receive the first address AD1 during the address Input section ADDR Input. Then, the nonvolatile memory device 120 may receive the second cache read command CRD2 during the command Input interval CMD Input. During the period of tR, the nonvolatile memory device 120 may read data of the first page corresponding to the first address AD1 as the first cache data dt_c1 in response to the second cache read command CRD2.

Then, the nonvolatile memory device 120 may receive the third cache read command CRD3 during the command Input interval CMD Input. During the period of tDCBSYR, the nonvolatile memory device 120 may prepare the previously read first cache data dt_c1 in response to the third cache read command CRD3.

After the period of tDCBSYR, the nonvolatile memory device 120 may output the first buffer data dt_c1 through the data line DQx. Meanwhile, the nonvolatile memory device 120 reads data of a second page different from the first page as the second buffer data dt_c2.

The nonvolatile memory device 120 may also receive a third cache read command CRD3 during the command Input interval CMD Input. During the period of tDCBSYR, the nonvolatile memory device 120 may prepare the previously read second buffer data dt_c2 in response to the third buffer read command CRD3 and may output the second buffer data dt_c2 through the data line DQx. Meanwhile, the nonvolatile memory device 120 reads data of another page (e.g., a third page) as the third buffer data dt_c3.

Thereafter, the nonvolatile memory device 120 may receive the fourth cache read command CRD4 during the command Input interval CMD Input, may prepare the third cache data dt_c3 in response to the fourth cache read command CRD4, and may output the prepared third cache data dt_c3 through the data line DQx. In an exemplary embodiment, each of the first to third buffer data dt_c1 to dt_c3 may be single page data.

Referring to fig. 1, 3, and 4C, the nonvolatile memory device 120 may perform a random cache read operation based on the timing diagram of fig. 4C. For example, the nonvolatile memory device 120 may sequentially receive the first cache read command CRD1, the first address AD1, and the second cache read command CRD2. Thereafter, during the period of tR, the nonvolatile memory device 120 may read data of a page corresponding to the first address AD1 as the first buffer data dt_c1.

Then, the nonvolatile memory device 120 may sequentially receive the first cache read command CRD1, the second address AD2, and the third cache read command CRD3. In response to the third cache read command CRD3, the nonvolatile memory device 120 may prepare the previously read first cache data dt_c1 during the period of tDCBSYR and may output the first cache data dt_c1 through the data line DQx. Meanwhile, the nonvolatile memory device 120 may read data of a page corresponding to the second address AD2 as the second buffer data dt_c2.

Then, the nonvolatile memory device 120 may sequentially receive the first cache read command CRD1, the third address AD3, and the third cache read command CRD3. In response to the third cache read command CRD3, the nonvolatile memory device 120 may prepare the previously read second cache data dt_c2 during the period of tDCBSYR and may output the second cache data dt_c2 through the data line DQx. Meanwhile, the nonvolatile memory device 120 may read data of a page corresponding to the third address AD3 as the third buffer data dt_c3.

Thereafter, the nonvolatile memory device 120 may receive the fourth cache read command CRD4, may prepare the previously read third cache data dt_c3 in response to the fourth cache read command CRD4, and may output the prepared third cache data dt_c3 through the data line DQx.

As described above, in order for the nonvolatile memory device 120 to perform a sequential cache read operation or a random cache read operation, a command call or an address call from a page unit of the memory controller 110 is required. For example, as shown in fig. 4B or 4C, a page-based command or a page-based address is received from the memory controller 110 between the transmission of the first to third buffer data dt_c1 to dt_c3. That is, in a conventional sequential read operation or a conventional random cache read operation, a plurality of cache data are discontinuously output through the data line DQx.

In an example embodiment, for sequential read operations of the non-volatile memory device 120, no separate command or address invocation or issue of the page unit is used in outputting the plurality of sequential data. For example, the nonvolatile memory device 120 may receive signals such as a set of sequential read commands and sequential read information, and may output a plurality of sequential data based on the received signals. In this case, the plurality of sequential data may be a plurality of data corresponding to a plurality of pages, respectively. Sequential read operations of the nonvolatile memory device according to embodiments of the inventive concept will be described with reference to the following drawings.

Fig. 5A is a flowchart illustrating a sequential read operation of the non-volatile memory device of fig. 1 according to an example embodiment. Referring to fig. 1, 3 and 5A, in operation S110, the nonvolatile memory device 120 may receive a first sequential read command SQRD1 (e.g., a first advanced read command) during a first command Input section 1st CMD Input.

In operation S120, the nonvolatile memory device 120 may receive the sequential read information SQRI during the address Input section ADDR Input. In an exemplary embodiment, the sequential read information SQRI may include information related to a sequential read mode, information related to a size of sequential data, information related to the number of sequential data, and the like.

In operation S130, the nonvolatile memory device 120 may receive a second sequential read command SQRD2 (e.g., a second advanced read command) during a second command Input section 2nd CMD Input. In an exemplary embodiment, the first sequential read command SQRD1 and the second sequential read command SQRD2 may be command sets for sequential read operations (e.g., advanced read operations).

In operation S140, the nonvolatile memory device 120 may generate a plurality of sequential addresses addr_sq based on the sequential read information SQRI. For example, the sequential address generator 121 of the nonvolatile memory device 120 may generate a plurality of sequential addresses addr_sq (e.g., a plurality of sequentially generated sequential addresses or a plurality of randomly generated sequential addresses) based on an address generation manner or algorithm corresponding to a sequential read mode of the sequential read information SQRI.

In operation S150, the nonvolatile memory device 120 may prepare a plurality of sequential data dt_sq based on a plurality of sequential addresses addr_sq. For example, a plurality of sequential data dt_sq may be prepared in the page buffer circuit 124 or in the input/output circuit 125. In operation S160, the nonvolatile memory device 120 may output the plurality of sequential data dt_sq without a separate command.

In an exemplary embodiment, the nonvolatile memory device 120 may perform operation S150 and operation S160 in parallel (or simultaneously). For example, in the case where the sequential address generator 121 generates the first sequential address addr_sq1 to the nth sequential address addr_sqn, first, the nonvolatile memory device 120 may prepare the first sequential data dt_sq1 corresponding to the first sequential address addr_sq1. Thereafter, the nonvolatile memory device 120 may prepare the second sequential data dt_sq2 corresponding to the second sequential address addr_sq2 while outputting the first sequential data dt_sq1. Thereafter, the nonvolatile memory device 120 may prepare the third sequential data dt_sq3 corresponding to the third sequential address addr_sq3 while outputting the second sequential data dt_sq2. The nonvolatile memory device 120 may repeatedly perform the above operation until the nth sequential data dt_sqn corresponding to the nth sequential address addr_sqn is output.

As described above, the nonvolatile memory device 120 according to the inventive concept may generate a plurality of sequential addresses addr_sq based on the sequential read information SQRI received during the address Input section ADDR Input, and may output a plurality of sequential data dt_sq based on the plurality of sequential addresses addr_sq thus generated. In this case, since the page-based command or address call is not used when outputting the plurality of sequential data dt_sq, the speed of outputting the data can be increased.

Fig. 5B is a flowchart illustrating a sequential read operation of the non-volatile memory device of fig. 1 according to an example embodiment. Referring to fig. 1, 3 and 5B, the nonvolatile memory device 120 may perform operations S410 to S470. Operations S410 to S440 are similar to operations S110 to S140 of fig. 5A, and thus, detailed descriptions thereof will not be repeated here.

In operation S450, the nonvolatile memory device 120 may prepare the first sequential data dt_sq1 based on the first sequential address addr_sq1. For example, the first sequential data dt_sq1 may be prepared in the page buffer circuit 124 or in the input/output circuit 125. In operation S460, the nonvolatile memory device 120 may sequentially output the first sequential data dt_sq1 without any additional read command.

In operation S470, the nonvolatile memory device 120 may determine whether all sequential data dt_sq based on the sequential read information SQRI is transmitted.

In the case where all the sequential data dt_sq has not been transmitted to the memory controller 110 (i.e., in the case where there is sequential data dt_sq that has not been transmitted to the memory controller 110), the nonvolatile memory device 120 may repeatedly perform operations S450 and S460. For example, the nonvolatile memory device 120 may prepare the second sequential data dt_sq2 based on the second sequential address addr_sq2 in operation S450. For example, the second sequential data dt_sq2 may be prepared in the page buffer circuit 124 or in the input/output circuit 125. In operation S460, the nonvolatile memory device 120 may sequentially output the second sequential data dt_sq2 after outputting the first sequential data dt_sq1 without any additional read command.

Fig. 6 is a timing diagram illustrating the operation of the nonvolatile memory device according to the flowcharts of fig. 5A and 5B. As in the above description, some control signals (e.g., CLE, ALE, RE/, WE/and DQS) are omitted for simplicity of illustration. Next, the control signals are controlled as shown in table 1 in the command Input section CMD Input, the address Input section ADDR Input, and the data Output section DT Output.

Referring to fig. 1, 5A, 5B, and 6, the nonvolatile memory device 120 may receive the first sequential read command SQRD1 through the data line DQx during the first command Input section 1st CMD Input.

After that, the nonvolatile memory device 120 may receive the sequential read information SQRI through the data line DQx during the address Input section ADDR Input. In the exemplary embodiment, in the page read operation, the sequential cache read operation, and the random cache read operation described with reference to fig. 4A to 4C, the physical address corresponding to the read data is received during the address Input section ADDR Input. However, in the advanced read operation of the nonvolatile memory device 120 according to the inventive concept, the sequential read information SQRI is received during the address Input section ADDR Input. In this case, the sequential read information SQRI may be information different from the general address ADDR.

For example, the sequential reading information SQRI may include pieces of information related to the sequential reading mode SRM, the sequential data size SDS, and the number of sequential data NSD. The information included in the sequential read information SQRI may be received during a plurality of cycles of the write enable signal WE. For example, as described with reference to fig. 4A, in the address Input section ADDR Input, the write enable signal WE may be switched as many as a plurality of cycles (for example, n times, where n is an integer greater than 1). As an example, one cycle (or one period) may be the same as the width of one rising pulse or the width of one falling pulse. Various information (e.g., sequential read mode SRM, sequential data size SDS, and number of sequential data NSD) included in the sequential read information SQRI may be provided in synchronization with a rising edge or a falling edge of the write enable signal WE/switched during a plurality of cycles.

Thereafter, the nonvolatile memory device 120 may receive the second sequential read command SQRD2 during the second command Input interval 2nd CMD Input. The nonvolatile memory device 120 may perform a sequential data preparation operation in response to the second sequential read command SQRD2. For example, as described above, the sequential address generator 121 of the nonvolatile memory device 120 may generate a plurality of sequential addresses addr_sq based on the sequential read information SQRI. The nonvolatile memory device 120 may prepare a plurality of sequential data dt_sq based on the plurality of sequential addresses addr_sq thus generated.

For example, as described with reference to fig. 6, the nonvolatile memory device 120 may prepare the first sequential data dt_sq1 corresponding to the first sequential address addr_sq1 during the first period T1. The external ready/busy signal ext.r/B and the internal ready/busy signal int.r/B may be kept in a low state (i.e., a busy state) while the first sequential data dt_sq1 is prepared.

In an embodiment, the external ready/busy signal ext.r/B may be a signal informing the memory controller 110 of an operation state of the nonvolatile memory device 120, and the internal ready/busy signal int.r/B may be a signal informing an internal operation inside the nonvolatile memory device 120. For example, even if the internal ready/busy signal int.r/B is in a low state (i.e., a busy state), the nonvolatile memory device 120 may provide the sequential data dt_sq to the memory controller 110 through the data line DQx when the external ready/busy signal ext.r/B is in a high state (i.e., a ready state).

When the first sequential data dt_sq1 is ready, the external ready/busy signal ext.r/B and the internal ready/busy signal int.r/B may be converted to a high state (i.e., a ready state). Thereafter, the nonvolatile memory device 120 may output the first sequential data dt_sq1 under the control of the memory controller 110. The nonvolatile memory device 120 may prepare the second sequential data dt_sq2 corresponding to the second sequential address adrr_sq2 during the second period T2 while outputting the first sequential data dt_sq1. In this case, during the second period T2, the external ready/busy signal ext.r/B may remain in a high state (i.e., a ready state), and the internal ready/busy signal int.r/B may remain in a low state (i.e., a busy state).

In the case where the first sequential data dt_sq1 is completely transmitted and the second sequential data dt_sq2 is completely prepared, the nonvolatile memory device 120 may output the second sequential data dt_sq2 under the control of the memory controller 110. Similarly, the nonvolatile memory device 120 may prepare the third sequential data dt_sq3 corresponding to the third sequential address addr_sq3 while outputting the second sequential data dt_sq2. The nonvolatile memory device 120 may repeatedly perform the above operations until the nth sequential data dt_sqn is output. By repeatedly performing the above operations, the first to nth sequential data dt_sq1 to dt_sqn may be "sequentially or continuously" output. For example, the nonvolatile memory device 120 does not receive an additional sequential read command from the memory controller 110 while sequentially outputting the first to nth sequential data dt_sq1 to dt_sqn.

In an exemplary embodiment, "sequentially or continuously" outputting the first to nth sequential data dt_sq1 to dt_sqn means that no other command or address is received from the memory controller 110 through the data line DQx during the output of the first to nth sequential data dt_sq1 to dt_sqn. For example, after the first sequential data dt_sq1 is output, the second sequential data dt_sq2 may be output without a separate command or a separate address from the memory controller 110.

For example, in a sequential read operation, the nonvolatile memory device 120 according to an embodiment of the inventive concept may not receive a separate command from the memory controller 110 through the data line DQx while outputting the first to nth sequential data dt_sq1 to dt_sqn. For example, after receiving the first sequential read command SQRD1, the sequential read information SQRI, and the second sequential read command SQRD2, the nonvolatile memory device 120 may not receive a separate command (e.g., the cache read command described with reference to fig. 4B and 4C) while outputting the plurality of sequential data dt_sq. In this way, since a separate command is not used while outputting a plurality of sequential data dt_sq, the speed at which the nonvolatile memory device 120 outputs data can be increased.

In an exemplary embodiment, the memory controller 110 may provide the read enable signal RE/' to the nonvolatile memory device 120 in response to an external ready/busy signal ext.r/B of a high state (i.e., ready state). The nonvolatile memory device 120 may output a plurality of sequential data dt_sq1 to dt_sqn in response to a read enable signal RE received from the memory controller 110.

In an example embodiment, the first to nth sequential addresses addr_sq1 to addr_sqn may be sequentially or randomly generated based on the sequential read information SQRI.

Fig. 7A to 7D are exemplary diagrams for describing various sequential read modes of the nonvolatile memory device of fig. 1 according to example embodiments. Some of various sequential read modes of a nonvolatile memory device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 7A to 7D, but the inventive concept is not limited thereto.

For simplicity of illustration and for ease of description, it is assumed that the memory cell array 122 includes a first plane PL1 and a second plane PL2, the first plane PL1 including memory blocks BLK11 and BLK12, the second plane PL2 including memory blocks BLK21 and BLK22, each of the memory blocks BLK11, BLK12, BLK21 and BLK22 including six pages. Assume that each of the six pages is a physical page indicating a set of data stored in a memory cell connected to one word line. However, the inventive concept is not limited thereto.

Referring to fig. 1, 3 and 7A, in case that information related to the sequential read mode SRM included in the sequential read information SQRI received from the memory controller 110 indicates the first sequential read mode srm_1, as shown in fig. 7A, the sequential address generator 121 may generate a plurality of sequential addresses addr_sq such that a plurality of sequential data dt_sq1 to dt_sq6 are output. For example, the first sequential read mode srm_1 may indicate an operation of reading all pages of a specific memory block (e.g., the memory block BLK11 of the first plane PL 1). In this case, the sequential address generator 121 may generate addresses corresponding to the pages PG111 to PG116 of the memory block BLK11 of the first plane PL1, respectively, as a plurality of sequential addresses addr_sq.

In detail, the sequential address generator 121 may generate an address of the first page PG111 of the memory block BLK11 as the first sequential address addr_sq1, and may output data of the first page PG111 corresponding to the first sequential address addr_sq1 as the first sequential data dt_sq1 ((1) of fig. 7A). The sequential address generator 121 may generate an address of the second page PG112 of the memory block BLK11 as a second sequential address addr_sq2, and may output data of the second page PG112 corresponding to the second sequential address addr_sq2 as second sequential data dt_sq2 ((2) of fig. 7A). Also, the sequential address generator 121 may generate addresses corresponding to the third to sixth pages PG113 to PG116 of the memory block BLK11 as third to sixth sequential addresses addr_sq3 to addr_sq6, respectively, and may output data of the third to sixth pages PG113 to PG116 corresponding to the third to sixth sequential addresses addr_sq3 to addr_sq6 as third to sixth sequential data dt_sq3 to dt_sq6 ((3) to (6) of fig. 7A).

In example embodiments, each of the first to sixth sequential data dt_sq1 to dt_sq6 may be output from a memory cell connected to at least one word line of the plurality of word lines. As an example, each of the first to sixth sequential data dt_sq1 to dt_sq6 may be output from memory cells connected to first to sixth word lines of the plurality of word lines, respectively. As another example, all of the sequential data of the first to sixth sequential data dt_sq1 to dt_sq6 may be output from memory cells connected to the same word line (e.g., the first word line).

In an example embodiment, the first to sixth sequential addresses addr_sq1 to addr_sq6 may be sequentially generated. For example, the first to sixth sequential addresses addr_sq1 to addr_sq6 may be sequential addresses sequentially generated.

In the case where the information related to the sequential read mode SRM included in the sequential read information SQRI received from the memory controller 110 indicates the second sequential read mode srm_2, as shown in fig. 7B, the sequential address generator 121 may generate a plurality of sequential addresses addr_sq such that a plurality of sequential data dt_sq1 to dt_sq3 are output. For example, the second sequential read mode srm_2 may indicate an operation of reading a specific page of a specific memory block. In detail, in the second sequential read mode srm_2, the sequential address generator 121 may generate addresses of specific pages PG113, PG114, and PG115 of a specific memory block (e.g., the memory block BLK 11) as first to third sequential addresses addr_sq1 to addr_sq3, and may output data of the pages PG113, PG114, and PG115 corresponding to the first to third sequential addresses addr_sq1 to addr_sq3 as first to third sequential data dt_sq1 to dt_sq3 ((1) to (3) of fig. 7B).

In example embodiments, each of the first to third sequential data dt_sq1 to dt_sq3 may be output from a memory cell connected to at least one selected word line of the plurality of word lines. As an example, each of the first to third sequential data dt_sq1 to dt_sq3 may be output from memory cells connected to first to third word lines of the plurality of word lines, respectively. As another example, all of the sequential data of the first to third sequential data dt_sq1 to dt_sq3 may be output from the memory cells connected to the same word line.

In an example embodiment, the first to third sequential addresses addr_sq1 to addr_sq3 may be sequentially generated. For example, the first to third sequential addresses addr_sq1 to addr_sq3 may be sequential addresses sequentially generated.

In the case where the information related to the sequential read mode SRM included in the sequential read information SQRI received from the memory controller 110 indicates the third sequential read mode srm_3, as shown in fig. 7C, the sequential address generator 121 may generate a plurality of sequential addresses addr_sq such that a plurality of sequential data dt_sq1 to dt_sq4 are output. For example, the third sequential read mode srm_3 may indicate an operation of reading a specific page (e.g., a fourth page) of each of the plurality of memory blocks. In detail, in the third sequential read mode srm_3, the sequential address generator 121 may generate addresses of the fourth pages PG114, PG214, PG124, and PG224 of the memory blocks BLK11, BLK21, BLK12, and BLK22 as the first to fourth sequential addresses addr_sq1 to addr_sq4. The data of the fourth pages PG114, PG214, PG124, and PG224, which respectively correspond to the first to fourth sequential addresses addr_sq1 to addr_sq4, can be output as the first to fourth sequential data dt_sq1 to dt_sq4 ((1) to (4) of fig. 7C).

In this case, the first to fourth sequential addresses addr_sq1 to addr_sq4 may be randomly generated.

In the case where the information related to the sequential read mode SRM included in the sequential read information SQRI received from the memory controller 110 indicates the fourth sequential read mode srm_4, as shown in fig. 7D, the sequential address generator 121 may generate a plurality of sequential addresses addr_sq such that a plurality of sequential data dt_sq1 to dt_sq4 are output. For example, the fourth sequential reading mode srm_4 may indicate an operation of reading a page predetermined by a user or any other algorithm.

In detail, in the fourth sequential read mode srm_4, the sequential address generator 121 may generate addresses of the pages PG125, PG222, PG216, and PG111 of the memory blocks BLK12, BLK22, BLK21, and BLK11 as the first to fourth sequential addresses addr_sq1 to addr_sq4. The data of the pages PG125, PG222, PG216, and PG111 corresponding to the first to fourth sequential addresses addr_sq1 to addr_sq4, respectively, may be sequentially output as the first to fourth sequential data dt_sq1 to dt_sq4 ((1) to (4) of fig. 7D).

In an example embodiment, the first to fourth sequential addresses addr_sq1 to addr_sq4 may be randomly generated. For example, the first to fourth sequential addresses addr_sq1 to addr_sq4 may be randomly generated sequential addresses.

As described above, the manner or algorithm of sequentially generating the plurality of sequential addresses or randomly generating the plurality of sequential addresses may vary depending on the sequential read mode. The above-described embodiments related to the first sequential reading mode to the fourth sequential reading mode are used to easily describe the inventive concept, and the inventive concept is not limited thereto. For example, any other sequential reading mode may be applied to the inventive concept.

Fig. 8 is a diagram for describing information on the sequential data size SDS shown in fig. 6 according to an example embodiment. For convenience of description, information about the size of sequential data (sequential data size SDS) will be described with reference to the page PG 111. Also, for convenience of description, it is assumed that the page PG111 includes 16KB of data. However, the inventive concept is not limited thereto.

Referring to fig. 1, 6 and 8, one sequential data dt_sq output corresponding to the sequential address addr_sq may be determined according to information about the sequential data size SDS included in the sequential read information SQRI. For example, in the case where the information on the sequential data size SDS included in the sequential read information SQRI is a first value (i.e., sds=1), only 4B data among the data read from the page corresponding to the sequential address addr_sq may be output as the sequential data dt_sq. Alternatively, in the case where the information on the sequential data size SDS included in the sequential read information SQRI is the second value (i.e., sds=2), only 4KB data among the data read from the page corresponding to the sequential address addr_sq may be output as the sequential data dt_sq. Alternatively, in the case where the information on the sequential data size SDS included in the sequential read information SQRI is a third value (i.e., sds=3), all data read from the page corresponding to the sequential address addr_sq (i.e., 16KB data) may be output as the sequential data dt_sq.

As described above, the size of one sequential read data may be determined according to the information about the sequential data size SDS included in the sequential read information SQRI. The above information about the size of the sequential data is an example, and the inventive concept is not limited thereto.

Fig. 9A and 9B are diagrams for describing information about the number NSD of sequential data shown in fig. 6 according to example embodiments. Referring to fig. 1, 6, 9A and 9B, information about the number of sequential data NSD included in the sequential read information SQRI received from the memory controller 110 may indicate information about the number of unit sequential data to be output from the nonvolatile memory device 120.

For example, as shown in fig. 9A, in the case where the information about the sequential read mode SRM included in the sequential read information SQRI indicates the first sequential read mode srm_1 and the information about the number of sequential data NSD is "3", the sequential address generator 121 may generate the addresses of the three pages PG111, PG112, and PG113 as the first to third sequential addresses addr_sq1 to addr_sq3. The first to third sequential data dt_sq1 to dt_sq3 may be sequentially output based on the first to third sequential addresses addr_sq1 to addr_sq3 thus generated.

In an example embodiment, referring to fig. 8 and 9A, when the sequential data size SDS information is "1" and the number of sequential data NSD is "3", the nonvolatile memory device 120 may continuously output the first to third sequential data dt_sq1 to dt_sq3. In this case, each of the first to third sequential data dt_sq1 to dt_sq3 may include 4B data.

For another example, as shown in fig. 9B, in the case where the information related to the sequential read mode SRM included in the sequential read information SQRI indicates the first sequential read mode srm_1 and the information related to the number of sequential data NSD indicates "5", the sequential address generator 121 may generate the addresses of the five pages PG111, PG112, PG113, PG114, and PG115 as the first to fifth sequential addresses addr_sq1 to addr_sq5. The first to fifth sequential data dt_sq1 to dt_sq5 may be sequentially output based on the first to fifth sequential addresses addr_sq1 to addr_sq5 thus generated.

In an example embodiment, referring to fig. 8 and 9B, when the sequential data size SDS information is "2" and the number of sequential data NSD is "5", the nonvolatile memory device 120 may continuously output the first to fifth sequential data dt_sq1 to dt_sq5. In this case, each of the first to fifth sequential data dt_sq1 to dt_sq5 may include 4KB data.

As described above, the nonvolatile memory device 120 according to the inventive concept may determine the number of sequential data to be transmitted to the memory controller 110 based on information about the number of sequential data NSD included in the sequential read information SQRI.

According to the above-described embodiments, the nonvolatile memory device 120 may generate a plurality of sequential addresses addr_sq (i.e., sequentially generated or randomly generated) based on the sequential read information SQRI, and may continuously transmit a plurality of sequential data dt_sq corresponding to the plurality of sequential addresses addr_sq to the memory controller 110. In this case, a plurality of sequential addresses addr_sq may be generated in various ways based on information related to the sequential read mode SRM, information related to the sequential data size SDS, or information related to the number of sequential data NSD included in the sequential read information SQRI. Further, since a separate page-based command or address is not required when transmitting the plurality of sequential data dt_sq, the speed of transmitting a large amount of data by the nonvolatile memory device 120 is improved.

Fig. 10 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the inventive concept. Fig. 11 is a diagram illustrating the lookup table of fig. 10 according to an example embodiment. Referring to fig. 10 and 11, the memory system 200 may include a memory controller 210 and a nonvolatile memory device 220. The nonvolatile memory device 220 may include a sequential address generator 221, a memory cell array 222, an address decoder 223, a page buffer circuit 224, an input/output circuit 225, a control logic circuit 226, and a look-up table LUT. The sequential address generator 221, the memory cell array 222, the address decoder 223, the page buffer circuit 224, the input/output circuit 225, and the control logic circuit 226 are the same as or similar to the sequential address generator 121, the memory cell array 122, the address decoder 123, the page buffer circuit 124, the input/output circuit 125, and the control logic circuit 126 described with reference to fig. 3, and thus, additional description will be omitted to avoid redundancy.

The look-up table LUT may be stored in a memory circuit (not shown). The lookup table LUT may include various information required to generate the sequential address addr_sq. For example, the sequential address generator 221 may generate the sequential address addr_sq based on the sequential read information SQRI. In this case, as described above, the sequential read information SQRI may include information related to the sequential read mode SRM, information related to the sequential data size SDS, and information related to the number of sequential data NSD. The lookup table LUT may include information associated with an address generation policy corresponding to information included in the sequential read information SQRI, a size of sequential data corresponding thereto, and various variables.

In detail, as shown in fig. 11, the lookup table LUT may include information on an address generation policy corresponding to each of the plurality of sequential read modes srm_1 to srm_n. Based on the lookup table LUT, the sequential address generator 221 may select a policy corresponding to the sequential read mode SRM of the sequential read information SQRI received from the memory controller 210, and may sequentially generate the plurality of sequential addresses addr_sq or randomly generate the plurality of sequential addresses addr_sq based on the selected policy.

In detail, the first sequential read mode srm_1 may refer to an operation mode of outputting data of first to last pages of the i-th memory block, the second sequential read mode srm_2 may refer to an operation mode of outputting data of a-th to b-th pages of the i-th memory block, and the third sequential read mode srm_3 may refer to an operation mode of outputting data of a c-th page of each memory block. In an exemplary embodiment, the nth sequential read mode srm_n may refer to an operation mode in which data of pages according to a policy customized by the memory controller 210 or a user is output. The sequential address generator 221 may sequentially generate a plurality of sequential addresses addr_sq or randomly generate a plurality of sequential addresses addr_sq based on policies corresponding to each of the above sequential read modes.

In an exemplary embodiment, the above variables (e.g., "i", "a", and "b") indicating a particular memory block or a particular page may be stored in a lookup table LUT and may be changed under the control of the memory controller 210. For example, the sequential address generator 221 may generate a plurality of sequential addresses addr_sq based on various variables stored in the lookup table LUT and the selected policy.

Fig. 12A is a flowchart illustrating an operation of the nonvolatile memory device of fig. 10 according to an example embodiment. Referring to fig. 10 and 12A, the nonvolatile memory device 220 may set a lookup table LUT by a set feature command or initializing an operation in operation S201. For example, when the memory system 200 is booted, the nonvolatile memory device 220 may be initialized under the control of the memory controller 210. In this case, the memory controller 210 may set various information required for the sequential read operation to the lookup table LUT.

Alternatively, the memory controller 210 may change or update various information stored in the lookup table LUT by a set feature command while driving the memory system 200.

After that, the nonvolatile memory device 220 may perform operations S210 to S230. Operations S210 to S230 may be similar to operations S110 to S130 of fig. 5A, and thus, detailed descriptions thereof will not be repeated here.

In operation S240, the nonvolatile memory device 220 may generate the sequential address addr_sq based on the sequential read information SQRI and the lookup table LUT. For example, based on the lookup table LUT, the sequential address generator 221 may select a policy corresponding to the sequential read mode SRM included in the sequential read information SQRI, and may generate a plurality of sequential addresses addr_sq based on the selected policy. In an exemplary embodiment, the sequential address generator 221 may determine a start point or offset of the plurality of sequential addresses addr_sq based on information about various variables included in the lookup table LUT.

After that, the nonvolatile memory device 220 may perform operations S250 and S260. Operation S250 and operation S260 may be similar to operation S150 and operation S160 of fig. 5A, and thus, their detailed descriptions will not be repeated here.

Fig. 12B is a flowchart illustrating a sequential read operation of the nonvolatile memory device of fig. 10 according to an example embodiment. Referring to fig. 10 and 12B, the nonvolatile memory device 220 may perform operations S501 to S570. Operations S501 to S540 are similar to operations S201 to S240 of fig. 12A, and thus, detailed descriptions thereof will not be repeated here.

In operation S550, the nonvolatile memory device 220 may prepare the first sequential data dt_sq1 based on the first sequential address addr_sq1. For example, the first sequential data dt_sq1 may be prepared in the page buffer circuit 224 or in the input/output circuit 225. In operation S560, the nonvolatile memory device 220 may sequentially output the first sequential data dt_sq1 without any additional read command.

In operation S570, the nonvolatile memory device 220 may determine whether all sequential data dt_sq based on the sequential read information SQRI and the lookup table LUT is transmitted.

In the case where all the sequential data dt_sq has not been transmitted to the memory controller 210 (i.e., in the case where there is sequential data dt_sq that has not been transmitted to the memory controller 210), the nonvolatile memory device 220 may repeatedly perform operations S550 and S560. For example, the nonvolatile memory device 220 may prepare the second sequential data dt_sq2 based on the second sequential address addr_sq2 in operation S550. For example, the second sequential data dt_sq2 may be prepared in the page buffer circuit 224 or in the input/output circuit 225. In operation S560, the nonvolatile memory device 220 may sequentially output the second sequential data dt_sq2 after outputting the first sequential data dt_sq1 without any additional read command.

Fig. 13 is a block diagram illustrating a memory system according to an embodiment of the inventive concept. Referring to fig. 13, a memory system 300 may include a memory controller 310 and a nonvolatile memory device 320. The non-volatile memory device 320 may include a sequential address generator 321. The memory controller 310, the nonvolatile memory device 320, and the sequential address generator 321 are the same as or similar to the memory controller 110, the nonvolatile memory device 120, and the sequential address generator 121 described with reference to fig. 1, and thus, detailed descriptions thereof will not be repeated here.

The memory controller 310 of fig. 13 may provide a suspend signal SSP to the nonvolatile memory device 320. The suspension signal SSP may be a signal for suspending the output of the plurality of sequential data dt_sq from the nonvolatile memory device 320. For example, in the case where the nonvolatile memory device 320 performs a sequential read operation, a plurality of sequential data dt_sq may be sequentially output through the data line DQx. The memory controller 310 may provide a suspension signal SSP to the nonvolatile memory device 320 to allow the nonvolatile memory device 320 to suspend the output of the plurality of sequential data dt_sq. The nonvolatile memory device 320 may suspend a sequential read operation (i.e., an operation of outputting sequential data) in response to the received suspension signal SSP.

In an exemplary embodiment, the suspension signal SSP may be provided to the nonvolatile memory device 320 through a separate signal line. Alternatively, the suspension signal SSP may be provided through the data line DQx or may be provided as a combination of signals provided through the control signal line CTRL.

Fig. 14 is a flowchart illustrating an operation of the nonvolatile memory device of fig. 13 according to an example embodiment. Referring to fig. 13 and 14, the nonvolatile memory device 320 may perform operations S310 through S360. Operations S310 to S360 are similar to operations S110 to S160 of fig. 5A or operations S210 to S260 of fig. 12A, and thus, detailed descriptions thereof will not be repeated here.

In operation S370, the nonvolatile memory device 320 may determine whether the memory controller 310 requests a suspension operation. For example, the nonvolatile memory device 320 may receive the suspension signal SSP from the memory controller 310 while outputting a plurality of sequential data dt_sq. In this case, in response to the suspend signal SSP, the nonvolatile memory device 320 may determine that the memory controller 310 requests a suspend operation.

In the case where the suspension operation is not requested (i.e., in the case where the suspension signal SSP is not received from the memory controller 310), the nonvolatile memory device 320 may determine whether all the sequential data dt_sq is transmitted in operation S380. The total sequential data dt_sq may be data output based on sequential read information. As an example, the total sequential data dt_sq may be the first to third sequential data dt_sq1 to dt_sq3 in fig. 9A or the first to fifth sequential data dt_sq1 to dt_sq5 in fig. 9B. In the case where the entire sequential data dt_sq is transmitted to the memory controller 310, the nonvolatile memory device 320 may terminate the data transmission operation in operation S390.

In the case where all the sequential data dt_sq has not been transmitted to the memory controller 310 (i.e., in the case where there is sequential data dt_sq that has not been transmitted to the memory controller 310), the nonvolatile memory device 320 performs operations S350 and S360.

In the case where the determination result of operation S370 indicates that the memory controller 310 requests a suspension operation, the nonvolatile memory device 320 performs operation S390. For example, in a case where the suspension signal SSP is received from the memory controller 310 while a plurality of sequential data dt_sq is transmitted, the nonvolatile memory device 320 may suspend an operation of transmitting the sequential data dt_sq.

In an exemplary embodiment, the nonvolatile memory device 320 may suspend the sequential data transmission operation upon receiving the suspension signal SSP from the memory controller 310. Alternatively, after completely transmitting the unit sequential data (i.e., sequential data corresponding to one address) being transmitted at the point of time when the suspension signal SSP is received from the memory controller 310, the nonvolatile memory device 320 may suspend a transmission operation with respect to the remaining sequential data.

As described above, the nonvolatile memory device 320 according to an embodiment of the inventive concept may continuously output a plurality of sequential data without a separate call or issuance of a command or address from the memory controller 310. In this case, the nonvolatile memory device 320 may suspend the sequential data transmission operation in response to the suspend signal SSP received from the memory controller 310.

Fig. 15A and 15B are block diagrams illustrating a memory system according to an embodiment of the inventive concept. Fig. 16A is a diagram illustrating information managed by the sequential address generator 411a included in the memory controller 410a of fig. 15A according to an example embodiment, and fig. 16B is a diagram illustrating information managed by the sequential data manager 411B included in the memory controller 410B of fig. 15B according to an example embodiment.

Referring to fig. 15A and 16A, a memory system 400a includes a memory controller 410a and a nonvolatile memory device 420a. The memory controller 410a may include a sequential address generator 411a, and the nonvolatile memory device 420a may include a sequential address generator 421a. The nonvolatile memory device 420a and the sequential address generator 421a are the same as the nonvolatile memory device 120 and the sequential address generator 121 described with reference to fig. 1, and thus, their detailed descriptions will not be repeated here.

The operation of the sequential address generator 411a included in the memory controller 410a may be the same as the operation of the sequential address generator 421a of the nonvolatile memory device 420a. For example, the sequential address generator 411a of the memory controller 410a may sequentially generate a plurality of sequential addresses addr_sq or randomly generate a plurality of sequential addresses addr_sq based on specific information.

The sequential address ADDR SQ generated from the sequential address generator 411a of the memory controller 410a may be used to manage data programmed to the nonvolatile memory device 420 a. For example, as shown in fig. 16A, the memory controller 410a may include address information related to the plurality of sets of data dt_1 to dt_m. In this case, each of the plurality of sets of data dt_1 to dt_m may be a large amount of data having different attributes or different kinds from each other.

For example, the sequential address generator 411a of the memory controller 410a may generate a plurality of sequential addresses addr_sq11 to addr_sq1i corresponding to an area where the first set of data dt_1 is to be stored (i.e., sequentially generated plurality of sequential addresses addr_sq11 to addr_sq1i or randomly generated plurality of sequential addresses addr_sq11 to addr_sq1i). The memory controller 410a may control the nonvolatile memory device 420a such that the first set of data dt_1 is stored to an area corresponding to the plurality of sequential addresses addr_sq11 to addr_sq1i generated thereby. For example, the memory controller 410a may provide the first set of data dt_1 and the plurality of sequential addresses addr_sq11 to addr_sq1i to the nonvolatile memory device 420 a. The nonvolatile memory device 420a may store the first set of data dt_1 to regions (or pages) corresponding to the plurality of sequential addresses addr_sq11 to addr_sq1i.

Likewise, for the second to mth sets of data dt_2 to dt_m, the memory controller 410a may generate a plurality of sequential addresses "addr_sq21 to addr_sq2k" to "addr_ SQm1 to addr_sqmj", and may control the nonvolatile memory device 420a such that the second to mth sets of data dt_2 to dt_m are stored to regions corresponding to the plurality of sequential addresses "addr_sq21 to addr_sq2k" to "addr_ SQm1 to addr_sqmj" generated thereby, respectively.

In an exemplary embodiment, the nonvolatile memory device 420a may output the first to mth sets of data dt_1 to dt_m through sequential read operations described with reference to fig. 1 to 3, 5A, 5B, 6, 7A to 7D, 8, 9A, 9B, 10, 11, 12A, 12B, 13, and 14, respectively. In an embodiment, the information shown in fig. 16A may be managed in the flash translation layer FTL described with reference to fig. 2.

Referring to fig. 15B and 16B, a memory system 400B includes a memory controller 410B and a nonvolatile memory device 420B. Memory controller 410b may include sequential data manager 411b and non-volatile memory device 420b may include sequential address generator 421b. The nonvolatile memory device 420b and the sequential address generator 421b are the same as the nonvolatile memory device 120 and the sequential address generator 121 described with reference to fig. 1, and thus, their detailed descriptions will not be repeated here.

The sequential data manager 411b of the memory controller 410b may be configured to manage sequential read information regarding a large amount of data to be stored to the non-volatile memory device 420b. For example, as shown in fig. 16B, the sequential data manager 411B may manage information about the sequential read mode SRM, information about the sequential data size SDS, information about the number of sequential data NSD, and information about the variable of each of the plurality of sets of data dt_1 to dt_m.

The memory controller 410b may store the plurality of sets of data dt_1 to dt_m to the nonvolatile memory device 420b based on the information managed by the sequential data manager 411 b. For example, to store the first set of data dt_1 to the nonvolatile memory device 420b, the memory controller 410b may provide information (e.g., srm_1, sds_1, nsd_1, and v_1) corresponding to the first set of data dt_1 as the sequential write information SQWI to the nonvolatile memory device 420b. The sequential address generator 421b of the nonvolatile memory device 420b may generate a plurality of sequential addresses addr_sq based on the sequential write information SQWI. The operation of the sequential address generator 421b is similar to that disclosed above, and thus, additional description will be omitted to avoid redundancy. The nonvolatile memory device 420b may store the first set of data dt_1 to a region (or page) corresponding to one of the plurality of sequential addresses addr_sq.

As described above, in the case where the memory controller 410a or the memory controller 410b stores a large amount of data to the nonvolatile memory device 420a or the nonvolatile memory device 420b, the memory controller 410a or the memory controller 410b may store the large amount of data to the nonvolatile memory device 420a or the nonvolatile memory device 420b by directly generating and managing a plurality of addresses for sequential read operations or by directly managing overall information (e.g., sequential read mode SRM, sequential data size SDS, number NSD of sequential data, or variable) for generating the plurality of addresses. In the case of performing a sequential read operation on a large amount of stored data, a large amount of data may be normally output from the nonvolatile memory device 420a or the nonvolatile memory device 420b.

Fig. 17 is a block diagram illustrating a Solid State Drive (SSD) system 1000 to which a nonvolatile memory device according to the inventive concept is applied. Referring to fig. 17, SSD system 1000 may include a host 1100 and an SSD 1200.

SSD 1200 may transmit signal SIG to host 1100 or receive signal from host 1100 through signal connector 1201 and be provided with power PWR through power connector 1202. SSD 1200 includes an SSD controller 1210, a plurality of non-volatile memory devices (NVM) 1221 to 122n, an auxiliary power source 1230, and a buffer memory 1240. In an example embodiment, each of the plurality of NVM 1221-122 n may be configured to perform the sequential read operations described with reference to fig. 1-3, 5A, 5B, 6, 7A-7D, 8, 9A, 9B, 10, 11, 12A, 12B, 13, 14, 15A, 15B, 16A, and 16B.

The SSD controller 1210 can control the plurality of NVM 1221 to 122n in response to a signal SIG received from the host 1100. The plurality of NVM 1221 through 122n may operate under the control of the SSD controller 1210. The auxiliary power source 1230 is connected to the host 1100 via the power connector 1202. The auxiliary power source 1230 may be charged by power PWR from the host 1100. In the case where the host 1100 does not smoothly supply the power PWR, the auxiliary power source 1230 may supply the SSD 1200 power.

According to the inventive concept, when the nonvolatile memory device outputs a plurality of sequential data, a command or address based on page/page unit is not required. In this way, since overhead due to issuing a command or address problem is reduced when a large amount of data is read, a nonvolatile memory device having improved performance, an operating method of the nonvolatile memory device, and an operating method of a memory controller controlling the nonvolatile memory device are provided.

Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A non-volatile memory device, the non-volatile memory device comprising:

a memory cell array including a plurality of memory cells connected to a plurality of word lines;

a control logic circuit configured to receive a first sequential read command and a second sequential read command subsequent to the first sequential read command from outside the nonvolatile memory device;

a sequential address generator configured to generate a plurality of sequential addresses based on sequential read information received from outside the nonvolatile memory device under control of a control logic circuit that receives the first sequential read command and the second sequential read command;

an address decoder connected to the memory cell array through the plurality of word lines and configured to sequentially select a plurality of pages in at least one word line corresponding to the plurality of sequential addresses from the plurality of word lines under control of a control logic circuit receiving a first sequential read command and a second sequential read command;

a page buffer circuit connected to the memory cell array through a plurality of bit lines and configured to prepare a plurality of sequential data from memory cells connected to a page selected by the address decoder under control of a control logic circuit receiving the first sequential read command and the second sequential read command; and

An input/output circuit configured to sequentially output the plurality of sequential data from the page buffer circuit to an outside of the nonvolatile memory device through the data line under control of the control logic circuit,

wherein the control logic is configured to: receiving a first sequential read command during a first command input interval; and receiving a second sequential read command during a second command input section subsequent to the first command input section,

wherein the sequential address generator is configured to receive sequential read information during an address input interval between the first command input interval and the second command input interval, and

wherein the input/output circuit sequentially outputs the plurality of sequential data from the selected page based on the sequential read information after the second command input section.

2. The non-volatile memory device of claim 1, wherein the input/output circuit is configured to output the plurality of sequential data continuously without receiving additional commands or addresses at the control logic circuit from outside the non-volatile memory device.

3. The non-volatile memory device of claim 1, wherein the sequential address generator is configured to: during an address input section in which a command latch enable signal from outside the nonvolatile memory device is logic low and an address latch enable signal from outside the nonvolatile memory device is logic high, sequentially read information is received through the data line in synchronization with a rising edge of a write enable signal received from outside the nonvolatile memory device.

4. The non-volatile memory device of claim 3, wherein the control logic circuit is configured to: sequential read information is received within 5 periods of the write enable signal.

5. The nonvolatile memory device according to claim 1, wherein the plurality of sequential data are continuously output in synchronization with rising and falling edges of the data strobe signal based on a read enable signal received from outside the nonvolatile memory device.

6. The non-volatile memory device of claim 1, wherein the sequential read information includes information about a sequential read mode, information about a size of each of the plurality of sequential data, and information about a number of the plurality of sequential data.

7. The non-volatile memory device of claim 6, the non-volatile memory device further comprising:

a storage circuit configured to store a lookup table including a sequential read pattern of sequential read information and corresponding information of a sequential address generation policy.

8. The non-volatile memory device of claim 7, wherein the sequential address generator is configured to: the plurality of sequential addresses are generated based on a sequential address generation policy corresponding to a sequential read mode received from an outside of the non-volatile memory device.

9. The non-volatile memory device of claim 7, wherein the lookup table is configured to be updated in response to a set feature command received from outside the non-volatile memory device.

10. The non-volatile memory device of claim 1, wherein the control logic circuit is further configured to: a pause signal received from outside the nonvolatile memory device is received while the plurality of sequential data are continuously output, and an output operation related to the plurality of sequential data is paused in response to the received pause signal.

11. A method of operating a non-volatile memory device, the method comprising:

receiving a first sequential read command from outside the non-volatile memory device through the data line during a first command input interval;

sequentially reading information from outside the nonvolatile memory device through the data line during an address input section subsequent to the first command input section;

receiving a second sequential read command from outside the nonvolatile memory device through the data line during a second command input section subsequent to the address input section; and

after the second command input section, sequentially outputting a plurality of sequential data based on the sequential read information,

Wherein the plurality of sequential data correspond to a plurality of physical pages, respectively.

12. The method of claim 11, the method further comprising:

during an address input interval, receiving a logic low command latch enable signal received from outside the non-volatile memory device, and receiving a logic high address latch enable signal received from outside the non-volatile memory device,

wherein the sequential read information is received in synchronization with a rising edge of a write enable signal received from outside the nonvolatile memory device.

13. The method of claim 11, the method further comprising:

during the first command input section and the second command input section, receiving a logic high command latch enable signal received from outside the nonvolatile memory device, and receiving a logic low address latch enable signal received from outside the nonvolatile memory device,

wherein the first sequential read command and the second sequential read command are received in synchronization with a rising edge of a write enable signal received from outside the nonvolatile memory device.

14. The method of claim 11, wherein the plurality of sequential data is continuously output to the outside of the non-volatile memory device in synchronization with a data strobe signal switching based on a read enable signal received from the outside of the non-volatile memory device.

15. The method of claim 11, wherein the non-volatile memory device does not receive additional commands or addresses from outside the non-volatile memory device until the plurality of sequential data is completely output.

16. A method of operating a memory controller that controls a non-volatile memory device comprising a plurality of pages, the method comprising:

transmitting a first sequential read command to the nonvolatile memory device through the data line during a first command input interval;

transmitting sequential read information to the nonvolatile memory device through the data line during an address input section subsequent to the first command input section;

transmitting a second sequential read command to the nonvolatile memory device through the data line during a second command input interval subsequent to the address input interval; and

after the second command input interval, a read enable signal is provided to the non-volatile memory device to continuously receive a plurality of sequential data from a selected page of the plurality of pages of the non-volatile memory device.

17. The method of claim 16, the method further comprising:

during the first command input interval and the second command input interval, a logic high command latch enable signal is sent to the non-volatile memory device, and a logic low address latch enable signal is sent to the non-volatile memory device,

Wherein the read enable signal is logic high and each of the first sequential read command and the second sequential read command is sent to the non-volatile memory device in synchronization with a rising edge of the write enable signal.

18. The method of claim 16, the method further comprising:

during an address input interval, a command latch enable signal of logic low is sent to the non-volatile memory device, and an address latch enable signal of logic high is sent to the non-volatile memory device,

wherein the read enable signal is logic high and sequential read information is sent to the non-volatile memory device in synchronization with the rising edge of the write enable signal.

19. The method of claim 16, wherein the read enable signal is provided to the non-volatile memory device after a ready/busy signal received from the non-volatile memory device transitions to a ready state.

20. The method of claim 16, wherein no additional commands or addresses are sent to the non-volatile memory device over the data lines until the plurality of sequential data is fully received from the non-volatile memory device.