CN110782840B

CN110782840B - Pixel circuit, compensation method and display panel

Info

Publication number: CN110782840B
Application number: CN201911119577.3A
Authority: CN
Inventors: 金台镇; 鲍文超
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2021-08-06
Anticipated expiration: 2039-11-15
Also published as: CN110782840A

Abstract

The invention discloses a pixel circuit, a compensation method and a display panel, wherein the pixel circuit comprises a driving module, a reading module, a sampling module, a resetting module and a light-emitting device, wherein the driving module is used for driving the light-emitting device to emit light; the reading module is used for reading the output voltage of the light-emitting device; the reset module is used for resetting the light-emitting device in a reset stage; the sampling module is used for sampling the output voltage read by the reading module for multiple times according to a preset first time sequence in a sampling stage and transmitting a plurality of sampling signals to the time sequence controller, so that the time sequence controller acquires a compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the driving module. The embodiment of the invention compensates according to the sampling signals sampled for multiple times, can reduce the noise introduced by electromagnetic interference and compensate the pixel circuit aiming at the noise, and effectively improves the display effect of the pixel circuit.

Description

Pixel circuit, compensation method and display panel

Technical Field

The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a compensation method, and a display panel.

Background

The OLED, which is a current type light emitting device, has been increasingly used in high performance display, and has many advantages of high contrast, ultra-thin, flexibility, and the like, compared to a liquid crystal display due to its self-luminous property.

Then, the threshold voltage of the OLED may shift under long-time pressurization and high temperature conditions, and the difference in display brightness may be caused by the difference in the data voltage written and the difference in the threshold shift amount of the tft driven by each portion of the OLED panel, so that the OLED panel needs to be compensated.

Disclosure of Invention

In order to solve at least one of the above problems, a first embodiment of the present invention provides a pixel circuit including a driving module, a reading module, a sampling module, a reset module, and a light emitting device, wherein

The driving module is used for driving the light-emitting device to emit light;

the reading module is used for reading the output voltage of the light-emitting device;

the reset module is used for resetting the light-emitting device in a reset stage;

the sampling module is used for sampling the output voltage read by the reading module for multiple times according to a preset first time sequence in a sampling stage and transmitting a plurality of sampling signals to the time sequence controller, so that the time sequence controller acquires a compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the driving module.

Further, the driving module comprises a first terminal, a second terminal and a third terminal, the first terminal is connected to a data voltage in response to the gate signal, the second terminal is connected to a first power voltage, and the third terminal and the anode of the light emitting device are connected to a first node;

the light-emitting device comprises an anode and a cathode, the anode and the driving module are connected to a first node, and the cathode is connected to a second power voltage;

the reading module comprises a first reading end, a second reading end and a third reading end, the first reading end and the light-emitting device are connected to a first node, the second reading end is respectively connected to a second node with the resetting module and the sampling module, and the third reading end is connected to a third power supply voltage;

the reset module comprises a reset transistor, the reset transistor comprises a reset control end, a first reset end and a second reset end, the first reset end and the reading module are connected to a second node, the second reset end is connected to a reset voltage, and the reset transistor responds to a reset signal input by the reset control end to conduct the first reset end and the second reset end;

the sampling module comprises a first sampling end, a second sampling end and a third sampling end, wherein the first sampling end and the reading module are connected to a second node, the second sampling end is connected to a third power voltage, the third sampling end is connected with the time schedule controller, and the sampling module transmits a plurality of sampling signals to the time schedule controller according to a preset first time sequence, so that the time schedule controller acquires compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the first end of the driving module.

Further, the sampling module comprises a first sampling switch, a second sampling switch, a sampling capacitor and an analog-to-digital sampling circuit, wherein,

the first sampling switch and the second sampling switch both comprise a first end and a second end, the sampling capacitor comprises a first end and a second end, the analog-digital sampling circuit comprises a first input end and a first output end, the first end of the first sampling switch and the reading module are connected to a second node, the second end of the first sampling switch and the first end of the sampling capacitor are connected to a third node, the second end of the sampling capacitor is connected to the third power voltage, the first end of the second sampling switch and the first end of the sampling capacitor are connected to the third node, the second end of the second sampling switch is connected to the first input end of the analog-digital sampling circuit, and the first output end of the analog-digital sampling circuit is connected to the timing controller;

the first sampling switch and the second sampling switch charge and sample the sampling capacitor for multiple times according to a preset first time sequence, and the second sampling switch transmits a plurality of sampling signals to the analog-digital sampling circuit respectively, outputs the sampling signals to the time schedule controller after analog-digital conversion, so that the time schedule controller obtains compensation voltage according to the sampling signals and transmits the compensation voltage to the first end of the driving module.

Furthermore, the sampling module further comprises a processor, the processor comprises a second input end and a second output end, the second input end of the processor is connected with the first output end of the analog-digital sampling circuit, and the second output end of the processor is connected with the time schedule controller;

the first sampling switch and the second sampling switch charge and sample the sampling capacitor for multiple times according to a preset second time sequence, the second sampling switch transmits a plurality of sampling signals to the analog-to-digital sampling circuit respectively, the sampling signals are transmitted to the processor after analog-to-digital conversion, the processor receives and stores the sampling signals, generates a sampling mean value signal and outputs the sampling mean value signal to the time sequence controller, and the time sequence controller obtains the compensation voltage according to the sampling mean value signal and transmits the compensation voltage to the first end of the driving module.

Further, the read module comprises a read line, a read capacitor and a read transistor, the read capacitor comprises a first terminal and a second terminal, the read transistor comprises a read control terminal, a first terminal and a second terminal, wherein

A first terminal of the readout transistor and an anode of the light emitting device are connected to the first node, a second terminal of the readout transistor and the readout line are connected to a second node, and the readout transistor turns on the first terminal and the second terminal in response to a readout signal input from the readout control terminal;

the first end of the reading capacitor and the reading line are connected to the second node, and the second end of the reading capacitor is connected to the third power supply voltage.

Further, the driving module includes a first thin film transistor, a second thin film transistor and a driving capacitor, the first thin film transistor and the second thin film transistor include a control terminal, a first terminal and a second terminal, the driving capacitor includes a first terminal and a second terminal, wherein

A first end of the first thin film transistor is connected with a data voltage, a second end of the first thin film transistor and a control end of the second thin film transistor are connected with a fourth node, and the first thin film transistor responds to a gate signal input by the control end to connect the data voltage to the fourth node;

a first end of the second thin film transistor is connected to a first power voltage, a second end of the second thin film transistor and the anode of the light emitting device are connected to a first node, and the first end and the second end of the second thin film transistor are conducted to drive the light emitting device in response to the data voltage input by the control end;

the first end of the driving capacitor and the control end of the second thin film transistor are connected to the fourth node, and the second end of the driving capacitor and the second end of the second thin film transistor are connected to the first node.

A second embodiment of the present invention provides a compensation method using the pixel circuit according to the first embodiment, including:

a preamble stage: the reset module resets the light-emitting device, the drive module drives the light-emitting device, and the reading module reads the output voltage of the light-emitting device;

a sampling stage: the sampling module samples the output voltage read by the reading module for multiple times according to a preset first time sequence and transmits a plurality of sampling signals to the time sequence controller;

a data write-back stage: the time sequence controller acquires compensation voltage according to a plurality of sampling signals and transmits the compensation voltage to the driving module, and the driving module responds to the compensation voltage to drive the light-emitting device to emit light.

Further, the driving module comprises a first terminal, a second terminal and a third terminal, the first terminal is connected to a data voltage in response to the gate signal, the second terminal is connected to a first power voltage, and the third terminal and the anode of the light emitting device are connected to a first node; the light-emitting device comprises an anode and a cathode, the anode and the driving module are connected to a first node, and the cathode is connected to a second power voltage; the reading module comprises a first reading end, a second reading end and a third reading end, the first reading end and the light-emitting device are connected to a first node, the second reading end is respectively connected to a second node with the resetting module and the sampling module, and the third reading end is connected to a third power supply voltage; the reset module comprises a reset transistor, the reset transistor comprises a reset control end, a first reset end and a second reset end, the first reset end and the reading module are connected to a second node, the second reset end is connected to a reset voltage, and the reset transistor responds to a reset signal input by the reset control end to conduct the first reset end and the second reset end; the sampling module comprises a first sampling end, a second sampling end and a third sampling end, wherein the first sampling end and the reading module are connected to a second node, the second sampling end is connected to the third power voltage, the third sampling end is connected to the time schedule controller, and the sampling module transmits a plurality of sampling signals to the time schedule controller according to a preset first time sequence, so that the time schedule controller obtains a compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the first end of the driving module;

the preamble stage comprises:

data write and reset phases: the reset module responds to a reset signal to switch in a reset voltage to a second node, the reading module responds to a reading signal to switch in the reset voltage to a first node, and the driving module responds to a grid signal to switch in a data voltage;

and (3) a stabilization stage: the driving module is used for responding to the accessed data voltage and stabilizing the voltage of the first node into a first steady-state voltage in a first steady-state time;

a reading stage: the read module reads a second steady-state voltage of the first node at a second steady-state time in response to a read signal.

Further, the sampling module comprises a first sampling switch, a second sampling switch, a sampling capacitor and an analog-digital sampling circuit, wherein the first sampling switch and the second sampling switch both comprise a first end and a second end, the sampling capacitor comprises a first end and a second end, the analog-digital sampling circuit comprises a first input end and a first output end, the first end of the first sampling switch and the reading module are connected to a second node, the second end of the first sampling switch and the first end of the sampling capacitor are connected to a third node, the second end of the sampling capacitor is connected with the third power supply voltage, the first end of the second sampling switch and the first end of the sampling capacitor are connected with a third node, the second end of the second sampling switch is connected with the first input end of the analog-digital sampling circuit, and the first output end of the analog-digital sampling circuit is connected with the time schedule controller;

the sampling stage comprises the following steps: the sampling module samples the output voltage read by the reading module a plurality of times according to a predetermined first timing and transmits a plurality of sampling signals to the timing controller further includes:

the first sampling switch and the second sampling switch charge and sample the sampling capacitor for multiple times according to a preset first time sequence so as to sample the output voltage, and the second sampling switch transmits a plurality of sampling signals to the analog-digital sampling circuit respectively and outputs the sampling signals to the time sequence controller after analog-digital conversion.

the first sampling switch and the second sampling switch charge and sample the sampling capacitor for multiple times according to a preset second time sequence so as to sample the output voltage, the second sampling switch transmits a plurality of sampling signals to the analog-to-digital sampling circuit respectively, the analog-to-digital conversion is carried out on the sampling signals, and then the sampling signals are transmitted to the processor, and the processor receives and stores the sampling signals, generates a sampling mean value signal and outputs the sampling mean value signal to the time sequence controller;

the data write-back stage: the timing controller obtains a compensation voltage according to a plurality of the sampling signals and transmits the compensation voltage to the driving module, and the driving module drives the light emitting device to emit light in response to the compensation voltage further comprises:

the time schedule controller obtains compensation voltage according to the sampling mean value signal and transmits the compensation voltage to the first end of the driving module, and the driving module responds to the compensation voltage to drive the light-emitting device to emit light.

Further, the charging and sampling times of the sampling capacitor by the first sampling switch and the second sampling switch are in a direct proportional relation with the accuracy rate of the compensation voltage;

and/or

The time interval of charging and sampling of the sampling capacitor by the first sampling switch and the second sampling switch is in inverse proportion to the accuracy rate of the compensation voltage.

Further, the reading module includes a reading line, a reading capacitor and a reading transistor, the reading capacitor includes a first terminal and a second terminal, the reading transistor includes a reading control terminal, a first terminal and a second terminal, the first terminal of the reading transistor and the anode of the light emitting device are connected to the first node, the second terminal of the reading transistor and the reading line are connected to the second node, and the reading transistor turns on the first terminal and the second terminal in response to a reading signal input by the reading control terminal; the first end of the reading capacitor and the reading line are connected to the second node, and the second end of the reading capacitor is connected to the third power supply voltage;

the driving module comprises a first thin film transistor, a second thin film transistor and a driving capacitor, the first thin film transistor and the second thin film transistor respectively comprise a control end, a first end and a second end, the driving capacitor comprises a first end and a second end, the first end of the first thin film transistor is connected with a data voltage, the second end of the first thin film transistor and the control end of the second thin film transistor are connected to a fourth node, and the first thin film transistor responds to a gate signal input by the control end and connects the data voltage to the fourth node; a first end of the second thin film transistor is connected to a first power voltage, a second end of the second thin film transistor and the anode of the light emitting device are connected to a first node, and the first end and the second end of the second thin film transistor are conducted to drive the light emitting device in response to the data voltage input by the control end; a first end of the driving capacitor and a control end of the second thin film transistor are connected to the fourth node, and a second end of the driving capacitor and a second end of the second thin film transistor are connected to the first node;

the data write and reset phases: the reset module switches a reset voltage into the second node in response to a reset signal, the read module switches the reset voltage into the first node in response to a read signal, the driving module switches a data voltage into the data voltage in response to a gate signal further comprises:

the reset transistor responds to a reset signal input by the reset control terminal to conduct a first reset terminal and a second reset terminal and switch the reset voltage into the second node;

the reading transistor responds to a reading signal input by the reading control terminal to conduct a first terminal and a second terminal and switch the reset voltage into the first node;

the first thin film transistor transmits the data voltage accessed by the first terminal to the fourth node in response to a gate signal input by a control terminal, and the second thin film transistor switches on the first terminal and the second terminal in response to the data voltage input by the control terminal;

the stabilization phase comprises the following steps: the driving module is used for stabilizing the voltage of the first node to be a first steady-state voltage in response to the accessed data voltage in a first steady-state time, and further comprises:

the driving capacitor is charged in response to the accessed data voltage at a first steady-state time, the second thin film transistor is switched from a conducting state to a closing state, and the voltage of the first node is stabilized to be a first steady-state voltage;

the reading stage: the reading module reading a second steady-state voltage of the first node at a second steady-state time in response to a read signal further comprises:

the reading transistor responds to a reading signal input by the reading control terminal to turn on a first terminal and a second terminal so as to read a first steady-state voltage of the first node;

the reading capacitor is charged at a second steady-state time in response to the first steady-state voltage being switched in, and the voltage of the first node is stabilized to be a second steady-state voltage.

A third embodiment of the present invention provides a display panel including the pixel circuit described in the first embodiment.

The invention has the following beneficial effects:

aiming at the existing problems, the invention sets a pixel circuit, a compensation method and a display panel, and compensates a light-emitting device through a sampling signal sampled for multiple times under the combined action of a driving module, a reading module, a sampling module and a resetting module, so that the noise introduced by electromagnetic interference can be reduced, the pixel circuit is compensated aiming at the noise, the display effect of the pixel circuit is effectively improved, and the pixel circuit has wide application prospect.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a block diagram showing a pixel circuit according to an embodiment of the present invention;

FIG. 2 shows a circuit diagram of a pixel circuit according to one embodiment of the invention;

FIG. 3 shows a timing diagram of a pixel circuit according to one embodiment of the invention;

fig. 4 shows a circuit diagram of a pixel circuit according to another embodiment of the invention;

FIG. 5 shows a timing diagram of a pixel circuit according to another embodiment of the invention;

6a-6b are schematic diagrams illustrating sampling time points of a sampled signal according to one embodiment of the present invention;

fig. 7 shows a flow chart of a compensation method according to an embodiment of the invention.

Detailed Description

In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.

As shown in fig. 1, an embodiment of the present invention provides a pixel circuit, including a driving module, a reading module, a sampling module, a resetting module, and a light emitting device, wherein the driving module is configured to drive the light emitting device to emit light; the reading module is used for reading the output voltage of the light-emitting device; the reset module is used for resetting the light-emitting device in a reset stage; the sampling module is used for sampling the output voltage read by the reading module for multiple times according to a preset first time sequence in a sampling stage and transmitting a plurality of sampling signals to the time sequence controller, so that the time sequence controller acquires a compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the driving module.

In this embodiment, as shown in fig. 1, the driving module includes a first terminal 1, a second terminal 2, and a third terminal 3, the first terminal 1 is connected to a data voltage Vdata in response to a gate signal, the second terminal 2 is connected to a first power voltage Vdd, and the third terminal 3 and the anode of the light emitting device are connected to a first node N1 to drive the light emitting device; the light-emitting device comprises an anode and a cathode, the anode and the driving module are connected to a first node N1, and the cathode is connected to a second power supply voltage Vss; the reading module comprises a first reading terminal 1, a second reading terminal 2 and a third reading terminal 3, the first reading terminal 1 and the light emitting device are connected to a first node N1, the second reading terminal 2 is respectively connected to the reset module and the sampling module to a second node N2, and the third reading terminal 3 is connected to a third power supply voltage Gnd; the reset module comprises a reset transistor, the reset transistor comprises a reset control terminal, a first reset terminal 1 and a second reset terminal 2, wherein the first reset terminal 1 and the read module are connected to a second node N2, the second reset terminal 2 is connected to a reset voltage Vrst, and the reset transistor responds to a reset signal RST input by the reset control terminal to turn on the first reset terminal 1 and the second reset terminal 2; the sampling module comprises a first sampling end 1, a second sampling end 2 and a third sampling end 3, wherein the first sampling end 1 and the reading module are connected to a second node N2, the second sampling end 2 is connected to the third power supply voltage Gnd, the third sampling end 3 is connected to a timing controller, and the sampling module transmits a plurality of sampling signals to the timing controller according to a predetermined first timing sequence, so that the timing controller acquires a compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the first end of the driving module.

In a specific example, as shown in fig. 2, the driving module includes a first thin film transistor T1, a second thin film transistor T2, and a driving capacitor Cst, the first thin film transistor T1 and the second thin film transistor T2 each include a control terminal, a first terminal, and a second terminal, and the driving capacitor Cst includes a first terminal and a second terminal. Wherein:

a first terminal of the first thin film transistor T1 is connected to a data voltage Vdata, a second terminal of the first thin film transistor T1 and a control terminal of the second thin film transistor T2 are connected to a fourth node N4, and the first thin film transistor T1 connects the data voltage Vdata to the fourth node N4 in response to a gate signal input from the control terminal.

The second thin film transistor T2 is a driving transistor of a light emitting device, a first terminal of the second thin film transistor T2 is connected to a first power voltage Vdd, a second terminal of the second thin film transistor T2 and an anode of the light emitting device are connected to a first node N1, and the second thin film transistor T2 turns on the first terminal and the second terminal thereof to drive the light emitting device in response to the data voltage Vdata input from a control terminal.

The first terminal of the driving capacitor Cst and the control terminal of the second thin film transistor T2 are connected to the fourth node N4, and the second terminal of the driving capacitor Cst and the second terminal of the second thin film transistor T2 are connected to the first node N1.

It should be noted that the driving module in this embodiment adopts the 2T1C mode, which is only used for explaining the technical solution of this application, and those skilled in the art should understand that the driving module in the modes such as 6T1C, 7T1C, etc. may also implement the technical solution of this application, which are all within the protection scope of this application and are not described herein again.

In this embodiment, the light emitting device includes a positive electrode and a negative electrode, the positive electrode and the driving module are connected to the first node N1, and the negative electrode is connected to the second power voltage Vss. The driving module drives the light emitting device to work in a 2T1C mode.

To compensate for the threshold voltage drift of the light emitting device under long time pressurization and high temperature conditions, similarly to the driving module using the 2T1C mode, exemplarily, as shown in fig. 2, the reading module in the present embodiment includes a reading Line sequence, a reading capacitance csref including a first terminal and a second terminal, and a reading transistor T3, the reading transistor T3 including a reading control terminal, a first terminal, and a second terminal, wherein:

a first terminal of the read transistor T3 and the anode of the light emitting device are connected to the first node N1, a second terminal of the read transistor T3 and the read Line sequence Line are connected to a second node N2, and the read transistor T3 turns on the first and second terminals in response to a read signal G2 input from the read control terminal.

A first terminal of the read capacitor csref and the read Line sequence Line are connected to the second node N2, and a second terminal of the read capacitor csref is connected to the third power supply voltage Gnd.

Meanwhile, in order to more accurately read the output voltage of the light emitting device, namely, the voltage applied to the anode of the light emitting device, the reading module is further connected with a reset module and a sampling module respectively. In this embodiment, as shown in fig. 2, the reset module includes a reset transistor T4, the reset transistor T4 includes a reset control terminal, a first reset terminal and a second reset terminal, wherein the first reset terminal and the read module are connected to the second node N2, the second reset terminal is connected to a reset voltage Vrst, and the reset transistor T4 turns on the first reset terminal and the second reset terminal in response to a reset signal RST input from the reset control terminal.

In this embodiment, the sampling module specifically includes a first sampling switch SW1, a second sampling switch SW2, a sampling capacitor Csmp, and an analog-to-digital sampling circuit ADC, where:

the first sampling switch SW1 and the second sampling switch SW2 both include a first terminal and a second terminal, the sampling capacitor Csmp includes a first terminal and a second terminal, the analog-to-digital sampling circuit ADC includes a first input terminal and a first output terminal, the first terminal of the first sampling switch SW1 and the reading module are connected to a second node N2, the second terminal of the first sampling switch SW1 and the first terminal of the sampling capacitor Csmp are connected to a third node N3, the second terminal of the sampling capacitor Csmp is connected to a third power supply voltage Gnd, the first terminal of the second sampling switch SW2 and the first terminal of the sampling capacitor Csmp are connected to a third node N3, the second terminal of the second sampling switch SW2 is connected to the first input terminal of the analog-to-digital sampling circuit ADC, and the first output terminal of the analog-to-digital sampling circuit ADC is connected to the timing controller TCON; the first and second sampling switches SW1 and SW2 charge and sample the sampling capacitor Csmp multiple times according to a predetermined first timing to obtain the output voltage of the light emitting device, and the second sampling switch SW2 transmits a plurality of sampling signals to the analog-to-digital sampling circuit ADC, converts the analog signals into digital signals, and outputs the digital signals to the timing controller TCON, so that the timing controller TCON obtains a compensation voltage according to the sampling signals and transmits the compensation voltage to a first end of the first thin film transistor T1 of the driving module.

As shown in fig. 2 and fig. 3, the specific steps are as follows:

a preamble stage: the reset module resets the light emitting device, the drive module drives the light emitting device, and the reading module reads the output voltage of the light emitting device.

The preamble stage specifically includes:

data write and reset phase t 1: the reset module responds to a reset signal to switch in a reset voltage to the second node, the reading module responds to a reading signal to switch in the reset voltage to the first node, and the driving module responds to a grid signal to switch in a data voltage.

In the present embodiment, stage t 1:

g1 is active high, the first thin film transistor T1 transmits the first-end-coupled data voltage Vdata to the fourth node N4 in response to a gate signal G1 input from a control terminal.

RST is active high, the reset transistor T4 turns on the first and second reset terminals to switch the reset voltage Vrst to the second node N2 in response to a reset signal RST input from the reset control terminal.

G2 is active high, the read transistor T3 turns on the first and second terminals to switch the reset voltage Vrst into the first node N1 in response to a read signal G2 input from the read control terminal.

The second thin film transistor T2 responds to the data voltage Vdata input from the control terminal and the reset voltage Vrst of the first node N1, and then the turn-on voltage Vgs of the second thin film transistor T2 is Vdata-Vrst > Vth, and the second thin film transistor T2 is turned on.

Stabilization phase t 2: the driving module is used for responding to the accessed data voltage and stabilizing the voltage of the first node into a first steady-state voltage in a first steady-state time;

in the present embodiment, stage t 2:

g1 deactivated, T1 turned off; g2 deactivated, T3 turned off; RST is inactive and T4 is turned off.

The driving capacitor Cst is charged at a first steady state time T2 in response to the accessed data voltage Vdata, the voltage of the first node N1 is continuously raised from 0, when the voltage of the first node N1 is raised to Vdata-Vth, the second thin film transistor T2 is switched from on to off, and the voltage of the first node is stabilized to the first steady state voltage Vdata-Vth.

Read phase t 3: the read module reads a second steady-state voltage of the first node at a second steady-state time in response to a read signal.

In the present embodiment, stage t 3:

g2 is active high, the read transistor T3 turns on the first and second terminals to read the first steady-state voltage Vdata-Vth of the first node in response to the read signal G2 inputted from the read control terminal.

The read capacitor csref is charged at a second steady-state time t3 in response to the first steady-state voltage Vdata-Vth being applied, and the voltage of the first node N1 is stabilized as a second steady-state voltage, i.e., an output voltage of the light emitting device.

Sampling phase t 4: the sampling module samples the output voltage read by the reading module for multiple times according to a preset first time sequence and transmits a plurality of sampling signals to the time sequence controller.

In the present embodiment, stage t 4:

the first sampling switch SW1 and the second sampling switch SW2 charge and sample the sampling capacitor Csmp for multiple times according to a predetermined first timing to sample the output voltage of the light emitting device, and the second sampling switch SW2 transmits a plurality of sampling signals to the analog-to-digital sampling circuit ADC respectively, performs analog-to-digital conversion, and outputs the sampling signals to the timing controller TCON.

Specifically, the first sampling switch SW1 is controlled to be closed, the sampling capacitor Csmp is charged, then the second sampling switch SW2 is controlled to be closed, the sampling signal of the voltage of the first node is transmitted to the analog-to-digital sampling circuit ADC, and the analog-to-digital sampling circuit ADC performs analog-to-digital conversion on the sampling signal and outputs the digital sampling signal of the current sampling to the timing controller TCON.

In order to reduce noise interference introduced by electromagnetic interference in the compensation circuit, the noise interference of the sampling signal is reduced by sampling for multiple times. Specifically, the method comprises the following steps: considering that the second sampling switch SW2 is closed and then influenced by the resistance in the circuit, the charge will slightly drop, so after the second sampling switch SW2 is closed for sampling, the first sampling switch SW1 is controlled to be closed again to charge the sampling capacitor Csmp, then the second sampling switch SW2 is controlled to be closed for sampling, and the sampled signal obtained by sampling is output to the timing controller TCON through the analog-to-digital sampling circuit ADC to realize sampling.

The above steps are cyclically repeated, the sampling capacitor Csmp is charged and sampled a plurality of times by controlling the timings of the first and second sampling switches SW1 and SW2, and is respectively output to the timing controller TCON.

Data write back stage t 5: the time sequence controller acquires compensation voltage according to a plurality of sampling signals and transmits the compensation voltage to the driving module, and the driving module responds to the compensation voltage to drive the light-emitting device to emit light.

In the present embodiment, stage t 5:

specifically, for example, in an ideal state, data output by the analog-to-digital sampling circuit ADC in the pixel circuit is ADC _ real ═ 500, and due to noise caused by electromagnetic interference in the circuit, the sampling value is respectively obtained by 5 times in this embodiment: the timing controller receives the sampling values, and performs average filtering processing on the data to obtain ADC (ADC1+ ADC2+ ADC3+ ADC4+ ADC 5)/5-502, so that the present embodiment can effectively reduce the influence of noise interference on the sampling signal by sampling for multiple times and obtaining the sampling average value, thereby improving the compensation effect.

In an optional embodiment, the first sampling switch and the second sampling switch charge the sampling capacitor and sample the sampling capacitor for a number of times proportional to the accuracy of the compensation voltage.

In this embodiment, when the first sampling switch and the second sampling switch charge and sample the sampling capacitor more times, the higher the accuracy of the compensation voltage is, the smaller the noise interference caused by the electromagnetic interference is.

In another alternative embodiment, the time interval between the charging and sampling of the sampling capacitor by the first and second sampling switches is inversely proportional to the accuracy of the compensation voltage.

In this embodiment, when the time interval between the charging and the sampling of the sampling capacitor by the first sampling switch and the second sampling switch is longer, the longer the sampling period is, the longer the time for acquiring the compensation voltage is, and the lower the accuracy of the compensation voltage is.

It should be noted that, those skilled in the art should set the sampling times and the sampling time intervals according to the actual application requirements to satisfy the compensation of the pixel circuit as the design criteria, and details are not repeated herein.

At stage t 5:

g1 is active high, the first TFT T1 transmits the compensation voltage Vdata connected to the first terminal to the fourth node N4 in response to the gate signal G1 inputted from the control terminal.

The second thin film transistor T2 responds to the compensation voltage Vdata input by the control terminal and the reset voltage Vrst of the first node N1, then the turn-on voltage Vgs of the second thin film transistor T2 is Vdata-Vrst > Vth, and the second thin film transistor T2 is turned on to drive the light emitting device to emit light.

Therefore, the compensation of the pixel circuits is completed, and the embodiment can effectively improve the uniformity of light emission of each pixel circuit and improve the display effect.

Considering that the sampling module needs to transmit the sampling signal to the time sequence controller after sampling each time, the time sequence controller calculates and obtains the compensation voltage according to the digital sampling signal obtained by sampling for many times, which easily causes the overlong compensation time and influences the display of the light-emitting device.

In an alternative embodiment, as shown in fig. 4, the sampling module further includes a processor, the processor includes a second input terminal and a second output terminal, the second input terminal of the processor is connected to the first output terminal of the analog-to-digital sampling circuit, and the second output terminal of the processor is connected to the timing controller; the first sampling switch and the second sampling switch charge and sample the sampling capacitor for multiple times according to a preset second time sequence, the second sampling switch transmits a plurality of sampling signals to the analog-to-digital sampling circuit respectively, the sampling signals are transmitted to the processor after analog-to-digital conversion, the processor receives and stores the sampling signals, generates a sampling mean value signal and outputs the sampling mean value signal to the time sequence controller, and the time sequence controller obtains the compensation voltage according to the sampling mean value signal and transmits the compensation voltage to the first end of the driving module.

In a specific example, as shown in fig. 4 and 5, on the basis of the foregoing embodiment, a processor ALU is added in the sampling module, after the sampling signal obtained by each sampling is converted into a digital sampling signal by an analog-to-digital conversion circuit ADC, the processor performs data processing on a plurality of digital sampling signals to obtain a sampling average signal, and transmits the sampling average signal to the timing controller TCON, and the timing controller TCON obtains the compensation voltage according to the sampling average signal and transmits the compensation voltage to the first end of the first thin film transistor of the driving module, so as to further realize fast compensation for the pixel circuits on the basis of compensating the pixel circuits and improving the light emitting uniformity of the light emitting devices of the pixel circuits.

Specifically, as shown in fig. 5, in the present embodiment,

the sampling phase t 4: the first sampling switch SW1 and the second sampling switch SW2 charge and sample the sampling capacitor Csmp for multiple times according to a predetermined second time sequence, the second sampling switch SW2 transmits a plurality of sampling signals to the analog-to-digital sampling circuit ADC, and transmits the sampling signals to the controller ALU after analog-to-digital conversion, and the processor ALU receives and stores the sampling signals, generates a sampling average signal, and outputs the sampling average signal to the time sequence controller TCON. As can be seen from comparison of fig. 3, the time interval between the sampling by the first sampling switch SW1 and the sampling by the second sampling switch SW2 in the second timing is significantly reduced, so that fast sampling is realized.

The data write-back stage t 5: and the time sequence controller TCON acquires compensation voltage according to the sampling mean value signal and transmits the compensation voltage to the first end of the first thin film transistor of the driving module, and the driving module responds to the compensation voltage to drive the light-emitting device to emit light.

As shown in fig. 6a and 6 b:

in fig. 6a, the sampling module directly transmits a plurality of sampling signals to the timing controller, the timing controller performs average filtering on each sampling signal, and calculates the compensation voltage according to each sampling signal, so that the sampling period is long and the time consumption is too long.

In fig. 6b, the sampling module stores and processes data through the controller added inside, transmits the processed sampling mean value signal to the timing controller, has a short sampling period, and can reduce the influence of noise interference when sampling points fall at different positions of an actual signal, and can quickly acquire compensation voltage on the basis of acquiring a relatively accurate sampling signal.

Corresponding to the pixel circuits provided in the above embodiments, an embodiment of the present application further provides a compensation method using the above pixel circuit, and since the compensation method provided in the embodiment of the present application corresponds to the pixel circuits provided in the above embodiments, the foregoing embodiments are also applicable to the compensation method provided in this embodiment, and detailed description is omitted in this embodiment.

As shown in fig. 7, an embodiment of the present application further provides a compensation method using the pixel circuit, including: a preamble stage: the reset module resets the light-emitting device, the drive module drives the light-emitting device, and the reading module reads the output voltage of the light-emitting device; a sampling stage: the sampling module samples the output voltage read by the reading module for multiple times according to a preset first time sequence and transmits a plurality of sampling signals to the time sequence controller; a data write-back stage: the time sequence controller acquires compensation voltage according to a plurality of sampling signals and transmits the compensation voltage to the driving module, and the driving module responds to the compensation voltage to drive the light-emitting device to emit light.

In an alternative embodiment, the driving module includes a first terminal connected to a data voltage in response to a gate signal, a second terminal connected to a first power voltage, and a third terminal connected to the anode of the light emitting device at a first node; the light-emitting device comprises an anode and a cathode, the anode and the driving module are connected to a first node, and the cathode is connected to a second power voltage; the reading module comprises a first reading end, a second reading end and a third reading end, the first reading end and the light-emitting device are connected to a first node, the second reading end is respectively connected to a second node with the resetting module and the sampling module, and the third reading end is connected to a third power supply voltage; the reset module comprises a reset transistor, the reset transistor comprises a reset control end, a first reset end and a second reset end, the first reset end and the reading module are connected to a second node, the second reset end is connected to a reset voltage, and the reset transistor responds to a reset signal input by the reset control end to conduct the first reset end and the second reset end; the sampling module comprises a first sampling end, a second sampling end and a third sampling end, wherein the first sampling end and the reading module are connected to a second node, the second sampling end is connected to the third power voltage, the third sampling end is connected to the time schedule controller, and the sampling module transmits a plurality of sampling signals to the time schedule controller according to a preset first time sequence, so that the time schedule controller obtains a compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the first end of the driving module; the preamble stage comprises: data write and reset phases: the reset module responds to a reset signal to switch in a reset voltage to a second node, the reading module responds to a reading signal to switch in the reset voltage to a first node, and the driving module responds to a grid signal to switch in a data voltage; and (3) a stabilization stage: the driving module is used for responding to the accessed data voltage and stabilizing the voltage of the first node into a first steady-state voltage in a first steady-state time; a reading stage: the read module reads a second steady-state voltage of the first node at a second steady-state time in response to a read signal.

In an alternative embodiment, the sampling module includes a first sampling switch, a second sampling switch, a sampling capacitor, and an analog-to-digital sampling circuit, wherein the first sampling switch and the second sampling switch both comprise a first end and a second end, the sampling capacitor comprises a first end and a second end, the analog-digital sampling circuit comprises a first input end and a first output end, the first end of the first sampling switch and the reading module are connected to a second node, the second end of the first sampling switch and the first end of the sampling capacitor are connected to a third node, the second end of the sampling capacitor is connected with the third power supply voltage, the first end of the second sampling switch and the first end of the sampling capacitor are connected with a third node, the second end of the second sampling switch is connected with the first input end of the analog-digital sampling circuit, and the first output end of the analog-digital sampling circuit is connected with the time schedule controller; the sampling stage comprises the following steps: the sampling module samples the output voltage read by the reading module a plurality of times according to a predetermined first timing and transmits a plurality of sampling signals to the timing controller further includes: the first sampling switch and the second sampling switch charge and sample the sampling capacitor for multiple times according to a preset first time sequence so as to sample the output voltage, and the second sampling switch transmits a plurality of sampling signals to the analog-digital sampling circuit respectively and outputs the sampling signals to the time sequence controller after analog-digital conversion.

In an optional embodiment, the sampling module further comprises a processor, the processor comprises a second input terminal and a second output terminal, the second input terminal of the processor is connected to the first output terminal of the analog-to-digital sampling circuit, and the second output terminal of the processor is connected to the timing controller; the sampling stage comprises the following steps: the sampling module samples the output voltage read by the reading module a plurality of times according to a predetermined first timing and transmits a plurality of sampling signals to the timing controller further includes: the first sampling switch and the second sampling switch charge and sample the sampling capacitor for multiple times according to a preset second time sequence so as to sample the output voltage, the second sampling switch transmits a plurality of sampling signals to the analog-to-digital sampling circuit respectively, the analog-to-digital conversion is carried out on the sampling signals, and then the sampling signals are transmitted to the processor, and the processor receives and stores the sampling signals, generates a sampling mean value signal and outputs the sampling mean value signal to the time sequence controller; the data write-back stage: the timing controller obtains a compensation voltage according to a plurality of the sampling signals and transmits the compensation voltage to the driving module, and the driving module drives the light emitting device to emit light in response to the compensation voltage further comprises: the time schedule controller obtains compensation voltage according to the sampling mean value signal and transmits the compensation voltage to the first end of the driving module, and the driving module responds to the compensation voltage to drive the light-emitting device to emit light.

On the basis of the above embodiments, in an optional embodiment, the reading module includes a reading line, a reading capacitor and a reading transistor, the reading capacitor includes a first terminal and a second terminal, the reading transistor includes a reading control terminal, a first terminal and a second terminal, wherein the first terminal of the reading transistor and the anode of the light emitting device are connected to the first node, the second terminal of the reading transistor and the reading line are connected to the second node, and the reading transistor turns on the first terminal and the second terminal in response to a reading signal input by the reading control terminal; the first end of the reading capacitor and the reading line are connected to the second node, and the second end of the reading capacitor is connected to the third power supply voltage; the driving module comprises a first thin film transistor, a second thin film transistor and a driving capacitor, the first thin film transistor and the second thin film transistor respectively comprise a control end, a first end and a second end, the driving capacitor comprises a first end and a second end, the first end of the first thin film transistor is connected with a data voltage, the second end of the first thin film transistor and the control end of the second thin film transistor are connected to a fourth node, and the first thin film transistor responds to a gate signal input by the control end and connects the data voltage to the fourth node; a first end of the second thin film transistor is connected to a first power voltage, a second end of the second thin film transistor and the anode of the light emitting device are connected to a first node, and the first end and the second end of the second thin film transistor are conducted to drive the light emitting device in response to the data voltage input by the control end; a first end of the driving capacitor and a control end of the second thin film transistor are connected to the fourth node, and a second end of the driving capacitor and a second end of the second thin film transistor are connected to the first node; the data write and reset phases: the reset module switches a reset voltage into the second node in response to a reset signal, the read module switches the reset voltage into the first node in response to a read signal, the driving module switches a data voltage into the data voltage in response to a gate signal further comprises: the reset transistor responds to a reset signal input by the reset control terminal to conduct a first reset terminal and a second reset terminal and switch the reset voltage into the second node; the reading transistor responds to a reading signal input by the reading control terminal to conduct a first terminal and a second terminal and switch the reset voltage into the first node; the first thin film transistor transmits the data voltage accessed by the first terminal to the fourth node in response to a gate signal input by a control terminal, and the second thin film transistor switches on the first terminal and the second terminal in response to the data voltage input by the control terminal; the stabilization phase comprises the following steps: the driving module is used for stabilizing the voltage of the first node to be a first steady-state voltage in response to the accessed data voltage in a first steady-state time, and further comprises: the driving capacitor is charged in response to the accessed data voltage at a first steady-state time, the second thin film transistor is switched from a conducting state to a closing state, and the voltage of the first node is stabilized to be a first steady-state voltage; the reading stage: the reading module reading a second steady-state voltage of the first node at a second steady-state time in response to a read signal further comprises: the reading transistor responds to a reading signal input by the reading control terminal to turn on a first terminal and a second terminal so as to read a first steady-state voltage of the first node; the reading capacitor is charged at a second steady-state time in response to the first steady-state voltage being switched in, and the voltage of the first node is stabilized to be a second steady-state voltage.

On the basis of the pixel circuit, an embodiment of the present application further provides a display panel including the pixel circuit. Since the display panel comprises the pixel circuit, the compensation effect similar to that of the pixel circuit can be realized, namely the display uniformity of the display panel is effectively improved.

Another embodiment of the present application further provides a display device, where the display device includes the above display panel, and the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims

1. A pixel circuit is characterized by comprising a driving module, a reading module, a sampling module, a resetting module and a light-emitting device, wherein

The driving module is used for driving the light-emitting device to emit light and comprises a first end, a second end and a third end, the first end is connected with a data voltage in response to a grid signal, the second end is connected with a first power voltage, and the third end and the anode of the light-emitting device are connected to a first node;

the reading module is used for reading the output voltage of the light-emitting device and comprises a first reading end, a second reading end and a third reading end, the first reading end and the light-emitting device are connected to a first node, the second reading end is respectively connected with the reset module and the sampling module to a second node, and the third reading end is connected to a third power supply voltage;

the reset module is used for resetting the light-emitting device in a reset stage and comprises a reset transistor, wherein the reset transistor comprises a reset control terminal, a first reset terminal and a second reset terminal, the first reset terminal and the reading module are connected to a second node, the second reset terminal is connected to a reset voltage, and the reset transistor responds to a reset signal input by the reset control terminal to conduct the first reset terminal and the second reset terminal;

the sampling module is used for sampling the output voltage read by the reading module for multiple times according to a preset first time sequence in a sampling stage and transmitting a plurality of sampling signals to the time sequence controller, so that the time sequence controller obtains a compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the driving module, and the sampling module comprises a first sampling end, a second sampling end and a third sampling end, wherein the first sampling end and the reading module are connected to a second node, the second sampling end is connected to the third power voltage, the third sampling end is connected to the time sequence controller, the sampling module transmits the plurality of sampling signals to the time sequence controller according to the preset first time sequence, and the time sequence controller obtains the compensation voltage according to the plurality of sampling signals and transmits the compensation voltage to the first end of the driving module;

the sampling module comprises a first sampling switch, a second sampling switch, a sampling capacitor and an analog-digital sampling circuit, wherein,

2. The pixel circuit according to claim 1, wherein the sampling module further comprises a processor, the processor comprising a second input terminal and a second output terminal, the second input terminal of the processor being connected to the first output terminal of the analog-to-digital sampling circuit, the second output terminal of the processor being connected to the timing controller;

3. The pixel circuit according to claim 1 or 2, wherein the read block comprises a read line, a read capacitor and a read transistor, the read capacitor comprises a first terminal and a second terminal, the read transistor comprises a read control terminal, a first terminal and a second terminal, wherein

4. The pixel circuit according to claim 3, wherein the driving module comprises a first thin film transistor, a second thin film transistor, and a driving capacitor, the first thin film transistor and the second thin film transistor each comprise a control terminal, a first terminal, and a second terminal, and the driving capacitor comprises a first terminal and a second terminal, wherein

5. A compensation method using the pixel circuit of claim 1, comprising:

a preamble stage: the reset module resets the light emitting device, the driving module drives the light emitting device, and the reading module reads the output voltage of the light emitting device, including:

a reading stage: the reading module reads a second steady-state voltage of the first node at a second steady-state time in response to a reading signal;

a sampling stage: the sampling module samples the output voltage read by the reading module for a plurality of times according to a predetermined first timing and transmits a plurality of sampling signals to the timing controller, further comprising:

the first sampling switch and the second sampling switch charge and sample the sampling capacitor for multiple times according to a preset first time sequence so as to sample the output voltage, and the second sampling switch transmits a plurality of sampling signals to the analog-to-digital sampling circuit respectively and outputs the sampling signals to the time sequence controller after analog-to-digital conversion;

6. The compensation method of claim 5, wherein the sampling module further comprises a processor, the processor comprising a second input terminal and a second output terminal, the second input terminal of the processor being connected to the first output terminal of the analog-to-digital sampling circuit, the second output terminal of the processor being connected to the timing controller;

7. The compensation method of claim 6,

the charging and sampling times of the sampling capacitor by the first sampling switch and the second sampling switch are in direct proportion to the accuracy rate of the compensation voltage;

and/or

8. The compensation method of claim 7,

the reading module comprises a reading line, a reading capacitor and a reading transistor, wherein the reading capacitor comprises a first end and a second end, the reading transistor comprises a reading control end, a first end and a second end, the first end of the reading transistor and the anode of the light-emitting device are connected to the first node, the second end of the reading transistor and the reading line are connected to the second node, and the reading transistor responds to a reading signal input by the reading control end to conduct the first end and the second end; the first end of the reading capacitor and the reading line are connected to the second node, and the second end of the reading capacitor is connected to the third power supply voltage;

9. A display panel comprising the pixel circuit according to any one of claims 1 to 4.