CN110781116A

CN110781116A - High speed point-to-point serial interface system

Info

Publication number: CN110781116A
Application number: CN201911121316.5A
Authority: CN
Inventors: 李洁
Original assignee: Guangzhou Jian Fei Communication Co Ltd
Current assignee: Guangzhou Jian Fei Communication Co Ltd
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2020-02-11

Abstract

The invention discloses a high-speed point-to-point serial interface system, which comprises: the sending module, the medium access control module and the physical layer module provide a higher-speed serial interface, and use a frame serial data link, an embedded clock and alignment characters, so that the number of wires among devices is reduced, the wire matching requirement is reduced, the problem of time sequence constraint establishment and maintenance is effectively eliminated, and the implementation of a high-speed converter data interface is simplified.

Description

High speed point-to-point serial interface system

Technical Field

The invention relates to the field of protocol standards of converters, in particular to a high-speed point-to-point serial interface system.

Background

A serial data link was defined in the past as a single serial channel between one or more converters and a receiver, wherein the physical interface between the converter and the receiver, and the interface is comprised of a differential pair employing a current mode logic driver and a receiver, wherein the link is a serial data link between the converter and the receiver, and the frame clock is routed to both the converter and the receiver, and provides a clock for the link between the devices, the link is encoded with 8b/10b, using an embedded clock, so that no additional clock lines need to be routed, and the associated complexity of aligning the data transmitted at high data rates with additional clock signals, it is therefore becoming appreciated that the standard needs to be modified to support multiple, aligned serial channels under multiple converters to meet the increasing speed and resolution of the converters.

However, the current technology still lacks a key factor, and the missing factor is the determined delay of serial data on the link. For a Converter, when a signal is received, if the Analog domain sampled signal is To be reconstructed correctly, it is critical To know the timing relationship between the sampled signal and its Digital representation, and although this is the case for an Analog-To-Digital Converter (hereinafter ADC), the case for a Digital-To-Analog Converter (hereinafter DAC) is similar, the timing relationship is affected by the delay of the Converter, which is defined for the ADC as the number of clock cycles in the period from the moment of the input signal sampling edge until the Converter outputs the Digital. Similarly, for a DAC, delay is defined as the number of clock cycles in the period of time from the time a digital signal is input to the DAC until the analog output begins to transition, whereas past techniques have not defined the ability to deterministically set the converter delay and serial digital input/output, and when its frame clock is an absolute time reference, the frame clock and converter sample clock are typically the same, which is not flexible enough and when this same signal is to be routed to multiple devices and the skew between different routing paths is counted, unnecessary complexity is introduced to the system design.

Disclosure of Invention

The technical problem to be solved by the present invention is to overcome the above-mentioned drawbacks of the prior art by providing a mechanism for ensuring a high-speed point-to-point serial interface system with high reproducibility between two power-up cycles and link resynchronization.

The technical scheme adopted by the invention for solving the technical problems is as follows: constructing a high speed point-to-point serial interface system comprising: the device comprises a medium access control module, a data processing module and a data processing module, wherein the medium access control module comprises a link layer, a register module, a scrambler and a delay phase-locked loop module of a multi-frame counter, and receives first data through the register module; a plurality of sending modules, electrically connected to the medium access control module, wherein the sending modules include a sending state register module, a sending control module, a sending scrambling module and a data link layer, and receive one or more sampling point data streams of the first data, and convert the sampling point data streams into one or more serial streams to generate second data; and the physical layer module is electrically connected with the plurality of sending modules, comprises an encoder, a word aligner, a physical coding sublayer of the serializer and a physical medium adaptation layer module of the serializer, receives the second data and outputs the second data to the digital-to-analog conversion module.

In the system of the present invention, the sending state registering module is a management configuration state registering module.

In the system of the present invention, the transmission controller is a state machine that manages synchronization signals and controls the state of the data link layer, a local multi-frame clock, and a deterministic delay of the entire link.

In the system of the present invention, wherein the transmission scrambler and the data link layer implement an initial channel alignment sequence with 32-bit data, and perform scrambling, channel insertion, and frame alignment of characters.

In the system of the present invention, the data link layer includes code group synchronization, initial channel synchronization, and user data phase, and establishes a synchronization link according to the code group synchronization, the initial channel synchronization, and the user data phase.

The high-speed point-to-point serial interface system has the following beneficial effects: a higher speed serial interface is provided, up to 12.5 Gbps/channel, using a frame serial data link and an embedded clock and alignment characters. The method reduces the number of wires among devices, reduces the wire matching requirement, and eliminates the problem of establishing and maintaining time sequence constraint, thereby simplifying the implementation of a data interface of a high-speed converter, reducing the number of digital input and output channels among the high-speed data converter, a Field Programmable Gate Array (FPGA) and other devices, greatly reducing the interconnection among the devices, and effectively simplifying the layout and the wiring.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a high speed point-to-point serial interface system according to the present invention;

FIG. 2 is a schematic diagram of a media access control module according to the present invention;

FIG. 3 is a schematic structural diagram of a transmitting module according to the present invention;

fig. 4 is a schematic structural diagram of a physical layer module according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In an embodiment of the high speed point-to-point serial interface system of the present invention, a schematic structural diagram of the high speed point-to-point serial interface system is shown in fig. 1. In the figure, the high-speed point-to-point serial interface system 1 comprises a medium access control module 11, a sending module 12 and a physical layer module 13.

The structure diagram of the medium access control module is shown in fig. 2. In the figure, the medium access control module 11 includes a link layer 111, a register module 112, a scrambler 113, and a delay locked loop module 114 of a multi-frame counter, and receives the first data D1 via the register module 112; the schematic structure of the sending module is shown in fig. 3. In the figure, the sending module 12 includes a sending status register module 121, a sending control module 122, a sending scrambling module 123 and a data link layer 124, and receives one or more sample data streams of the first data D1, and converts the data streams into one or more serial streams to generate the second data D2; the structure diagram of the physical layer module is shown in fig. 4. In the figure, the physical layer module 13 includes an encoder 131, a word aligner 132, a physical coding sublayer 133 of the serializer, and a physical medium adaptation layer module 134 of the serializer, receives the second data D2 and outputs to the digital-to-analog conversion module 2.

Wherein the sending state registering module 121 is a management configuration state registering module; the transmission control module 122 is a controller that manages synchronization signals, a state machine that controls the state of the data link layer, a local multi-frame clock, and deterministic delays of the entire link; the transmission scrambling module 123 and the data link layer 124 implement an initial channel alignment sequence with 32 bits of data, and perform scrambling, channel insertion, and frame alignment of characters; the data link layer 124 includes code group synchronization, initial lane synchronization, and user data phase, and establishes a synchronization link according to the code group synchronization, initial lane synchronization, and user data phase.

In this embodiment, the mac module 11 receives the first data D1 via the register module 112, and further operates the transmitter module 12 on a data width of 32 bits per channel according to its link layer 111, scrambler 113 and dll module 114 of multi-frame counter, wherein the frame groups the data into four octets per channel, so that if the link rates are the same, its multiple transmitters 12 can share the clock and reset, and receive one or more sample data streams of the first data D1, and convert them into one or more serial streams, generate the second data D2, and implement the initial channel alignment sequence with 32 bits of data via the transmitter status register module 121, the transmitter control module 122, the transmitter scrambling module 123 and the data link layer 124, and perform scrambling, channel insertion and frame alignment of characters, and wherein the data link layer 14 includes a code group synchronization, a channel synchronization, and a channel synchronization, Initial channel synchronization and user data phase, and a synchronization link is established according to the code group synchronization, the initial channel synchronization and the user data phase, and finally, after being encoded by the encoder 131 of the physical layer module 13, the word aligner 132, the physical coding sublayer 133 of the serializer, and the physical medium adaptation layer module 134 of the serializer, the second data D2 is output to the digital-to-analog conversion module 2.

The invention provides a higher speed serial interface, the interface speed is up to 12.5 Gbps/channel, frame serial data link, embedded clock and alignment character are used, it reduces the number of wires between devices, reduces the wire matching requirement, and eliminates the problem of establishing and maintaining time sequence constraint, thereby simplifying the implementation of high speed converter data interface, reducing the number of digital input and output channels between high speed data converter and FPGA and other devices, and greatly reducing the interconnection therein, effectively simplifying layout and wiring.

The above description is only exemplary of the present invention and should not be taken as limiting the invention, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high speed point-to-point serial interface system comprising:

the device comprises a medium access control module, a data processing module and a data processing module, wherein the medium access control module comprises a link layer, a register module, a scrambler and a delay phase-locked loop module of a multi-frame counter, and receives first data through the register module;

a plurality of sending modules, electrically connected to the medium access control module, wherein the sending modules include a sending state register module, a sending control module, a sending scrambling module and a data link layer, and receive one or more sampling point data streams of the first data, and convert the sampling point data streams into one or more serial streams to generate second data; and

and the physical layer module is electrically connected with the plurality of sending modules, comprises an encoder, a word aligner, a physical coding sublayer of the serializer and a physical medium adaptation layer module of the serializer, receives the second data and outputs the second data to the digital-to-analog conversion module.

2. The system of claim 1, wherein the sending state registration module is a management configuration state registration module.

3. The system of claim 1, wherein the transmission controller is a state machine that manages synchronization signals and controls data link layer states, a local multi-frame clock, and deterministic delays across the link.

4. The system of claim 1, wherein the transmission scrambler and data link layer implement an initial lane alignment sequence with 32 bits of data and perform scrambling, lane insertion and frame alignment of characters.

5. The system of claim 1 wherein said data link layer includes code group synchronization, initial channel synchronization and user data phase, and wherein a synchronization link is established based on said code group synchronization, said initial channel synchronization and said user data phase.