CN110768907A

CN110768907A - Method, device and medium for managing FPGA heterogeneous accelerator card cluster

Info

Publication number: CN110768907A
Application number: CN201910865769.2A
Authority: CN
Inventors: 刘钧锴; 葛海亮
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2020-02-07

Abstract

The invention discloses a method for managing an FPGA heterogeneous accelerator card cluster, which comprises the following steps of: judging whether a broadcast packet of a client applying for an IP address is received; in response to receiving a broadcast packet of a client applying for an IP address, distributing a data packet containing the IP address to the client, and recording the IP address to a hardware routing table; sequentially communicating with the client according to the hardware routing table every first preset time; in response to a communication failure, the IP address and the physical address of the client are deleted in the hardware routing table. The invention also discloses a computer device and a readable storage medium. The method, the equipment and the medium for managing the FPGA heterogeneous accelerator card cluster realize dynamic intelligent management of the interconnection of the FPGA heterogeneous accelerator cards on bottom hardware through hardware FPGA logic, reduce the interaction between software and the bottom hardware board card and improve the management efficiency.

Description

Method, device and medium for managing FPGA heterogeneous accelerator card cluster

Technical Field

The present invention relates to the field of FPGA, and more particularly, to a method, an apparatus, and a readable medium for managing clusters of FPGA heterogeneous accelerator cards.

Background

In recent years, with the rise of artificial intelligence and big data, a large number of FPGA acceleration boards are used in a data center, and how to intelligently manage the boards becomes a key problem. Most of the existing solutions are software protocol stack management, and the existing solutions have the problems that software codes are sequentially executed, and the efficiency is not high; and the software needs to interact with the bottom hardware board card more, which affects the execution efficiency of the system.

Disclosure of Invention

In view of this, an object of the embodiments of the present invention is to provide a method, a device, and a medium for managing a cluster of FPGA heterogeneous accelerator cards, which implement dynamic intelligent management of FPGA heterogeneous accelerator cards interconnection on bottom hardware through hardware FPGA logic, reduce interaction between software and bottom hardware boards, and improve management efficiency.

Based on the above object, an aspect of the embodiments of the present invention provides a method for managing an FPGA heterogeneous accelerator card cluster, including the following steps executed by a host of the FPGA heterogeneous accelerator card cluster: judging whether a broadcast packet of a client applying for an IP address is received; in response to receiving a broadcast packet of a client applying for an IP address, distributing a data packet containing the IP address to the client, and recording the IP address to a hardware routing table; sequentially communicating with the client according to the hardware routing table every first preset time; in response to a communication failure, deleting the client's IP address and physical address in the hardware routing table.

In some embodiments, further comprising: and acquiring setting information of the dial switch, and determining whether the card is a host of the FPGA heterogeneous accelerator card cluster according to the setting information.

In some embodiments, further comprising: judging whether the hardware routing table is changed every second preset time; and in response to the hardware routing table change, sending an instruction to the client to update the client hardware routing table.

In some embodiments, further comprising: the client receives the data packet sent by the host and judges whether the client has an IP address or not; responding to the client machine without an IP address, and judging whether the physical address in the data packet is consistent with the physical address of the client machine; and responding to the physical address in the data packet and the physical address of the client to be consistent, and acquiring the IP address in the data packet.

In some embodiments, further comprising: and responding to the IP address of the client, and judging whether the physical address and the IP address in the data packet are consistent with the physical address and the IP address of the client.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: judging whether a broadcast packet of a client applying for an IP address is received; in response to receiving a broadcast packet of a client applying for an IP address, distributing a data packet containing the IP address to the client, and recording the IP address to a hardware routing table; sequentially communicating with the client according to the hardware routing table every first preset time; in response to a communication failure, deleting the client's IP address and physical address in the hardware routing table.

In some embodiments, the steps further comprise: and acquiring setting information of the dial switch, and determining whether the card is a host of the FPGA heterogeneous accelerator card cluster according to the setting information.

In some embodiments, the steps further comprise: judging whether the hardware routing table is changed every second preset time; and in response to the hardware routing table change, sending an instruction to the client to update the client hardware routing table.

In some embodiments, the steps further comprise: the client receives the data packet sent by the host and judges whether the client has an IP address or not; responding to the client machine without an IP address, and judging whether the physical address in the data packet is consistent with the physical address of the client machine; and responding to the physical address in the data packet and the physical address of the client to be consistent, and acquiring the IP address in the data packet.

In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.

The invention has the following beneficial technical effects: the interconnection of the dynamic intelligent management FPGA heterogeneous accelerator cards is realized on bottom hardware through hardware FPGA logic, the interaction between software and bottom hardware board cards is reduced, and the management efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a method for managing clusters of FPGA heterogeneous accelerator cards provided by the present invention;

FIG. 2 is a schematic structural diagram of an FPGA heterogeneous accelerator card provided by the present invention;

fig. 3 is a flowchart of an embodiment of a method for managing an FPGA heterogeneous accelerator card cluster according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

Based on the above objectives, a first aspect of the embodiments of the present invention provides an embodiment of a method for managing an FPGA heterogeneous accelerator card cluster. Fig. 1 is a schematic diagram illustrating an embodiment of a method for managing an FPGA heterogeneous accelerator card cluster according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps executed by a host of an FPGA heterogeneous accelerator card cluster:

s1, judging whether a broadcast packet of the client applying for the IP address is received;

s2, responding to the received broadcast packet of the client applying for the IP address, distributing a data packet containing the IP address to the client, and recording the IP address to a hardware routing table;

s3, sequentially communicating with the client according to the hardware routing table every first preset time; and

s4, in response to the communication failure, deleting the IP address and the physical address of the client in the hardware routing table.

In some embodiments, the method further comprises: and acquiring setting information of the dial switch, and determining whether the card is a host of the FPGA heterogeneous accelerator card cluster according to the setting information. For example, setting one of the dial switch indicates that the FPGA heterogeneous accelerator card is the host, and setting zero of the dial switch indicates that the FPGA heterogeneous accelerator card is the client. The FPGA heterogeneous accelerator card cluster at least comprises one host, and a client can be directly connected with the host or indirectly connected with the host through other clients in a connection mode including but not limited to a form of internet access MAC and the like.

And judging whether the Host receives the broadcast packet of the client applying for the IP address, if so, distributing the IP address according to a Dynamic Host Configuration Protocol (DHCP) Protocol. Specifically, a packet containing an IP address may be distributed to the client, and the IP address may be recorded in a hardware routing table.

Each FPGA heterogeneous accelerator card has a unique physical (MAC) address, is 48 bits long, is fixed in FPGA logic, and can be recorded in a hardware routing table. First preset time can be set in the logic, the FPGA hardware logic communicates with each client in sequence according to the information in the hardware routing table through an ICMP (Internet Control Message Protocol) network Protocol at intervals of the first preset time, for example, ping operation can be performed, if the communication is successful, the FPGA board exists, and is in a pass state. This IP and MAC information is retained in the hardware routing table. If the ping operation is unsuccessful, the communication is failed, the FPGA board card is represented to be in a fail state, the IP and MAC information is deleted from the hardware routing table, the hardware routing table is updated, and meanwhile, an update instruction and update information are sent out.

The client receives the data packet sent by the host and judges whether the client has an IP address or not; if the client does not have an IP address, judging whether the physical address in the data packet is consistent with the physical address of the client or not; and if the physical address in the data packet is consistent with the physical address of the client, acquiring the IP address in the data packet. If the client has an IP address, judging whether the physical address and the IP address in the data packet are consistent with the physical address and the IP address of the client, and if the physical address and the IP address in the data packet are consistent with the physical address and the IP address of the client, responding to the instruction in the data packet.

Fig. 2 is a schematic structural diagram of an FPGA heterogeneous accelerator card provided by the present invention. As shown in fig. 2, the FPGA heterogeneous accelerator card includes a host and client identification module, a DHCP protocol module, a hardware routing table module, and a filtering module. The host and client identification module is used for determining whether the card is a host or a client, and the identification form includes but is not limited to a zero or one setting form of a dial switch; when the board card is a host, the DHCP module is responsible for distributing and managing IP addresses, and when the board card is a client, the DHCP module is responsible for communicating with the DHCP module of the host to apply for the IP address of the card from the host; the hardware routing table module is used for recording the IP address and the physical address of each FPGA heterogeneous accelerator card in the FPGA heterogeneous accelerator card cluster; when the card sends data to outside, the filter module does not work and does not filter, and when the card receives data, the received data packet is filtered according to the IP address and the physical address, and the data packet which does not belong to the card is filtered.

Fig. 3 is a flowchart illustrating an embodiment of a method for managing clusters of FPGA heterogeneous accelerator cards according to the present invention. As shown in fig. 3, starting from block 101, proceeding to block 102, determining whether the card is a host, if yes, proceeding to block 103, determining whether a broadcast packet of a client applying for an IP address is received, if no, proceeding to block 107, and ending; if a broadcast packet of a client applying for an IP address is received, proceeding to block 104, distributing a data packet containing the IP address to the client, and recording the IP address to a hardware routing table, if a broadcast packet of a client applying for an IP address is not received, continuing to wait at block 103; distributing packets containing IP addresses to the clients may be followed by communicating with the clients in sequence according to the hardware routing tables at block 105; proceeding to block 106, the communication fails, the client's IP address and physical address are deleted in the hardware routing table, and proceeding to block 107 ends.

It should be particularly noted that, steps in the embodiments of the method for managing an FPGA heterogeneous accelerator card cluster may be intersected, replaced, added, and deleted, so that these methods for managing an FPGA heterogeneous accelerator card cluster should also belong to the scope of the present invention, and the scope of the present invention should not be limited to the embodiments.

In view of the above object, a second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, judging whether a broadcast packet of the client applying for the IP address is received; s2, responding to the received broadcast packet of the client applying for the IP address, distributing a data packet containing the IP address to the client, and recording the IP address to a hardware routing table; s3, sequentially communicating with the client according to the hardware routing table every first preset time; and S4, in response to the communication failure, deleting the IP address and the physical address of the client in the hardware routing table.

In some embodiments, the steps further comprise: and responding to the IP address of the client, and judging whether the physical address and the IP address in the data packet are consistent with the physical address and the IP address of the client.

The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes in the methods according to the embodiments described above can be implemented by a computer program to instruct related hardware, and the program of the method for managing the FPGA heterogeneous accelerator card cluster can be stored in a computer-readable storage medium, and when executed, the program can include the processes according to the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method for managing an FPGA heterogeneous accelerator card cluster is characterized by comprising the following steps of:

judging whether a broadcast packet of a client applying for an IP address is received;

in response to receiving a broadcast packet of a client applying for an IP address, distributing a data packet containing the IP address to the client, and recording the IP address to a hardware routing table;

sequentially communicating with the client according to the hardware routing table every first preset time;

in response to a communication failure, deleting the client's IP address and physical address in the hardware routing table.

2. The method of claim 1, further comprising:

and acquiring setting information of the dial switch, and determining whether the card is a host of the FPGA heterogeneous accelerator card cluster according to the setting information.

3. The method of claim 1, further comprising:

judging whether the hardware routing table is changed every second preset time; and

in response to the hardware routing table change, an instruction is sent to the client to update the client hardware routing table.

4. The method of claim 1, further comprising:

the client receives the data packet sent by the host and judges whether the client has an IP address or not;

responding to the client machine without an IP address, and judging whether the physical address in the data packet is consistent with the physical address of the client machine; and

and responding to the consistency of the physical address in the data packet and the physical address of the client, and acquiring the IP address in the data packet.

5. The method of claim 4, further comprising:

and responding to the IP address of the client, and judging whether the physical address and the IP address in the data packet are consistent with the physical address and the IP address of the client.

6. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of:

7. The computer device of claim 6, wherein the steps further comprise:

8. The computer device of claim 6, wherein the steps further comprise:

9. The computer device of claim 6, wherein the steps further comprise:

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.