CN107046542A - A kind of method that common recognition checking is realized using hardware in network level - Google Patents
A kind of method that common recognition checking is realized using hardware in network level Download PDFInfo
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- CN107046542A CN107046542A CN201710270949.7A CN201710270949A CN107046542A CN 107046542 A CN107046542 A CN 107046542A CN 201710270949 A CN201710270949 A CN 201710270949A CN 107046542 A CN107046542 A CN 107046542A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/20—Network architectures or network communication protocols for network security for managing network security; network security policies in general
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/30—Decision processes by autonomous network management units using voting and bidding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
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Abstract
The invention discloses a kind of method that common recognition checking is realized using hardware in network level, node is used as by the use of hardware device FPGA, by realizing that ICP/IP protocol carries out point-to-point connection between FPGA nodes, ICP/IP protocol and the interaction of other FPGA nodes are aided in using ARP, ICMP, DHCP, shorten tcpip stack, effectively reduce time delay.FPGA nodes are spread news using block chain common recognition agreement such as PBFT/SBFT/RBFT etc. and known together, and select leader node, and other nodes send feedback and the ballot for receiving information after receiving common recognition message.By being encrypted and accompanied by digital signature in these common recognition agreement communication processes, it is ensured that the security of data.The present invention realizes common recognition agreement in hardware platform, effectively shortens time delay, reach the purpose of hardware-accelerated common recognition on the premise of no increase data center.
Description
Technical field
The invention belongs to block chain technical field, and in particular to a kind of side for realizing common recognition checking using hardware in network level
Method.
Background technology
Under current strict efficiency requirements, data center is faced with increasing data volume and workload complexity
Demand.In order to meet high-performance, scalability and the target of scalability, service is normally operated in hundreds of to thousands of machines
On.This is accomplished by the uniformity that some cooperations common recognition carrys out machine maintenance.Inevitable performance cost and the additional resource needed
Uniformity is often reduced, causes less user to must be set up more complicated application program to handle potential inconsistency.
The high cost that uniformity needs comes from reach an agreement needed for many wheels link up, traditional network stack not to time delay or
Specific communication pattern is optimized, and the acceleration of common recognition agreement is become a bottleneck.
Nowadays various hardware is, when previous increasingly feasible selection, the property of system can be improved under lower energy cost
Energy.In addition to considering performance and efficiency, for intelligent network, node can be added in a network, is customized using middleware
Its application, so wanting the attribute using common recognition as network, rather than only allows it to realize on the application layer, it is necessary in reality
Equalization point is found in the existing accessible handling capacity of complexity and middleware, then adds block chain common recognition agreement in a network and improves
System effectiveness is good selection, and (Practical Byzantine Fault Tolerance, practical Byzantium holds such as PBFT
Miscount method)/SBFT (Simple Byzantine Fault Tolerance simplify Byzantine failure tolerance algorithm)/RBFT
The common recognition such as (Redundant Byzantine Fault Tolerance, redundancy Byzantine failure tolerance algorithm) agreement, and FPGA
The characteristics of (Field-Programmable Gate Array, field programmable gate array) has low-power consumption, not by traditional
Linear speed limitations of the CPU in terms of data processing, can reduce time delay, by extending middleware operating above common recognition agreement
Function or the cheap common recognition of addition to network processing node, will common recognition agreement more value is generalized to network.
The content of the invention
In view of above-mentioned, the present invention proposes a kind of method that common recognition checking is realized using hardware in network level, does not increase number
According to the capacity at center, the block such as PBFT/SBFT/RBFT chain common recognition agreement is realized on FPGA, time delay is reduced.
A kind of method that common recognition checking is realized using hardware in network level, is comprised the following steps：
(1) the system operation framework for realizing common recognition checking using FPGA in network level is built；
(2) by performing TCP/IP (Transmission Control Protocol/Internet between FPGA nodes
Protocol, transmission control protocol/Internet Protocol) agreement progress point-to-point connection；
(3) FPGA nodes use ARP (Address Resolution Protocol, address resolution protocol), ICMP
(Internet Control Message Protocol, Internet Control Message Protocol), DHCP (Dynamic Host
Configuration Protocol, DHCP) aid in ICP/IP protocol to be interacted with other FPGA nodes, shorten
Tcpip stack, makes FPGA be in live network；
(4) data-message is converted into the message format for meeting common recognition agreement needs by FPGA nodes；
(5) data-message is carried out to transmit wide using PBFT, SBFT or RBFT block chain common recognition agreement by FPGA nodes
Broadcast, other FPGA nodes are sent after receiving to be fed back and voted.
The concrete methods of realizing of the step (1) is：Arrange a certain amount of FPGA as node, any two in a network
There is passage between FPGA nodes can interact, and each FPGA nodes are by connecting interchanger to realize many opposite ends of synchronization
Data transfer between mouthful, FPGA nodes are using its less feature of internal BRAM (embedded block RAM) buffering areas, to discharge
DRAM (dynamic random access memory) memory headroom is used to know together and using the execution of logic.
The concrete methods of realizing of the step (2) is as follows：By FPGA intra-node buffering area dynamically distributes TCP sessions, make
Client request data are less than Ethernet MTU (Maximum Transmission Unit, MTU) size；FPGA
Node is only mutually retransmitted between other nodes, without the timeouts between consideration and client, to reduce TCP pop down；
Realize that procotol allows to set up two real data flow paths correspondences and realizes that isolation sends and receives path, two by hardware
Bar passage be independent of each other other side and by data structure share connection status.
The data structure includes session lookup table, Port State Table and the event engine supported by timer；Wherein,
Session lookup table includes IP address, destination address and source port, and FPGA is when implementing using its depositing as content addressable
Reservoir；Port State Table is used for the state for tracking each TCP port and the TCP connection storage state information each to open；Thing
Part engine is responsible for activity and the incoming request of transmission interface and indicates corresponding output engine work.
The concrete methods of realizing of the step (3) is：Point-to-point communication is carried out between FPGA device, if data are because slow
Deposit insufficient space or line interruption and lose, then report that dependent event recipient can send weight to the source of data by ICMP
Send out the notice of request；When sending packet, if sender does not have the MAC Address of recipient but knows the IP address of recipient,
Broadcast the message of request recipient's MAC Address；It is one idle IP address of FPGA node distributions by Dynamic Host Configuration Protocol server, and
Stamp effective time stamp；When sending and receiving data in ARP, ICMP, DHCP these agreements, application program uses session and net
Network storehouse communicates, then directly forwards the data in the mixed-media network modules mixed-media of application-specific；Packet is directly passed over ethernet
During broadcasting, whether lost come detection data using sequence number, the sequence number increases with the increase of logic requests.
The concrete methods of realizing of the step (4) is：Data-message is divided into the module of needs, shows biography with Metadata table
Defeated metadata, payload is represented with Payload；Part in specification common recognition agreement, node is represented with Signature
The digital signature interacted with node, the timestamp of message is represented with Timestamp, represents that FPGA adds network registry and needed with Cert
The certificate wanted.It is beneficial to the identification datas such as block chain common recognition agreement PBFT/SBFT/RBFT after specification message format.
The concrete methods of realizing of the step (5) is：On the premise of the FPGA nodes generation certificate of registry of network is added,
Leader node is selected first, and the data-message for needing to broadcast is generated using hash function SHA-256 by leader node and made a summary, so
A random number nonce is generated afterwards and ECDSA (elliptic curve digital signature algorithm) is carried out using hardware encryption module calculates, it is raw
The signature made a summary in pairs, and then the data message after signature is carried out using PBFT, SBFT or RBFT block chain common recognition agreement
Transmission broadcast；Other FPGA nodes are received after data message, and whether checking signature is the data person of sending, and determines that data are legal
Property, then send the feedback notification for receiving message and ballot work is carried out to data.
The present invention realizes common recognition agreement, rather than increase without reducing performance, selection in order to improve uniformity on hardware
More data centers.The present invention realizes the block such as PBFT/SBFT/RBFT chain common recognition agreement in hardware FPGA system, creates
Middleware or intelligent network hardware can be increased reuses scheme, and can use hardware or progressively start to occur
Hardware platform come handle TCP/IP procotols and specific procotol work.FPGA can be accessed in most instances
Daily record in dram chip, reads cache memory head, is adapted to the block chains such as PBFT/SBFT/RBFT common recognition agreement and exists
Realized on FPGA hardware.
In traditional algorithm, the payload obtained from TCP flow has to fill up whole MTU data package sizes, so being
Wait more data, which are filled up, just has to wait for a period of time, and each request less than MTU sizes can be because of timeouts
And postpone a period of time.And in the present invention program, client request is always less than Ethernet MTU sizes 1500B, thus
Time delay can preferably be shortened.
Brief description of the drawings
Fig. 1 is interactive relation schematic diagram between node.
Fig. 2 is the overall structure diagram of FPGA hardware.
Fig. 3 is TCP stack architecture schematic diagrames.
Embodiment
In order to more specifically describe the present invention, below in conjunction with the accompanying drawings and embodiment is to technical scheme
It is described in detail.
Present embodiment arranges three FPGA hardware equipment as node, and node uses FPGA evaluation boards, the evaluation board
With multiple Ethernet interfaces.System is divided into three modules, and network protocol module, message format modified module and block chain are common
Know protocol module, hardware configuration is integrally as shown in Figure 1.
There is passage between each two node can be interacted, and multiple ports pair can be carried out in synchronization using interchanger
Between data transfer, have corresponding BRAM modules in each FPGA, BRAM buffering areas are smaller, delay can be reduced without influence property
Can, release DRAM memory headrooms are used for knowing together and using the execution of logic, so retaining Large Copacity DRAM buffering areas, hardware is overall
Structure is as shown in Figure 2.Between node point-to-point connection, FPGA internal buffers dynamically distributes are carried out by performing ICP/IP protocol
TCP sessions, client request is less than Ethernet MTU sizes, and FPGA is only mutually retransmitted between other FPGA, without considering and visitor
Timeouts between the end of family, reduces TCP pop down.
In network protocol module, using Transmission Control Protocol and multiple application protocols, in order to reduce time delay in Transmission Control Protocol,
Reduce the space that storage takes, hardware realizes that procotol allows to set up real data flow path and isolate to send and receive road
Footpath, makes them not influence other side, and two passes share connection status by data structure.These data structures have session lookup
Table, port table, state table and the event engine supported by timer, the four-tuple mapping session id that session lookup table is included are right
FPGA is used as a Content Addressable Memory；Port table tracks the state of each TCP port, is the TCP connections of each opening
State table storage information；Event engine is responsible for activity concurrency and send interface incoming request, and indicates corresponding TX engines work
Make.
BRAM internal buffers are divided into several FIFO (First Input First Output, First Input First Output),
Dynamically distributes TCP sessions, when BRAM buffering areas can determine that a complete request is available in a fifo queue, just by it
It is transmitted to application logic.It is all full if all of fifo queue, in order to not lose any data, just by TCP weight
Biography mechanism retransmits data.Client request always be less than Ethernet MTU sizes, remove after timeouts, FPGA except and other
Outside mutual re-transmission between FPGA, request is propagated in different layers and will not come because of the of different sizes and divided of MTU.Should
Whether, with agreement, packet is directly propagated over ethernet, lost come detection data with sequence number, and sequence number please with logic
The increase asked and increase.Point-to-point communication is carried out between FPGA device, if data are because the interruption of inadequate buffer space or circuit
And lose, recipient can send retransmit request notice, when sending and receiving data in the agreement, application program with network
Session is used when storehouse communicates, so that they are forwarded directly to the mixed-media network modules mixed-media specific to application program；TCP stack architectures are as schemed
Shown in 3.
In message format conversion module, the module of needs is specifically splitted data into, first number of transmission is represented with Metadata
According to Payload represents payload.Part in specification common recognition agreement, represents node with Signature and is interacted with node
Digital signature, represented with Timestamp message completion timestamp, Cert represent FPGA add network registry need certificate
Deng.
In block chain common recognition protocol module, FPGA nodes are using block chain common recognition agreement transmission message, such as PBFT/SBFT/
RBFT etc., other nodes send feedback and the ballot for receiving information after receiving common recognition message.Adding the FPGA nodes life of network
On the premise of certificate of registry, i.e., FPGA nodes enter network as legitimate node.By three FPGA node serial numbers 0,1,2, head
First according to block height to 3 modulus (three FPGA nodes), obtained remainder i.e. correspondence FPGA numbering so selects leader's section
Point.Leader node needs specification the data-message of broadcast to generate summary using hash function SHA-256 after message format,
Then a random number nonce is generated, and ECDSA calculating is carried out with hardware encryption module, the signature to summary is generated, to other
Node, which is submitted, to be proved.Whether other nodes are received after data message, be the data person of sending by random number nonce checking signatures
, data validation is determined, then carries out receiving the feedback notification of message and ballot work is carried out to data.
The above-mentioned description to embodiment is understood that for ease of those skilled in the art and using the present invention.
Person skilled in the art obviously can easily make various modifications to above-described embodiment, and described herein general
Principle is applied in other embodiment without passing through performing creative labour.Therefore, the invention is not restricted to above-described embodiment, ability
Field technique personnel are according to the announcement of the present invention, and the improvement made for the present invention and modification all should be in protection scope of the present invention
Within.
Claims (7)
1. a kind of method that common recognition checking is realized using hardware in network level, is comprised the following steps：
(1) the system operation framework for realizing common recognition checking using FPGA in network level is built；
(2) point-to-point connection is carried out by performing ICP/IP protocol between FPGA nodes；
(3) FPGA nodes are interacted using ARP, ICMP and DHCP auxiliary ICP/IP protocol with other FPGA nodes, shorten TCP/IP
Storehouse, makes FPGA be in live network；
(4) data-message is converted into the message format for meeting common recognition agreement needs by FPGA nodes；
(5) transmission broadcast is carried out to data-message using PBFT, SBFT or RBFT block chain common recognition agreement by FPGA nodes, its
His FPGA nodes are sent after receiving to be fed back and is voted.
2. according to the method described in claim 1, it is characterised in that：The concrete methods of realizing of the step (1) is：In a network
A certain amount of FPGA is arranged as node, there is passage between any two FPGA nodes can interact, and each FPGA nodes are equal
By connecting interchanger to realize the data transfer between the multipair port of synchronization, FPGA nodes utilize its internal BRAM buffering
The less feature in area, is used to know together and using the execution of logic to discharge DRAM memory headrooms.
3. according to the method described in claim 1, it is characterised in that：The concrete methods of realizing of the step (2) is as follows：By FPGA
Intra-node buffering area dynamically distributes TCP sessions, make client request data be less than Ethernet MTU sizes；FPGA nodes only with
Mutually retransmitted between other nodes, without the timeouts between consideration and client, to reduce TCP pop down；Pass through hardware
Realize that procotol allows to set up two real data flow paths correspondences and realizes that isolation sends and receives path, two passes are mutual
Other side is not influenceed and connection status is shared by data structure.
4. method according to claim 3, it is characterised in that：The data structure includes session lookup table, port status
Table and the event engine supported by timer；Wherein, session lookup table includes IP address, destination address and source port, FPGA
Implement when using its as a content addressable memory；Port State Table is for tracking the state of each TCP port simultaneously
For the TCP connection storage state information of each opening；Event engine is responsible for activity and the incoming request of transmission interface simultaneously
Indicate corresponding output engine work.
5. according to the method described in claim 1, it is characterised in that：The concrete methods of realizing of the step (3) is：Set in FPGA
Point-to-point communication is carried out between standby, if data are lost because of inadequate buffer space or line interruption, by ICMP to data
Source report, dependent event recipient can send retransmit request notice；When sending packet, if sender does not have recipient
MAC Address but know the IP address of recipient, then broadcast the message of request recipient's MAC Address；By Dynamic Host Configuration Protocol server
For one idle IP address of FPGA node distributions, and stamp effective time stamp；Sent in ARP, ICMP, DHCP these agreements
During with receiving data, application program is communicated using session with network stack, then directly forwards the data to application-specific
In mixed-media network modules mixed-media；During packet is directly propagated over ethernet, whether lost come detection data using sequence number, it is described
Sequence number increases with the increase of logic requests.
6. according to the method described in claim 1, it is characterised in that：The concrete methods of realizing of the step (4) is：Data are disappeared
Breath is divided into the module of needs, and the metadata of transmission is shown with Metadata table, payload is represented with Payload；Specification common recognition association
Part in view, the digital signature that node is interacted with node is represented with Signature, message is represented with Timestamp
Timestamp, represents that FPGA adds the certificate that network registry needs with Cert.
7. according to the method described in claim 1, it is characterised in that：The concrete methods of realizing of the step (5) is：Adding net
On the premise of the FPGA nodes generation certificate of registry of network, leader node is selected first, the data of broadcast will be needed by leader node
Message generates summary using hash function SHA-256, then generates a random number nonce and is carried out using hardware encryption module
ECDSA is calculated, and is generated to the signature of summary, and then after knowing together agreement to signature using PBFT, SBFT or RBFT block chain
Data message carries out transmission broadcast；Other FPGA nodes are received after data message, and whether checking signature is the data person of sending, really
Determine data validation, then send the feedback notification for receiving message and ballot work is carried out to data.
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