CN110767538B

CN110767538B - Layout structure and method for forming semiconductor integrated circuit device

Info

Publication number: CN110767538B
Application number: CN201810837135.1A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-07-26
Filing date: 2018-07-26
Publication date: 2024-06-07
Anticipated expiration: 2038-07-26
Also published as: CN110767538A

Abstract

The invention provides a layout structure and a method for forming a semiconductor integrated circuit device. Since the mask pattern has a plurality of cut-off pattern regions disposed closely on the boundary of the mask pattern region, when the first feature pattern is defined as a second feature pattern by the mask pattern, the defined second feature pattern can have an edge portion adjacent to the cut-off pattern region, and the edge portion has a larger margin between the side facing the cut-off pattern region and other portions in the adjacent second feature pattern. In this way, the node area is defined on the edge portion of the second feature pattern, that is, a larger space area is reserved for the node area correspondingly, so that the preparation difficulty of the corresponding process executed on the node area is reduced effectively, and the process window of the related process can be increased.

Description

Layout structure and method for forming semiconductor integrated circuit device

Technical Field

The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a layout structure and a method for forming a semiconductor integrated circuit device.

Background

With the continued development of semiconductor integrated circuits, it is generally desirable to increase the integration density of feature films by reducing the size of each feature film within the integrated circuit and reducing the spacing between adjacent feature films. However, as the arrangement density of the feature film layer is increased, the process difficulty is also greater when further processing is performed on the formed feature film layer having a smaller size, so that defects are more likely to occur.

Fig. 1a and 1b are schematic structural diagrams of a conventional method for forming a semiconductor integrated circuit device during the fabrication process. The forming method comprises the following steps:

First, referring to fig. 1a, a first feature film 1 having a first feature pattern is formed. Specifically, the first feature film layer 1 includes, for example, a plurality of annular sub-film layers 1a, the plurality of annular sub-film layers 1a are sequentially arranged in parallel along a first direction (X direction), and the annular sub-film layers 1a extend along a second direction (Y direction);

next, referring to fig. 1a and 1b in combination, a covering mask layer 2 is formed on the first feature film layer 1, where the covering mask layer 2 covers the middle area of the annular sub-film layer 1a of the first feature film layer 1 and exposes the end areas of the annular sub-film layer 1a, so that the middle area of the covered annular sub-film layer 1a is reserved by using the covering mask layer 2, and each annular sub-film layer 1a is cut into two strip-shaped sub-film layers 1b separated from each other, and a second feature film layer may be formed by a plurality of strip-shaped sub-film layers 1 b.

The covering mask layer 2 is generally rectangular (i.e., the boundary of the covering mask layer 2 in the second direction is generally a linear boundary), so that the ends of the plurality of strip-shaped sub-film layers 1b defined by the covering mask layer 2 are aligned in the first direction (X direction).

Next, as shown in fig. 1b, a node area is defined on the end of the strip-shaped sub-film layer 1b, and a node contact layer 1c is formed on the node area. The strip-shaped sub-film layer 1b is, for example, a conductive wire, and one of the node contact layers 1c is electrically connected with one strip-shaped sub-film layer 1b for leading out the conductive wire.

However, as shown in fig. 1b, since the ends of the plurality of strip-shaped sub-film layers 1b are aligned, the distance between the adjacent ends of the adjacent strip-shaped sub-film layers 1b is small, thereby correspondingly limiting the size of the node contact layer 1c formed on the ends, which would easily result in a large contact resistance between the node contact layer 1c and the strip-shaped sub-film layer 1 b; in addition, the process window reserved for preparing the node contact layer 1c is smaller, so that the node contact layer 1c is difficult to prepare, and the problem that the node contact layer 1c is in short circuit with the adjacent strip-shaped sub-film layer 1b is easily caused.

Disclosure of Invention

The present invention aims to provide a layout structure for improving a node area defined in the layout structure, which has a smaller distance from an adjacent pattern, so that the related process is not beneficial to the node area.

In order to solve the above technical problems, the present invention provides a layout structure, including:

a first pattern of features comprising at least one first sub-pattern (110); and

A mask pattern disposed over the first feature pattern, the mask pattern having a masking pattern region and a plurality of truncated pattern regions, the masking pattern region having two opposing first and second boundaries in a second direction, the first and second boundaries each extending along the first direction; and a plurality of the truncated graphic regions are respectively disposed in regions near the first and second boundaries;

Wherein the masking pattern region of the mask pattern masks the first sub-patterns of portions and exposes each of the first sub-pattern portions to the intercepting pattern region, the portions of the first sub-patterns exposed to the intercepting pattern region are arranged in an offset manner with respect to a center line of the first sub-pattern, the masked portions of the first sub-pattern are defined as a plurality of divided second sub-patterns, and a plurality of first node regions and second node regions are defined in a plurality of second sub-patterns of the second feature pattern with respect to a plurality of protruding sections adjacent to the second sub-pattern, the first node regions and the second node regions being adjacent to the first boundary and the second boundary of the masking pattern region, respectively, such that the first node regions and the second node regions are adjacent to the intercepting pattern region.

Optionally, the first feature pattern includes a plurality of first sub-patterns, where the first sub-patterns are annular sub-patterns and are sequentially arranged in parallel along the first direction; and the annular sub-pattern is provided with two mutually parallel lines, the lines extend along the second direction and are provided with two opposite first line ends and second line ends in the extending direction, and the ends of the two lines of the annular sub-pattern are mutually connected and provided with connecting parts.

Optionally, the covering pattern area of the mask pattern extends from the middle area to the end of the annular sub-pattern to cover the annular sub-pattern, the truncated pattern area corresponding to the first boundary exposes a first line end of one line of the annular sub-pattern, and the truncated pattern area corresponding to the second boundary exposes a second line end of another line of the annular sub-pattern, so that one annular sub-pattern in the first feature pattern is defined as two mutually separated strip-shaped sub-patterns, and the second feature pattern is formed by a plurality of strip-shaped sub-patterns.

Optionally, the truncated graphic region is located in an area between the first boundary and the second boundary of the cover graphic region to surround the truncated graphic region by the cover graphic region.

Optionally, the connection portion of the annular sub-pattern is covered by the covering pattern region of the mask pattern, so that the annular sub-pattern is defined into two strip-shaped sub-patterns from a line end portion of the annular sub-pattern, the strip-shaped sub-patterns are formed by the lines and the connection portion, and the first node region and the second node region are defined on the connection portion of the strip-shaped sub-pattern.

Optionally, the shape of the truncated graphic region includes a rectangle, a circle, or an ellipse.

Optionally, the cut-off pattern area is located on the first boundary or the second boundary of the covering pattern area, and extends from the first boundary or the second boundary toward the center direction of the covering pattern area, so that the cut-off pattern area is embedded into the covering pattern area from the first boundary or the second boundary, and a plurality of cut-off pattern areas corresponding to the same boundary are mutually communicated outside the boundary of the covering pattern area.

Optionally, each of the truncated pattern regions of the mask pattern exposes an end of one of the lines in the annular sub-pattern, and extends in a direction away from a center of the masking pattern region to expose at least a portion of the connection portion.

Optionally, the lines and part of the connecting portions in the annular sub-pattern form a stripe sub-pattern in the second feature pattern, and the first node area and the second node area are defined at corner joints of the lines and the connecting portions in the stripe sub-pattern.

Optionally, the cut-off pattern region of the mask pattern further exposes all the connection portions of the annular sub-pattern, and a stripe sub-pattern in the second feature pattern is formed by lines in the annular sub-pattern, and the first node region and the second node region are defined on ends of the stripe sub-pattern.

Optionally, in the mask pattern, the first boundary and the second boundary of the covering pattern area are both waveform boundaries, and the peaks and the troughs of the first boundary correspond to the peaks and the troughs of the second boundary, so that the truncated pattern area corresponding to the first boundary and the truncated pattern area corresponding to the second boundary expose two different lines in each annular sub-pattern respectively.

Optionally, the first boundary and the second boundary are both rectangular wave boundaries or arc wave boundaries.

Optionally, the parallel spacing dimension between adjacent stripe sub-patterns is smaller than the minimum pitch feature dimension of the photolithography process.

The invention also provides another layout structure, which comprises:

a first feature pattern including a plurality of island sub-patterns, and the plurality of island sub-patterns in the first direction being staggered from each other to present a wave arrangement;

A mask pattern disposed over the first feature pattern, the mask pattern having a masking pattern region and a plurality of intercepting pattern regions, the masking pattern region having two opposite first and second boundaries in a second direction, the first and second boundaries each extending along a first direction waveform to correspond to a waveform arrangement of the island sub-pattern in the first direction; and a plurality of the truncated graphic regions are respectively disposed in regions near the first and second boundaries;

Wherein the masking pattern region of the mask pattern masks a portion of the first feature pattern to define a masked portion of the first feature pattern as a second feature pattern; and a plurality of node areas are defined in the second feature pattern, the plurality of node areas being respectively adjacent to the first boundary and the second boundary of the cover pattern area such that the node areas are adjacent to the cut-off pattern area.

Optionally, in the mask pattern, the first boundary and the second boundary of the covering graphic area are both waveform boundaries, so as to correspond to waveform arrangement of the island-shaped sub-pattern in the first direction; and the boundaries recessed to the covering pattern areas in the first boundary and the second boundary define a plurality of the cut-off pattern areas, and the cut-off pattern areas corresponding to the same boundary are communicated with each other outside the covering pattern areas.

Optionally, the masking pattern region masks a portion of the island sub-patterns in the first feature pattern to define a plurality of the masked island sub-patterns in the first feature pattern as second feature patterns, and at least a portion of the island sub-patterns in the second feature pattern near the first boundary and the second boundary is defined as the node region.

Optionally, a dimension of a space between adjacent island sub-patterns is smaller than a minimum pitch feature dimension of a photolithography process.

Still another object of the present invention is to provide a method of forming a semiconductor integrated circuit device, comprising:

Forming a first characteristic film layer on a substrate, wherein the first characteristic film layer comprises at least one first sub-film layer;

Forming a covering mask layer on the first characteristic film layer, wherein the covering mask layer is provided with a covering pattern area and a plurality of cutting pattern areas, the covering pattern area is provided with a first boundary and a second boundary which are opposite in a second direction, the first boundary and the second boundary extend along the first direction, and the cutting pattern areas are respectively arranged in areas close to the first boundary and the second boundary; the covering pattern area of the covering mask layer covers the first sub-film layers of the first characteristic film layer, each first sub-film layer is partially exposed to the cutting pattern area, and the part exposed to the cutting pattern area in the first sub-film layer is arranged in an offset mode relative to the central line of the first sub-film layer; and

And etching the first sub-film layer of the first characteristic film layer by taking the covering mask layer as a mask, wherein a removed area in the first characteristic film layer forms a blank area, a reserved part in the first sub-film layer of the first characteristic film layer forms a plurality of divided second sub-film layers, the second sub-film layers form a second characteristic film layer, a plurality of first node areas and second node areas are defined in a plurality of protruding sections of the second sub-film layers of the second characteristic film layer relative to the adjacent second sub-film layers, and the first node areas and the second node areas are adjacent to the blank area.

Optionally, the first feature film layer includes a plurality of first sub-film layers, the first sub-film layers are annular sub-film layers, and the plurality of annular sub-film layers are sequentially arranged in parallel along a first direction; and dividing each annular sub-film layer in the first characteristic film layer into two mutually separated strip-shaped sub-film layers by utilizing the covering mask layer, and forming the second characteristic film layer by a plurality of strip-shaped sub-film layers.

Optionally, the first feature film layer is formed by using a pitch multiplication process, and the forming method includes:

Forming a plurality of auxiliary lines on the substrate, wherein the auxiliary lines are sequentially arranged along the first direction, and the auxiliary lines extend along the second direction;

Forming an annular side wall on the side wall of the auxiliary line, wherein the annular side wall surrounds the auxiliary line; and

And removing the auxiliary lines, forming a plurality of annular sub-film layers by the plurality of reserved annular side walls, and forming the first characteristic film layer by the annular sub-film layers.

Optionally, the strip-shaped sub-film of the second feature film has opposite first and second film ends; and the node area of one strip-shaped sub-film layer is positioned at the end part of the first film layer, and the node area of the other strip-shaped sub-film layer is positioned at the end part of the second film layer.

Optionally, after forming the second feature film layer, the method further includes: a node contact layer is formed on the node region.

Optionally, the semiconductor integrated circuit device is an integrated circuit memory, and the strip-shaped sub-film layer in the second characteristic film layer is a bit line of the integrated circuit memory.

The invention also provides a forming method of the integrated circuit device, which comprises the following steps:

Forming a first characteristic film layer on a substrate, wherein the first characteristic film layer comprises a plurality of island-shaped sub-film layers, and the island-shaped sub-film layers in a first direction are staggered to form each other so as to present wave-shaped arrangement;

forming a covering mask layer on the first characteristic film layer, wherein the covering mask layer is provided with a covering pattern area and a plurality of cutting pattern areas, the covering pattern area is provided with two opposite first boundaries and second boundaries in a second direction, and the first boundaries and the second boundaries extend along a waveform in the first direction so as to correspond to the waveform arrangement of the island sub-patterns in the first direction, and the covering pattern area of the covering mask layer is used for covering part of the island sub-film layers of the first characteristic film layer;

And etching the first characteristic film layer by taking the covering mask layer as a mask, wherein a removed area in the first characteristic film layer forms a blank area, a plurality of island-shaped sub-film layers reserved in the first characteristic film layer form a second characteristic film layer, a plurality of node areas are defined in the second characteristic film layer, and the node areas are adjacent to the blank area.

Optionally, the method for forming the first feature film layer includes:

Forming a plurality of first lines on a substrate by using a pitch multiplication process, wherein the first lines are parallel to each other;

Forming a plurality of second lines on the substrate by using a pitch multiplication process, wherein the second lines intersect the first lines and are provided with a plurality of overlapping areas; and

And etching the first line by taking the second line as a mask, wherein a part of the first line corresponding to the overlapping region is reserved to form a plurality of island-shaped sub-film layers, and the island-shaped sub-film layers form the first characteristic film layer.

Optionally, the method for forming the first feature film layer includes:

Forming a plurality of first island-shaped sub-film layers on a substrate, wherein a first interval dimension is arranged between adjacent first island-shaped sub-film layers, and the first interval dimension is larger than or equal to the minimum interval characteristic dimension of a photoetching process; and

And forming a plurality of second island-shaped sub-film layers on the substrate, wherein a second interval dimension is arranged between adjacent second island-shaped sub-film layers, the second interval dimension is larger than or equal to the minimum interval characteristic dimension of the photoetching process, and the second island-shaped sub-film layers are embedded between the adjacent first island-shaped sub-film layers.

Optionally, among the plurality of first island-shaped sub-film layers, three adjacent first island-shaped sub-film layers are arranged in a triangle shape; among the plurality of second island-shaped sub-film layers, three adjacent second island-shaped sub-film layers are arranged in a triangle shape, wherein the second island-shaped sub-film layers are arranged in an inverted triangle shape relative to the first island-shaped sub-film layers and are mutually nested with the triangle shape of the first island-shaped sub-film layers, so that the three first island-shaped sub-film layers and the three second island-shaped sub-film layers are arranged in a hexagon shape.

Optionally, after forming the second island sub-film layer, the method further includes:

Forming sacrificial film layers on the side walls of the first island-shaped sub-film layer and the second island-shaped sub-film layer, wherein in each hexagon, the sacrificial film layers on the side walls of the six island-shaped sub-film layers are connected with each other so as to surround a cavity in the central area of the hexagon; and

And filling a third island-shaped sub-film layer in the cavity, and removing the sacrificial film layer to form the first characteristic film layer formed by the first island-shaped sub-film layer, the second island-shaped sub-film layer and the third island-shaped sub-film layer.

Optionally, after forming the second feature film layer, the method further includes:

The filling medium material layer is arranged on the outer periphery of the island-shaped sub-film layer of the second characteristic film layer, and the island-shaped sub-film layer is exposed; and

And removing the island sub-film layer to form a plurality of through holes in the dielectric material layer, wherein the through holes form a through hole array.

Optionally, the semiconductor integrated circuit device is an integrated circuit memory, and the array of vias in the second feature film layer is used to form an array of capacitors of the integrated circuit memory.

In the layout structure provided by the invention, the mask pattern is provided with the covering pattern area and the plurality of cutting pattern areas, and the plurality of cutting pattern areas can be flexibly configured to be close to the boundary of the covering pattern area, so that when the first characteristic pattern is defined into the second characteristic pattern by the mask pattern, the edge part, close to the boundary of the covering pattern area, of the defined second characteristic pattern is close to the cutting pattern area, and a larger distance (at least the cutting pattern area is separated between the edge part and other parts of the adjacent second characteristic pattern) exists between the edge part and the side facing the cutting pattern area. Thus, a node region may be defined on a portion of the second feature pattern near the boundary of the masking pattern region, i.e., the defined node region corresponds to an adjacent truncated pattern region, and the node region has a larger spatial area on a side facing the truncated pattern region. Therefore, when the corresponding process is executed on the node area, the execution difficulty of the corresponding process can be effectively reduced, for example, when the node contact layer needs to be prepared on the node area, the size of the formed node contact layer can be increased, the problem that the formed node contact layer is short-circuited with other adjacent film layers can be effectively solved, and the process window of the node contact layer is increased.

Drawings

FIGS. 1 a-1 b are schematic diagrams illustrating a method of forming a semiconductor integrated circuit device in the prior art during the fabrication process;

FIG. 2 is a schematic diagram of a layout structure according to a first embodiment of the present invention;

Fig. 3a is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a first embodiment of the present invention when preparing a first feature film;

FIG. 3b is a schematic diagram illustrating a method for forming a semiconductor integrated circuit device according to an embodiment of the present invention, in which a second feature film is formed;

FIG. 4 is a schematic diagram of a layout structure in a second embodiment of the present invention;

fig. 5 is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a second embodiment of the present invention when the second feature film layer is formed;

FIG. 6a is a schematic diagram of one layout structure in a third embodiment of the present invention;

FIG. 6b is a schematic diagram of another layout structure in a third embodiment of the present invention;

Fig. 7 is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a third embodiment of the present invention when the second feature film layer is formed;

FIG. 8 is a diagram of a layout structure in a fourth embodiment of the present invention;

Fig. 9a is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a fourth embodiment of the present invention when one of the methods is used to prepare a first feature film;

fig. 9b is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to the fourth embodiment of the present invention when the method is used for preparing the first feature film layer by another method;

Fig. 10 is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to the fourth embodiment of the present invention when the second feature film layer is formed;

fig. 11 to 12 are schematic structural views of a method for forming a semiconductor integrated circuit device according to a fourth embodiment of the present invention in the process of preparing a via array.

Wherein, the reference numerals are as follows:

1-a first feature film layer; 1 a-a cyclic sub-film layer;

1 b-strip-shaped sub-film layer; 1 c-node contact layer;

2-covering the mask layer;

10-a first feature film layer;

11 a-auxiliary lines; 11-a ring-shaped sub-membrane layer;

10A/10B/10C-second feature film;

11A/11B/11C-strip-shaped sub-film layers; 12A/12B/12C-node contact layer;

100-a first feature pattern; 110-a ring-shaped sub-pattern;

110a-110a' -centerline;

111-lines; 112-a connection;

111X 1-first wire ends; 111X 2-second line ends;

100A/100B/100C/100D-second feature pattern;

110A/110B/110C/110D-stripe sub-patterns;

121A/121B/121C/121D-a first node area;

122A/122B/122C/122D-second node area;

200A/200B/200C/200D-mask patterns;

210A/210B/210C/210D-cover the graphics area;

220A/220B/220C/220D-truncated graphic region;

210X 1-a first boundary; 210X 2-a second boundary;

30-a first feature film layer; 31-island sub-film layers;

30A-a second feature film layer;

31 a-first lines; 31 b-a second line;

31a' -a first island seed film layer; 31b' -a second island seed film layer;

31c' -a third island seed film layer; 31d' -sacrificial film layer;

A 32-dielectric material layer;

33A-an array of vias; 33-through holes;

300-a first feature pattern; 310-island sub-patterns;

300A-a second feature pattern;

400-covering the mask layer;

410-masking the graphics area; 420-truncating the graphic region;

410X 1-mask graphics region boundaries.

Detailed Description

The layout structure and the method for forming the semiconductor integrated circuit device according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Example 1

Fig. 2 is a schematic diagram of a layout structure in a first embodiment of the present invention, as shown in fig. 2, where the layout includes:

a first feature pattern 100 comprising at least one first sub-pattern; and

A mask pattern 200A having a cover pattern region 210A and a plurality of cut-off pattern regions 220A; the masking graphics region 210A has two opposite first and second boundaries 210X1 and 210X2 in a second direction (Y direction), the first and second boundaries 210X1 and 210X2 each extending along the first direction (X direction); and, a plurality of the cut-off pattern areas 220A are respectively disposed in regions near the first boundary 210X1 and the second boundary 210X 2.

It will be appreciated that in the photolithography process, the masking pattern region 210A of the mask pattern 200A masks portions that do not need to be exposed, and the intercepting pattern region 220A exposes portions that need to be exposed.

With continued reference to fig. 2, the masking pattern region 210A masks the first sub-patterns of the first feature pattern 100 and exposes each of the first sub-patterns to the truncated pattern region 220A, the portions of the first sub-patterns exposed to the truncated pattern region 220A being in an offset configuration relative to the centerlines 110A-110A 'of the first sub-patterns (i.e., the portions of the first sub-patterns exposed to the truncated pattern region 220A are offset from the centerlines 110A-110A') of the first sub-patterns. The mask pattern 200A is used to define the covered portion of the first sub-pattern as a plurality of divided second sub-patterns (i.e., the defined plurality of second sub-patterns are discontinuous divided patterns). The plurality of divided second sub-patterns form a second feature pattern 100A, and the plurality of second sub-patterns of the second feature pattern 100A have a plurality of protruding sections with respect to the adjacent second sub-patterns (specifically, each of the second sub-patterns has a protruding section protruding from the adjacent second sub-pattern with respect to the adjacent second sub-pattern, and the plurality of second sub-patterns have a plurality of protruding sections correspondingly). And a first node region 121A and a second node region 122A are defined in a plurality of protruding sections of a plurality of second sub-patterns of the second feature pattern 100A, the first node region 121A and the second node region 122A being respectively adjacent to the first boundary 210X1 and the second boundary 210X2 of the mask pattern region such that the first node region 121A and the second node region 122A are adjacent to the cut-off pattern region 220A.

It will be appreciated that in this embodiment, the first feature pattern 100 defined initially is truncated by using the mask pattern 200A to exclude the exposed portion of the first feature pattern, and the remaining first feature pattern forms the second feature pattern 100A. Wherein, since the plurality of truncated pattern regions 220A of the mask pattern 200A are close to the first boundary 210X1 and the second boundary 210X2; that is, it means that the portions of the first feature pattern 100 near the first boundary 210X1 and the second boundary 210X2 and corresponding to the truncated graphic region 220A are removed, and the portions of the first feature pattern 100 near the first boundary 210X1 and the second boundary 210X2 and not corresponding to the truncated graphic region are reserved. Thus, the second feature pattern 100A is structured such that an edge portion thereof adjacent to the first boundary and the second boundary, i.e., the corresponding adjacent truncated pattern region 220A, can be considered to have a large blank area on at least the side facing the truncated pattern region 220A (this corresponding causes the edge portion to protrude from the blank area, constituting the protruding section) such that a large distance exists between the protruding section and other portions in the adjacent second feature pattern (e.g., the protruding section is spaced from other portions in the adjacent second feature pattern by at least the truncated pattern region 220A). At this time, when the edge portion is defined as the first node region 121A and the second node region 122A, it is equivalent to enabling the first node region 121A and the second node region 122A to have a larger blank area at least on the side facing the cut-off pattern region 220A, thereby being advantageous to reduce the difficulty of manufacturing related processes performed on the node regions later.

Specifically, when the semiconductor integrated circuit device is manufactured based on the layout structure, the formed feature film layer corresponding to the second feature pattern 100A has a larger blank area on one side of the node area, so that when the node contact layer needs to be formed on the node area of the feature film layer, on one hand, the formed node contact layer can be prevented from being short-circuited with other adjacent film layers; on the other hand, the area of the node contact layer can be increased, so that the process window of the node contact layer can be effectively increased, and the preparation difficulty of the node contact layer is reduced.

In particular, when the first feature pattern 100 is defined based on the pitch multiplication process (Pitch Doubling), the pitches between the sub-patterns in the first feature pattern 100 are greatly reduced, so that smaller pitches are correspondingly provided between the sub-patterns in the defined second feature pattern 100. At this time, when forming the feature film layer corresponding to the second feature pattern 100A of the layout structure and forming the node contact layer on the node area of the feature film layer, it is inevitable that the film layer on the node area is easily shorted with other adjacent film layers.

In this embodiment, the first feature pattern 100 includes a plurality of first sub-patterns, the first sub-patterns are annular sub-patterns 110, and the second sub-patterns formed by cutting off the annular sub-patterns 110 may be corresponding strip-shaped sub-patterns 110A, i.e. a plurality of strip-shaped sub-patterns 110A form the second feature pattern 100A. Specifically, the plurality of annular sub-patterns 110 are sequentially arranged in parallel along the first direction (X direction), and the annular sub-patterns 110 have two mutually parallel lines 111 extending along the second direction (Y direction) and having two opposite first line ends 111X1 and second line ends 111X2 in the extending direction thereof. The ends of the two lines 111 of the ring-shaped sub-pattern 110 are connected to each other to form a ring-shaped structure by having a connection portion 112.

Based on the first feature pattern 100 defined by the pitch multiplication process, a first feature film layer may be formed by using the pitch multiplication process correspondingly, so that the first feature film layer has the first feature pattern 100, that is, the first feature film layer includes a plurality of first sub-film layers, and the first sub-film layer may be an annular sub-film layer.

Fig. 3a is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a first embodiment of the present invention when the first feature film layer is formed. As shown in fig. 2 and 3a, the method for forming the first feature film layer of the semiconductor integrated circuit device includes:

A first step of forming a plurality of auxiliary lines 11a on a substrate; the auxiliary lines 11a extend along the second direction (Y direction), and the plurality of auxiliary lines 11a are sequentially arranged in the first direction (X direction); the auxiliary lines 11a may be directly defined by a mask, for example, through a photolithography process;

A second step of forming an annular side wall on the side wall of the auxiliary line 11a by using the side wall of the auxiliary line 11a, wherein the annular side wall surrounds the side wall of the auxiliary line 11a, thereby forming an annular sub-film layer 11;

and a third step, removing the auxiliary line 11a, and forming the annular sub-film layer 11 by the remaining annular side wall, so that a plurality of annular sub-film layers 11 in the first characteristic film layer 10, namely, the first characteristic film layer 10 has the pattern of the first characteristic pattern 100, can be formed on the substrate.

It should be appreciated that, among the auxiliary lines 11a directly defined by performing the photolithography process using the reticle, the formed auxiliary lines 11a have a minimum width dimension capable of achieving only a minimum line width feature size, and the adjacent auxiliary lines 11a have a minimum pitch capable of achieving only a minimum pitch feature size of the photolithography process, due to the limitation of the photolithography process window. When the sidewalls of the auxiliary lines 11a are used in combination with the pitch multiplication process, lines with smaller line pitches and line widths can be formed, i.e., the width dimension of a single line of the annular sub-film 11 in the first feature film 10 is much smaller than the minimum line width feature size, and the spacing dimension between adjacent annular sub-film 11 in the first feature film 10 is much smaller than the minimum pitch feature size.

Specifically, in this embodiment, when the N auxiliary lines 11a are directly defined by using the photolithography process, if the line width of the auxiliary line 11a is equal to the minimum line width feature size under the limit condition of the photolithography process, and the parallel pitch of the adjacent auxiliary lines 11a is equal to the minimum pitch feature size under the limit condition of the photolithography process. However, in the further pitch multiplication process, namely, 2N lines 111 extending in the same direction can be formed, the number of line arrangements can be defined 2 times on the same substrate size by the pitch multiplication process, compared to the case where the auxiliary lines 11a are defined directly by the photolithography process.

Accordingly, in the layout structure, the width dimension of a single line of the annular sub-pattern 110 of the first feature pattern 100 is much smaller than the minimum line width feature dimension of the photolithography process, and the space dimension between adjacent annular sub-patterns 110 in the first feature pattern 100 is much smaller than the minimum pitch feature dimension of the photolithography process.

Further, the first feature pattern 100 includes a plurality of annular sub-patterns 110, and then one annular sub-pattern 110 in the first feature pattern 100 may be truncated into two spaced-apart stripe sub-patterns 110A by using the mask pattern 200A, and the second feature pattern 100A is formed by the stripe sub-patterns 110A.

With continued reference to fig. 2, the masking pattern region 210A of the mask pattern 200A masks the middle region of each annular sub-pattern 110 in the first feature pattern, and extends to cover the annular sub-pattern 110 in the two end directions of the annular sub-pattern 110 in the second direction, and the truncated pattern region 220A corresponding to the first boundary 210X1 exposes the first line end 111X1 of one line 111 of the annular sub-pattern 110, and the truncated pattern region 220A corresponding to the second boundary 210X2 exposes the second line end 111X2 of the other line 111 of the annular sub-pattern 110. In this way, one of the annular sub-patterns 110 in the first feature pattern 100 can be defined as two mutually separated strip-shaped sub-patterns 110A, and the two cut-off pattern areas 220A expose different lines of the same annular sub-pattern 110 respectively, so that the two defined strip-shaped sub-patterns 110A have the same or similar length dimensions.

Further, the number of the truncated pattern areas 220A in the mask pattern 200A may be set according to the number of the annular sub-patterns in the first feature pattern, for example, one annular sub-pattern 110 corresponds to two truncated pattern areas 220A. In this embodiment, the first feature pattern 100 includes N annular sub-patterns 110, so that 2N truncated pattern regions 220A are correspondingly disposed in the mask pattern 200A, and 2N truncated pattern regions 220A are disposed in the regions near the first boundary 210X1 and the second boundary 210X2, respectively, in an average number. At this time, the N truncated pattern areas 220A corresponding to the first boundary 210X1 expose the first line ends 111X1 of the first lines of the N annular sub-patterns 110, and the N truncated pattern areas 220A corresponding to the second boundary 210X2 expose the second line ends 111X2 of the second lines of the N annular sub-patterns 110. That is, the same annular sub-pattern 110 corresponds to two cut-off pattern areas 220A and is disposed on both ends of the annular sub-pattern 110, respectively, to cut off one of the annular sub-patterns 110 into 2 strip-shaped sub-patterns 110A, thereby defining 2N strip-shaped sub-patterns 110A separated from each other by N annular sub-patterns 110.

With continued reference to fig. 2, in this embodiment, the truncated graphic region 220A is located in a region between the first boundary 210X1 and the second boundary 210X2 of the cover graphic region 210A so as to surround the truncated graphic region 220A by the cover graphic region 210A. That is, the cut-off pattern area 220 in the present embodiment is surrounded by the cover pattern area 210A, and constitutes a closed cut-off pattern area 220A. The truncated graphic region 220A has a rectangular, circular, oval or the like shape and corresponds to the end of the line 111 of the ring-shaped sub-pattern 110.

In addition, the connection of the ends of the two lines 111 of the ring-shaped sub-pattern 110 forms a connection 112. In this embodiment, the closed-type cut-off pattern region 220A exposes only the line end of the annular sub-pattern 110, but does not expose the connection portion 112 of the annular sub-pattern 110 (i.e., the covering pattern region 210A covers the connection portion 112 of the annular sub-pattern 110) to define the annular sub-pattern into two of the strip-shaped sub-patterns from the line end of the annular sub-pattern 110, so that the strip-shaped sub-pattern 110A defined by the annular sub-pattern 110 includes a portion of the line 111 and the connection portion 112. In this embodiment, the shape of the defined stripe sub-pattern 110A may be L-shaped, for example. Further, the first node region 121A and the second node region 122A may be defined on each of the defined stripe sub-patterns 110A to prepare specific elements on the first node region 121A and the second node region 122A in a subsequent process. In this embodiment, the connection portion 112 of the strip-shaped sub-pattern 110A protrudes with respect to the adjacent strip-shaped sub-pattern 110A to form a protruding section, so that the first node area 121A and the second node area 122A can be defined on the connection portion 112 of the strip-shaped sub-pattern 110A. Each of the sub-stripe patterns 110A defines a node area, wherein the connection portion of the sub-stripe pattern 110A is close to the first boundary, the defined node area may be considered as a first node area 121A, and the connection portion of the sub-stripe pattern 110A is close to the second boundary, the defined node area may be considered as a second node area 122A.

Fig. 3b is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to an embodiment of the present invention, in which a second feature film layer is formed. As shown in fig. 2 and fig. 3a to 3b, the method of forming the second feature film layer having the second feature pattern based on the first feature film layer 10 formed in fig. 3a may refer to the following steps.

Step one, referring specifically to fig. 3a, a first feature film 10 is formed on a substrate. As described above, the first feature film 10 includes at least one first sub-film. In this embodiment, the first feature film 10 includes a plurality of first sub-films 11, which are annular sub-films and thus can be formed by a pitch multiplication process.

Step two, referring to fig. 2 and 3b, a masking mask layer is formed on the first feature film layer 10, where the masking mask layer has the mask pattern 200A in the layout structure. That is, the masking mask layer has a masking pattern region having two opposite first and second boundaries in a second direction, each of the first and second boundaries extending along the first direction, and a plurality of intercepting pattern regions provided in regions near the first and second boundaries, respectively. The masking pattern region of the masking mask layer is used to mask the first sub-film layers of the first feature film layer 10, and each first sub-film layer is partially exposed to the truncated pattern region, and the part of the first sub-film layer exposed to the truncated pattern region is offset relative to the central line 10a-10a' of the first feature film layer 10.

In this embodiment, the covering mask layer extends from the middle area of the annular sub-film layer 11 of the first feature film layer 10 to the end direction thereof to cover the annular sub-film layer 11, and two lines in the same annular sub-film layer 11 have ends extending in opposite directions exposed from the truncated pattern area, where the truncated pattern area is offset with respect to the center line of the annular sub-film layer 11.

Step three, referring to fig. 2 and fig. 3b, the masking film layer is used as a mask to etch the first sub-film layer of the first feature film layer, the removed area in the first feature film layer forms a blank area, the reserved part in the first sub-film layer of the first feature film layer forms a plurality of divided second sub-film layers, and a plurality of second sub-film layers form a second feature film layer 10A. In this embodiment, one annular sub-film 11 in the first feature film 10 is divided into two strip-shaped sub-films 11A, and the second feature film 10A is formed by a plurality of strip-shaped sub-films 11A. Thus, even if the second feature film 10A is formed to have the second feature pattern 100A as in the layout structure.

And, in the second feature film 10A, an end of each second sub-film (i.e., the strip-shaped sub-film 11A) thereof is adjacent to the blank area, and the strip-shaped sub-film has a protruding section with respect to other adjacent sub-films based on the blank area, so that a plurality of node areas can be defined in the protruding section. Accordingly, the plurality of strip-shaped sub-film layers 11A have a plurality of protruding sections, respectively, and a first node area is defined in the plurality of protruding sections near the first boundary, and a second node area is defined in the plurality of protruding sections near the second boundary, the first node area and the second node area being adjacent to the white space.

Specifically, the strip-shaped sub-film layer 11A has a first film layer end and a second film layer end opposite to each other, and one strip-shaped sub-film layer has a first node area and is located at the first film layer end, and the other strip-shaped sub-film layer has a second node area and is located at the second film layer end in the two adjacent strip-shaped sub-film layers 11A. It will be appreciated that the first and second film ends of each strip of sub-film extending in opposite directions are adjacent to the blank space, so that the node areas may be disposed on the first and second film ends, and that the node areas in adjacent strip of sub-film may also be staggered (i.e., disposed at the first and second film ends, respectively), so as to facilitate increasing the spacing of adjacent node contact layers 12A formed.

Further, the shape of the strip-shaped sub-film layer 11A is close to an "L" shape, which corresponds to the strip-shaped sub-pattern 110A of the second feature pattern, and the arrangement of the first node area and the second node area can also refer to the arrangement of the first node area 121A and the second node area 122A in fig. 2.

Step four, with continued reference to fig. 3b, after forming the second feature film layer 10A, further includes: a node contact layer 12A is formed on the first node region and the second node region of the second feature film layer 10A. In this embodiment, the node contact layer 12A is formed on an end portion of the strip-shaped sub-film layer 11A.

As described above, the first node area and the second node area on the second feature film layer are adjacent to the blank area, i.e., reserved for a larger formation space of the node contact layer 12A, so that the problem that the formed node contact layer 12A is shorted with the adjacent film layer can be improved, and the size of the node contact layer 12A can be increased, which is also beneficial to improving the process window of the node contact layer.

Specifically, the semiconductor integrated circuit device is, for example, an integrated circuit memory, the strip-shaped sub-film layer 11A may further form a bit line of the memory, and the node junction contact layer 12A may be a contact pad of the bit line, that is, the contact pad is electrically connected to the bit line, for guiding out the bit line. Therefore, in the present embodiment, since the contact pad (node contact layer 12A) with larger size can be formed, the contact resistance between the contact pad and the bit line can be effectively reduced, and the process window of the contact pad can be increased, so that the quality of the formed contact pad can be further ensured.

Example two

Fig. 4 is a schematic structural diagram of a layout structure in a second embodiment of the present invention. As shown in fig. 2 and 4, the difference between the present embodiment and the first embodiment is that: the cut-off pattern region of the mask pattern is a non-closed cut-off pattern region.

As shown in fig. 4, the first feature pattern 100 in this embodiment has a plurality of annular sub-patterns 110. And, in the mask pattern 200B, the intercepting pattern region 220B is located on the first boundary 210X1 or the second boundary 210X2 of the covering pattern region 210B and extends from the first boundary 210X1 or the second boundary 210X2 toward the center of the covering pattern region 210B such that the intercepting pattern region 220B is embedded into the covering pattern region 210B from the first boundary 210X1 or the second boundary 210X2, and a plurality of intercepting pattern regions 220B communicate with each other outside the boundary of the covering pattern region 210B.

It can be considered that, in the present embodiment, the first boundary 210X1 and the second boundary 210X2 of the covering graphic region 210B are both waveform boundaries, and the waveform boundaries of the first boundary 210X1 and the second boundary 210X2 may be further waveform boundaries of rectangular structure, and the waveform boundaries of the first boundary 210X1 have peaks and troughs corresponding to the waveform boundaries of the second boundary 210X2 (for example, the peaks of the first boundary 210X1 and the peaks of the second boundary 210X2 have positions corresponding to the peaks of the waveform boundary, and the troughs of the first boundary 210X1 and the troughs of the waveform boundary of the second boundary 210X2 have positions corresponding to the peaks of the cut-off graphic region 220B corresponding to the first boundary 210X1 and the cut-off graphic region 220B corresponding to the second boundary 210X2 respectively expose two different lines 111 in each annular sub-pattern 110.

Thus, the non-closed cut-off pattern area in the present embodiment is constituted. It will be appreciated that the first boundary 210X1 and the second boundary 210X2 of the masking pattern region 210B form the boundary of the truncated pattern region 220B adjacent to the masking pattern region 210B; or the first boundary 210X1 and the second boundary 210X2 are the boundary line between the covering pattern area 210B and the intercepting pattern area 220B.

With continued reference to fig. 4, similar to the embodiment, the truncated pattern area 220B corresponding to the first boundary 210X1 exposes the first line end 111X1 of one line of the ring-shaped sub-pattern 110, and the truncated pattern area 220B corresponding to the second boundary 210X2 exposes the second line end 111X2 of the other line of the ring-shaped sub-pattern 110. For example, the covering pattern area 210B extends on the first boundary 210X1 to cover the first line end 111X1 of the first line of the annular sub-pattern 110, and the truncated pattern area 220B corresponding to the first boundary 210X1 exposes the first line end 111X1 of the second line of the annular sub-pattern 110; similarly, the covering pattern region 210B extends on the second boundary 210X2 to cover the second line end 111X2 of the second line of the annular sub-pattern 110, and the truncated pattern region 220B corresponding to the second boundary 210X2 exposes the second line end 111X2 of the first line of the annular sub-pattern 110. Thus, in the two adjacent stripe sub-patterns 110B, one end of one stripe sub-pattern extends out with respect to the end of the other stripe sub-pattern, i.e. one of the stripe sub-patterns has one end extending out with respect to the other stripe sub-pattern, so that the extending out end can be used to form a protruding section.

Further, the truncated graphic region 220B in the present embodiment is embedded into the cover graphic region 210B from the boundary of the cover graphic region 210B, and a plurality of the truncated graphic regions 220B communicate with each other outside the boundary of the cover graphic region 210B. Therefore, in this embodiment, the truncated graphic region 220B extends to expose a portion of the connection portion 112 in a direction away from the center of the cover graphic region on the basis of exposing an end of one of the lines of the annular sub-pattern 110.

Thus, in this embodiment, the defined stripe sub-pattern 110B may include the line 111 and a portion of the connecting portion 112, where the end portion of the line 111 and the connecting portion 112 together form a protruding section. Further, a first node region 121B and a second node region 122B may be defined at corner junctions of the line 111 and the connection portion 112 in the stripe sub-pattern 110B.

Fig. 5 is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a second embodiment of the present invention when the second feature film layer is formed. Wherein the step of forming a second feature film layer having a second feature pattern includes:

first, a first feature film 10 is formed on the substrate, and the first feature film 10 may include a plurality of ring-shaped sub-patterns, which may be referred to as embodiment one;

next, as shown in fig. 4, a masking mask layer is formed on the first feature film layer 10, where the pattern of the masking mask layer corresponds to the mask pattern in this embodiment;

Next, referring to fig. 5, the first feature film layer is etched to form a second feature film layer 10B; wherein, one annular sub-film 11 in the first feature film 10 is divided into two strip-shaped sub-films 11B, and the second feature film 10B is formed by a plurality of strip-shaped sub-films 11B.

In this embodiment, the pattern of the strip-shaped sub-film layer 11B of the second feature film layer 10B corresponds to the strip-shaped sub-pattern 110B of the second feature pattern 100B shown in fig. 4, so the strip-shaped sub-film layer 11B of the second feature film layer 10B has a first extension portion and a second extension portion connected thereto, and the first extension portion and the second extension portion respectively correspond to the line 111 and the part of the connection portion 112 shown in fig. 4.

Next, as shown in fig. 5, a node contact layer 12B is formed at the corner junction of the first extension and the second extension of the strip-shaped sub-film layer 11B, that is, at the corner junction of the first extension and the second extension, a node region (corresponding to 121B and 122B described in fig. 4) is defined, and the node contact layer 12B is formed on the node region.

Example III

In this embodiment, the truncated pattern region of the mask pattern is also an unsealed truncated pattern region. And compared with the embodiment, the truncated pattern area in the embodiment further exposes all the connection parts of the annular sub-pattern.

Fig. 6a is a schematic diagram of one layout structure in the third embodiment of the present invention, as shown in fig. 6a, in the mask pattern 200C, each of the truncated pattern regions 220C exposes an end portion of one of the lines 111 of the ring-shaped sub-pattern 110, and a plurality of truncated pattern regions 220C are mutually connected at a side far from the covering pattern region and further expose all the connection portions 112 of the ring-shaped sub-pattern 110. That is, the cover pattern region 210C of the mask pattern 200C covers only the lines 111 of the annular sub-pattern 110, so that the stripe sub-pattern 110C of the second feature pattern 100C may be constituted by the lines 111 of the annular sub-pattern.

The layout structure in this embodiment may define a linear stripe sub-pattern 110C. In the adjacent stripe sub-patterns 110C, the end of one stripe sub-pattern 110C extends and protrudes with respect to the end of the other stripe sub-pattern adjacent thereto, and the protruding end constitutes a protruding section. For example, in the same annular sub-pattern 110, a first line end of the line of the first stripe sub-pattern 110C extends with respect to a first line end of the line of the second stripe sub-pattern 110C, and a second line end of the line of the second stripe sub-pattern extends with respect to a second line end of the line of the first stripe sub-pattern.

Since in the present embodiment, the linear stripe sub-patterns 110C are formed, and one end of each stripe sub-pattern 110C extends from the adjacent stripe sub-pattern, the first node area 121C and the second node area 122C can be directly defined on the extending end of the stripe sub-pattern 110C.

In addition, the first and second boundaries of the mask pattern region 210C shown in fig. 6a are rectangular wave boundaries. It should be appreciated, however, that the first and second boundaries of the mask pattern region may also be arcuate wave boundaries (e.g., present as a wave-like structure).

For example, referring to fig. 6b, fig. 6b is a schematic diagram of another layout structure according to the third embodiment of the present invention. In fig. 6b, the first and second boundaries of the masking pattern region 210D of the mask pattern 200D are wavy boundaries of a wavy structure, and the corresponding truncated pattern region 220D is also embedded in the masking pattern region 210D with a curved boundary.

Referring to fig. 6a and 6b in combination, the stripe sub-pattern 110D of the second feature pattern 100D defined in fig. 6b is similar to the stripe sub-pattern 110C of the second feature pattern 100C defined in fig. 6a, and linear stripe sub-patterns can be defined. In the second feature pattern 100D defined in fig. 6b, the first node area 121D and the second node area 122D may be directly defined on the extending ends of the stripe sub-pattern 110D.

Fig. 7 is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a third embodiment of the present invention for preparing a second feature film. As shown in fig. 7, the forming method includes the following steps.

First, a first feature film layer is formed on a substrate, where the first feature film layer has a first feature pattern, and reference may be made to the first embodiment and the second embodiment, which are not described herein.

Next, a capping mask layer is formed on the first feature film layer, the capping mask layer having a mask pattern such as shown in fig. 6a or 6 b.

Then, the first feature film layer is etched, and a second feature film layer 10C is formed, and the formed second feature film layer 10C corresponds to the second feature pattern shown in fig. 6a or fig. 6b. That is, the second characteristic film layer 10C includes a plurality of linear strip-shaped sub-film layers 11C. And, after forming the second feature film layer 10C, the node contact layer 12C may be continuously formed on the end of the strip-shaped sub-film layer 11C.

It should be noted that, the semiconductor integrated circuit devices in the first to third embodiments may be, for example, integrated circuit memories, and the second feature patterns defined by the layout structures in the above embodiments may further correspond to a plurality of bit lines of the integrated circuit memories. The second characteristic film layer (10A/10B/10C) formed by the layout structure is a bit line in the memory, and each of the second characteristic film layers (11A/11B/11C) is a bit line. And node contact layers (12A/12B/12C) subsequently formed on each strip-like sub-film layer, i.e., on the ends of the bit lines, respectively.

Furthermore, the layout structure described above can also be used to form word lines of an integrated circuit memory. Specifically, each of the sub-film layers formed by the layout structure described above constitutes one word line. And a node contact layer formed on each strip-shaped sub-film layer in a subsequent mode, namely formed on the end part of the word line correspondingly, and used for leading out the word line.

In summary, in the embodiment, when the first sub-pattern is truncated into a plurality of divided second sub-patterns by using the mask pattern, the portion of the first sub-pattern exposed in the truncated pattern region is offset with respect to the center line of the first sub-pattern, so that the divided second sub-pattern has a protruding section protruding with respect to the adjacent second sub-pattern, and a larger blank area exists on the periphery of the protruding section of the second sub-pattern. Based on the above, the protruding section is defined as a node area, namely, the outer periphery of the node area can have a larger blank area, so that the preparation difficulty of the related process executed on the node area in the following process is reduced.

Example IV

The difference from the above-described embodiment is that in the present embodiment, the first feature pattern includes a plurality of island-like sub-patterns, and the plurality of island-like sub-patterns in the second direction are aligned and arranged, and the plurality of island-like sub-patterns in the first direction are staggered from each other to assume a waveform arrangement.

Fig. 8 is a schematic diagram of a layout structure in a fourth embodiment of the present invention, as shown in fig. 8, the first feature pattern 300 includes a plurality of island sub-patterns 310, and the island sub-patterns 310 in the second direction (Y direction) are aligned, and the island sub-patterns 310 in the first direction (X direction) are staggered to each other to present a waveform arrangement. In this embodiment, the plurality of island sub-patterns 310 further exhibit a hexagonal array arrangement, i.e., six island sub-patterns of the same island sub-pattern that are equidistant from adjacent island sub-patterns in the plurality of island sub-patterns 310 exhibit a hexagonal array arrangement.

As described with reference to fig. 8, a mask pattern 400 in this embodiment is disposed above the first feature pattern 300, where the mask pattern has a covering pattern area 410 and a plurality of intercepting pattern areas 420, and the covering pattern area 410 has two opposite first boundaries and second boundaries in the second direction (Y direction), where the first boundaries and the second boundaries each extend along a waveform in the first direction (X direction) (for example, as shown with reference to fig. 8, a covering pattern area boundary 410X1 of the covering pattern area 410 extends in a waveform) so as to correspond to the waveform arrangement of the island-shaped sub-pattern 310 in the first direction; and a plurality of the truncated graphic regions 420 are respectively disposed in regions near the first and second boundaries.

In this embodiment, the mask pattern 400 is used to intercept a portion of the island sub-patterns from the island sub-patterns 310 of the first feature pattern 300 to define a second feature pattern 300A.

Further, the first boundary and the second boundary (for example, reference to the cover pattern region boundary 410X 1) are recessed to the boundary of the cover pattern region 410, that is, define a plurality of the truncated pattern regions 420, and the plurality of the truncated pattern regions 420 corresponding to the same boundary communicate with each other outside the cover pattern region 410.

Thus, a portion of the island sub-patterns 310 in the first feature pattern 300 may be masked with the masking pattern region 410 of the mask pattern 400 to define the plurality of island sub-patterns 310 masked in the first feature pattern as second feature patterns 300A.

In this embodiment, the island sub-pattern 310 of the second feature pattern 300A near the mask pattern region boundary 410X1 may be defined as a node region. That is, the plurality of node areas defined in the second feature pattern 300A are respectively adjacent to the first boundary and the second boundary of the masking pattern area such that the node areas are adjacent to the truncated pattern area 420. In addition, in the present embodiment, all island sub-patterns 310 in the second feature pattern 300A may also be defined as node areas.

The first feature pattern 300 may also be defined based on a pitch multiplication process, so that each island-shaped sub-pattern 310 in the defined first feature pattern 300 may have a smaller pitch, and a denser arrangement of a plurality of island-shaped sub-patterns 310 may be realized. Thus, a first feature film layer having the first feature pattern 300 may also be formed based on a pitch multiplication process. The method of forming the first feature film layer by the pitch multiplication process in this embodiment is explained below with reference to the drawings.

Method one

Fig. 9a is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a fourth embodiment of the present invention when one of the methods is used to prepare a first feature film, and particularly, referring to fig. 9a, the method for forming a first feature film includes the following steps.

In the first step, a plurality of first lines 31a are formed on a substrate, and the plurality of first lines 31a are arranged parallel to each other.

Wherein, the first lines 31a may be formed by a pitch multiplication process, for example, as shown in fig. 3a of the first embodiment: firstly, forming a plurality of auxiliary lines on a substrate; then, forming an annular side wall on the side wall of the auxiliary line by using the side wall of the auxiliary line; and then removing the auxiliary lines, so that a plurality of annular sub-film layers can be formed. The annular sub-film layer comprises two first lines 31a parallel to each other, and the space between the adjacent first lines 31a is much smaller than the minimum pitch feature size of the photolithography process.

Step two, forming a plurality of second lines 31b on the substrate, wherein the second lines 31b intersect with the first lines 31a, so that a plurality of overlapping areas are formed between the first lines 31a and the second lines 31 b; it is considered that the overlapping area corresponds to the portion of the first line 31a covered by the second line 31 b.

The second lines 31b may also be formed by a pitch multiplication process. And the angle of the acute angle between the first line 31a and the second line 31b is, for example, 50 ° to 70 °, so that the overlapping areas defined by the first line 31a and the second line 31b are arranged in a hexagonal array.

And thirdly, etching the first line by using the second line 31b as a mask, so that a part of the first line corresponding to the overlapping region is reserved, thereby forming a plurality of island-shaped sub-film layers 31, and forming a first characteristic film layer 30 by the island-shaped sub-film layers 31, wherein the island-shaped sub-film layers 31 in the embodiment are arranged in a hexagonal array.

Because the first lines 31a and the second lines 31b are formed by a pitch multiplication process, the first lines 31a and the second lines 31b with smaller sizes can be formed, and the plurality of first lines 31a and the plurality of second lines 31b have higher arrangement density, so that the defined island-shaped sub-film 31 has smaller sizes and higher arrangement density correspondingly.

Thus, the first feature film 30 may have the first feature pattern 300 shown in fig. 8, that is, the first feature film 30 includes a plurality of island-shaped sub-films 31, and the island-shaped sub-films 31 in the first direction (X direction) are staggered to each other to form a wave arrangement.

Method II

Fig. 9b is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a fourth embodiment of the present invention, in which a first feature film layer is formed by another method. Referring specifically to fig. 9b, a second method for forming the first feature film layer by using a pitch multiplication process includes the following steps.

In the first step, a plurality of first island-like sub-film layers 31a 'are formed on a substrate, and a first space dimension is provided between adjacent first island-like sub-film layers 31 a'. The first island-shaped sub-film layers 31a 'may be directly formed by using a photolithography process, so that the first spacing dimension between adjacent first island-shaped sub-film layers 31a' is greater than or equal to the minimum pitch feature dimension of the photolithography process.

In this embodiment, the explanation is given taking the case that the finally formed first feature film layer includes island-shaped sub-film layers arranged in a hexagonal array, and based on this, the plurality of first island-shaped sub-film layers 31a 'may be arranged in a triangular array, that is, three adjacent first island-shaped sub-film layers 31a' respectively form three vertex angles of a triangle so as to surround the triangle.

Step two, forming a plurality of second island-shaped sub-film layers 31b 'on a substrate, wherein a second interval dimension is provided between adjacent second island-shaped sub-film layers 31b', and the second island-shaped sub-film layers 31b 'are embedded between adjacent first island-shaped sub-film layers 31a', so that the limitation of the precision of the photoetching process can be overcome, and the first island-shaped sub-film layers 31a 'and the second island-shaped sub-film layers 31b' have higher arrangement density.

In this embodiment, the second spacing dimension between adjacent second island sub-film layers 31b 'may be the same as or similar to the first spacing dimension between adjacent first island sub-film layers 31 a'. And, the plurality of second island-shaped sub-film layers 31b 'may be arranged in a triangular array, that is, three adjacent second island-shaped sub-film layers 31b' respectively form three vertex angles of a triangle so as to surround the triangle. In addition, the triangle surrounded by the second island sub-film 31b 'is inverted triangle with respect to the triangle surrounded by the first island sub-film 31a', so that after the inverted triangle of the second island sub-film 31b 'and the regular triangle of the first island sub-film 31a' are nested with each other, three of the first island sub-films and three of the second island sub-films can be arranged in a hexagonal shape, that is, a hexagon is further surrounded.

It should be noted that the "inverted triangle" and the "regular triangle" described herein are relatively speaking, and thus the second island-shaped sub-film layer 31b 'may also be considered to surround the regular triangle, and the first island-shaped sub-film layer 31a' may surround the inverted triangle.

At this time, a plurality of island-like sub-film layers densely arranged can be formed. In this embodiment, the arrangement density of the finally formed first feature film layer may be further improved based on the island-shaped sub-film layers arranged in a hexagonal manner. That is, the following steps may also be included.

Step three, forming a sacrificial film 31d 'on the sidewalls of the first island-shaped sub-film 31a' and the second island-shaped sub-film 31b ', wherein in each hexagon, the sacrificial films 31d' on the sidewalls of six island-shaped sub-films are connected to each other, and a hollow is formed around the hollow in the center region of the hexagon.

And step four, filling the third island-shaped sub-film layer 31c 'in the cavity, and removing the sacrificial film layer, thereby forming a first characteristic film layer consisting of the first island-shaped sub-film layer 31a', the second island-shaped sub-film layer 31b 'and the third island-shaped sub-film layer 31 a'. The first island sub-film layer, the second island sub-film layer and the third island sub-film layer all form an island sub-film layer 31 in the first feature film layer 30, and correspond to the island sub-pattern 310 in the first feature pattern 300 shown in fig. 8.

After forming the first feature film 30, a capping mask layer having a mask pattern 400 shown in fig. 8 may be further formed to intercept a portion of the first feature film 30 and form a second feature film. Fig. 10 is a schematic structural diagram of a method for forming a semiconductor integrated circuit device according to a fourth embodiment of the present invention, in which a second feature film layer is formed. The method of forming the second feature film layer in this embodiment is explained below with reference to the drawings.

In a first step, a first feature film 30 is formed on a substrate, and the first feature film 30 may be formed by a pitch multiplication process as shown in fig. 9a or 9 b.

In a second step, referring to fig. 8, a capping mask layer is formed on the substrate, the capping mask layer capping the mask pattern 300A shown in fig. 8. That is, the covering mask layer has a covering pattern region and a plurality of intercepting pattern regions, the covering pattern region has two opposite first and second boundaries in the second direction, each of the first and second boundaries extends along the first direction in a wave form, and covers a portion of the island sub-film layer 31 in a wave form arrangement corresponding to the island sub-film layer 31 in the first direction, so that the covered island sub-film layers of the first feature film layer 30 may be defined as the second feature film layer 30A.

In a third step, referring to fig. 10 specifically, the first feature film layer is etched by the masking film layer, and the island-shaped sub-film layer exposed in the first feature film layer is removed to form a blank area, and the masked island-shaped sub-film layer 31 in the first feature film layer is remained to form the second feature film layer 30A.

As described above, in this embodiment, the island-shaped sub-film layer near the boundary of the masking film layer may be directly defined as the node region, so that the corresponding process is performed in the subsequent process, that is, based on the island-shaped sub-film layer 31. In this embodiment, all island sub-layers 31 in the second feature layer 30A are further defined as node areas.

Alternatively, an array of through holes may be further formed based on the island-shaped sub-film layer array of the formed second feature film layer 30A, where the pattern of the through hole array also corresponds to the second feature pattern 300A in the layout structure shown in fig. 8.

Fig. 11 to 12 are schematic structural views of a method for forming a semiconductor integrated circuit device according to a fourth embodiment of the present invention, in which a via array is formed.

First, as shown in fig. 11, after the second feature film 30A is formed, a filling dielectric material layer 32 is formed around the outer periphery of the island-like sub-film 31 of the second feature film 30A, the dielectric material layer 32 fills the region between adjacent island-like sub-films 31, and the island-like sub-film 31 is exposed.

Next, as described with reference to fig. 12, the island-like sub-film layer 31 is removed to form a plurality of through holes 33 in the dielectric material layer 32, so that a through hole array 33A corresponding to the second feature pattern 300A in the layout structure can be formed.

In this embodiment, the semiconductor integrated circuit device may be an integrated circuit memory, and further may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), where the via array 33A is formed, for example, to further form a capacitor array, and one via is used to form one capacitor, so that the formed capacitor has a cylindrical structure corresponding to the via shape. Therefore, in the forming method based on the integrated circuit memory, after the via hole array is formed, a lower electrode, a capacitance medium layer and an upper electrode may be further formed in the via hole in order to form a storage capacitor.

In this embodiment, the island-shaped array is formed by using the pitch multiplication process, so that the formed via array is also correspondingly based on the pitch multiplication process, thereby effectively improving the arrangement density of a plurality of vias in the via array, and corresponding to the subsequently formed capacitor array, the arrangement density of a plurality of capacitors can be effectively improved.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. A layout structure, comprising:

A first feature pattern comprising at least one first sub-pattern; and

The masking pattern region of the mask pattern masks the first sub-pattern of the first feature pattern, and each of the first sub-pattern portions is exposed to the truncated pattern region, the portions of the first sub-pattern exposed to the truncated pattern region are arranged in an offset manner relative to the center line of the first sub-pattern, and the masked portions of the first sub-pattern are defined into a plurality of divided second sub-patterns, the plurality of second sub-patterns form a second feature pattern, and a plurality of first node regions and second node regions are defined in a plurality of protruding sections of the second feature pattern relative to adjacent second sub-patterns, the first node regions and the second node regions being respectively adjacent to the first boundary and the second boundary of the masking pattern region, so that the first node regions and the second node regions are adjacent to the truncated pattern region.

2. The layout structure according to claim 1, wherein the first feature pattern includes a plurality of first sub-patterns, the first sub-patterns are ring-shaped sub-patterns, and the plurality of ring-shaped sub-patterns are sequentially arranged in parallel along the first direction; and the annular sub-pattern is provided with two mutually parallel lines, the lines extend along the second direction and are provided with two opposite first line ends and second line ends in the extending direction, and the ends of the two lines of the annular sub-pattern are mutually connected and provided with connecting parts.

3. The layout structure according to claim 2, wherein the covering pattern region of the mask pattern extends from a middle region to an end of the annular sub-pattern to cover the annular sub-pattern, and the intercepting pattern region corresponding to the first boundary exposes a first line end of one line of the annular sub-pattern, and the intercepting pattern region corresponding to the second boundary exposes a second line end of another line of the annular sub-pattern, so as to define one of the annular sub-patterns in the first feature pattern into two mutually separated stripe sub-patterns, and the second feature pattern is constituted by a plurality of the stripe sub-patterns.

4. A layout structure according to claim 3, wherein the cut-off pattern region is located in an area between the first and second boundaries of the mask pattern region to surround the cut-off pattern region by the mask pattern region.

5. The layout structure according to claim 4, wherein the covering pattern region of the mask pattern covers the connection portion of the annular sub-pattern to define the annular sub-pattern into two of the strip-shaped sub-patterns from a line end portion of the annular sub-pattern, and the strip-shaped sub-pattern is constituted by the line and the connection portion, and the first node region and the second node region are defined on the connection portion of the strip-shaped sub-pattern.

6. The layout structure according to claim 4, wherein the shape of the truncated graphic region comprises a rectangle, a circle, or an ellipse.

7. A layout structure according to claim 3, wherein said cut-off pattern region is located on said first boundary or said second boundary of said mask pattern region and extends from said first boundary or said second boundary toward the center of said mask pattern region so that said cut-off pattern region is embedded into said mask pattern region from said first boundary or said second boundary, and a plurality of said cut-off pattern regions corresponding to the same boundary communicate with each other outside the boundary of said mask pattern region.

8. The layout structure according to claim 7, wherein each of the truncated pattern regions of the mask pattern exposes an end of one of the lines in the ring-shaped sub-pattern and extends away from a center of the mask pattern region to expose at least a portion of the connection portion.

9. The layout structure according to claim 8, wherein the lines and portions of the connection portions in the ring-shaped sub-pattern constitute a stripe sub-pattern in the second feature pattern, and the first node area and the second node area are defined at corner connections of the lines and the connection portions in the stripe sub-pattern.

10. The layout structure according to claim 8, wherein the cut-off pattern region of the mask pattern also exposes all of the connection portions of the ring-shaped sub-patterns, and a stripe sub-pattern in the second feature pattern is constituted by lines in the ring-shaped sub-patterns, the first node region and the second node region being defined on ends of the stripe sub-pattern.

11. The layout structure according to claim 7, wherein in the mask pattern, the first boundary and the second boundary of the masking pattern region are both waveform boundaries, and the peaks and the valleys of the first boundary and the peaks and the valleys of the second boundary correspond to each other so that the truncated pattern region corresponding to the first boundary and the truncated pattern region corresponding to the second boundary expose two different lines in each ring-shaped sub-pattern, respectively.

12. The layout structure according to claim 11, wherein the first boundary and the second boundary are both rectangular wave boundaries or arcuate wave boundaries.

13. The layout structure according to any one of claims 3-12, wherein the parallel spacing dimension between adjacent stripe sub-patterns is smaller than the minimum pitch feature dimension of the photolithographic process.

14. A layout structure, comprising:

15. The layout structure according to claim 14, wherein the boundaries recessed into the masking pattern region in the first boundary and the second boundary define a plurality of the cutoff pattern regions, and the plurality of cutoff pattern regions corresponding to the same boundary communicate with each other outside the masking pattern region.

16. The layout structure according to claim 14, wherein the masking pattern region masks a portion of the island sub-patterns in the first feature pattern to define a plurality of the masked island sub-patterns in the first feature pattern as second feature patterns, and at least a portion of the island sub-patterns in the second feature pattern near the first boundary and the second boundary is defined as the node region.

17. A layout structure according to any one of claims 14 to 16 wherein the size of the space between adjacent island sub-patterns is less than the minimum pitch feature size of the lithographic process.

18. A method of forming a semiconductor integrated circuit device, comprising:

19. The method of forming a semiconductor integrated circuit device of claim 18, wherein the first feature film comprises a plurality of first sub-films, the first sub-film being a ring-shaped sub-film, the plurality of ring-shaped sub-films being sequentially arranged in parallel along a first direction; and dividing each annular sub-film layer in the first characteristic film layer into two mutually separated strip-shaped sub-film layers by utilizing the covering mask layer, and forming the second characteristic film layer by a plurality of strip-shaped sub-film layers.

20. The method of forming a semiconductor integrated circuit device as recited in claim 19, wherein the first feature film layer is formed using a pitch multiplication process, the method of forming comprising:

And removing the auxiliary lines, forming a plurality of annular sub-film layers by the plurality of annular side walls, and forming the first characteristic film layer by the annular sub-film layers.

21. The method of forming a semiconductor integrated circuit device of claim 19, wherein the stripe-shaped sub-film of the second feature film has opposite first and second film ends; and the node area of one strip-shaped sub-film layer is positioned at the end part of the first film layer, and the node area of the other strip-shaped sub-film layer is positioned at the end part of the second film layer.

22. The method for forming a semiconductor integrated circuit device according to claim 21, further comprising, after forming the second feature film layer: a node contact layer is formed on the node region.

23. The method for forming a semiconductor integrated circuit device according to any one of claims 19 to 22, wherein the semiconductor integrated circuit device is an integrated circuit memory, and the stripe-shaped sub-film layer in the second feature film layer is a bit line of the integrated circuit memory.

24. A method for forming a semiconductor integrated circuit device, characterized in that,

Forming a covering mask layer on the first characteristic film layer, wherein the covering mask layer is provided with a covering pattern area and a plurality of cutting pattern areas, the covering pattern area is provided with two opposite first boundaries and second boundaries in a second direction, and the first boundaries and the second boundaries extend along a waveform in the first direction so as to correspond to the waveform arrangement of the island-shaped sub-film layer in the first direction, and the covering pattern area of the covering mask layer is used for covering part of the island-shaped sub-film layer of the first characteristic film layer; and

25. The method of forming a semiconductor integrated circuit device according to claim 24, wherein the method of forming the first feature film layer comprises:

26. The method of forming a semiconductor integrated circuit device according to claim 24, wherein the method of forming the first feature film layer comprises:

27. The method of forming a semiconductor integrated circuit device according to claim 26, wherein among the plurality of first island-like sub-film layers, adjacent three of the first island-like sub-film layers are arranged in a triangle; among the plurality of second island-shaped sub-film layers, three adjacent second island-shaped sub-film layers are arranged in a triangle shape, wherein the second island-shaped sub-film layers are arranged in an inverted triangle shape relative to the first island-shaped sub-film layers and are mutually nested with the triangle shape of the first island-shaped sub-film layers, so that the three first island-shaped sub-film layers and the three second island-shaped sub-film layers are arranged in a hexagon shape.

28. The method of forming a semiconductor integrated circuit device according to claim 27, further comprising, after forming the second island seed film layer:

29. The method of forming a semiconductor integrated circuit device according to claim 24, further comprising, after forming the second feature film layer:

30. The method of forming a semiconductor integrated circuit device of claim 29, wherein the semiconductor integrated circuit device is an integrated circuit memory, and the array of vias in the second feature film layer is used to form an array of capacitors of the integrated circuit memory.