CN110753095A - Data processing method and device of network card and storage medium - Google Patents
Data processing method and device of network card and storage medium Download PDFInfo
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- CN110753095A CN110753095A CN201910954925.2A CN201910954925A CN110753095A CN 110753095 A CN110753095 A CN 110753095A CN 201910954925 A CN201910954925 A CN 201910954925A CN 110753095 A CN110753095 A CN 110753095A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/565—Conversion or adaptation of application format or content
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- Computer Security & Cryptography (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a data processing method of a network card, which comprises the following steps: receiving a data packet and extracting data characteristics in the data packet; comparing the data characteristics in the data packet with the data characteristics in the cache to judge the type of the effective load data in the data packet; and responding to the fact that the effective load data are to-be-stored data, extracting the effective load data in the data packet and sending the effective load data to a server. The invention also discloses a computer device and a readable storage medium. The method disclosed by the invention reduces the load of the server by improving the data processing capacity of the network card.
Description
Technical Field
The invention relates to the field of servers, in particular to a data processing method and device of a network card and a storage medium.
Background
As data is growing exponentially, data center operators require greater bandwidth for data transmission, and 40G,100G, and 400G networks are widely used. After the data bandwidth is expanded, a high-performance network card is needed to transmit the data, so that various intelligent network cards are developed to improve the transmission efficiency and reduce the network delay.
The current network card can only process to a physical layer, does not have the capability of data analysis, and cannot analyze a data packet, so that all processing tasks are given to a server to be completed, a large load is brought to the server, and the service efficiency of the server is reduced.
Therefore, a data processing method of the network card is urgently needed.
Disclosure of Invention
In view of this, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a data processing method for a network card, including:
receiving a data packet and extracting data characteristics in the data packet;
comparing the data characteristics in the data packet with the data characteristics in the cache to judge the type of the effective load data in the data packet;
and responding to the fact that the effective load data are to-be-stored data, extracting the effective load data in the data packet and sending the effective load data to a server.
In some embodiments, further comprising the step of:
responding to the fact that the effective load data are configuration data, and judging whether the effective load data need to be processed by the server or not;
and responding to the fact that the effective load data needs to be processed by a server, extracting the effective load data and sending the effective load data to the server.
In some embodiments, further comprising the step of:
in response to the payload data not requiring processing by the server, processing the payload data with a network card.
In some embodiments, extracting the payload data in the data packet and sending to a server, further comprises:
judging whether the effective load data belongs to fragment data or not;
responding to the fact that the effective load data belong to the fragment data, and continuing to receive the data packet until the obtained plurality of effective load data can form complete data;
and recombining the plurality of payload data and then sending the recombined payload data to the server.
In some embodiments, receiving the data packet comprises: receiving a data packet by using the FPGA:
determining the type of payload data in the data packet comprises: and judging the type of the effective load data in the data packet according to the data characteristics in the cache of the FPGA.
In some embodiments, in response to the payload data being configuration data, determining whether the payload data needs to be processed by the server further includes:
and responding to the fact that the effective load data are configuration data, and sending the data packet to a microprocessor through the FPGA for processing.
In some embodiments, further comprising:
and the microprocessor extracts the payload data in the data packet and judges whether the payload data needs to be processed by the server or not.
In some embodiments, further comprising:
responding to the situation that the type of the effective load data cannot be judged, and sending the data packet to a microprocessor through the FPGA;
and after the data packet is processed by the microprocessor, updating the data characteristics of the data packet and the type of the corresponding payload data into the cache of the FPGA.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to execute the steps of the data processing method of any of the network cards described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, and the computer program, when executed by a processor, executes the steps of the data processing method of any one of the network cards described above.
The invention has the following beneficial technical effects: the method disclosed by the invention reduces the load of the server by improving the data processing capacity of the network card.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a data processing method of a network card according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides a data processing method for a network card, as shown in fig. 1, which may include the steps of: s1, receiving a data packet and extracting data characteristics in the data packet; s2, comparing the data characteristics in the data packet with the data characteristics in the cache to judge the type of the payload data in the data packet; s3, responding to the data to be stored of the effective load data, extracting the effective load data in the data packet and sending the effective load data to a server.
The method disclosed by the invention reduces the load of the server by improving the data processing capacity of the network card.
In some embodiments, receiving the data packet and extracting the data feature in the data packet comprises: and receiving the data packet transmitted from the network through the FPGA of the network card, and extracting the data characteristics in the data packet through the FPGA.
And then, comparing the data characteristics in the data packet with the data characteristics in the cache to judge the type of the payload data in the data packet. Determining the type of payload data in the data packet includes: and judging the type of the effective load data in the data packet according to the data characteristics in the cache of the FPGA.
In some embodiments, the data characteristic may be MAC + IP + TCP/UDP + PORT in the data packet, so that the type of PAYLOAD (PAYLOAD data) carried by the data packet may be determined through MAC + IP + TCP/UDP + PORT.
Specifically, the data characteristics and the corresponding data types may be written in the cache of the FPGA in advance, and then after the data packet is received, the payload data in the data packet may be determined according to the data characteristics in the data packet.
In some embodiments, in response to the payload data being data to be stored, the payload data in the data packet is extracted and sent to a server.
Specifically, if the FPGA determines that the type of the PAYLOAD data is the data to be stored, the FPGA directly copies the PAYLOAD of the data packet to the memory of the server through DMA after deleting the data header protocol portion of the data packet.
In some embodiments, extracting the payload data in the data packet and sending the extracted payload data to a server further includes: judging whether the effective load data belongs to fragment data or not; responding to the fact that the effective load data belong to the fragment data, and continuing to receive the data packet until the obtained plurality of effective load data can form complete data; and recombining the plurality of payload data and then sending the recombined payload data to the server.
Specifically, when the initial original data packet is larger than the maximum transmission unit of the link, the initial original data packet needs to be decomposed into a plurality of small segments for transmission, so that only after a plurality of payload data obtained by the FPGA can form complete data, the recombined data is sent to the server through the DMA instead of sending only one piece of fragmented data to the server, and the load of the server is further reduced.
It should be noted that the FPGA has the advantages of concurrent multithreading and low network delay. The data to be stored has the characteristics of simple transmission protocol, high transmission efficiency, relative simplicity and no need of a feedback mechanism. Therefore, the data to be stored can be directly sent to the memory of the server through the FPGA, and the process that the server processes the data packet again is avoided.
In some embodiments, in response to the payload data being configuration data, the FPGA sends the data packet to a microprocessor, with which the data packet is processed.
In some embodiments, the specific processing may include determining whether the payload data requires processing by the server; responding to the fact that the effective load data need to be processed by a server, extracting the effective load data and sending the effective load data to the server; in response to the payload data not requiring processing by the server, processing the payload data with a network card.
Specifically, when the FPGA determines that the payload data is the configuration data according to the data characteristics, the FPGA sends the data packet to a microprocessor (ARM), and the microprocessor extracts the payload data in the data packet and then determines whether the payload data needs to be processed by the server.
After extracting the payload data in the data packet, the microprocessor needs to analyze and analyze the protocol, if the payload data is data for maintaining and judging the state, such as a timeout state, a packet loss state, and whether to wait for the state, the microprocessor can process the data without sending the data to the server, and if the data is not the above data but higher-level data, the data needs to be sent to the server for processing.
The ARM can process the data packet through a linux network protocol stack running on the ARM, wherein the linux network protocol stack can process and analyze a complex protocol.
In some embodiments, in response to failing to determine the type of the payload data, the FPGA sends the data packet to a microprocessor; and after the data packet is processed by the microprocessor, updating the data characteristics of the data packet and the type of the corresponding payload data into the cache of the FPGA.
Specifically, if the type of the payload data in the received data packet cannot be judged according to the data characteristics in the FPGA cache, the data packet is directly sent to the ARM, the ARM judges that the data packet belongs to the data to be stored through the network protocol stack, the payload data is extracted and sent to the memory of the server, and if the data packet belongs to the configuration data, the data packet is processed according to the method for processing the data packet by the ARM in the embodiment of the present invention. And simultaneously, the data characteristics and the corresponding data types are sent to a cache of the FPGA, so that the FPGA can identify the data characteristics.
According to the method provided by the invention, the FPGA carries out network data shunting according to the network data feature table, data (to-be-stored data) of the data plane is processed by the FPGA, and data (configuration data) of the control plane is transmitted to a protocol stack of the ARM for processing. If the data type can not be judged, learning of data characteristics is carried out through a protocol data stream through a program on the ARM, and new data characteristics are written into a data characteristic table of the FPGA so as to be convenient for subsequent FPGA processing. Therefore, the capacity of the network card for processing data is increased, and the burden of the server is reduced.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 2, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
the memory 510 and the memory 510 store a computer program 511 that can be run on the processor, and the processor 520 executes the program to execute the steps of the data processing method of any of the above network cards.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of the data processing method of any network card as above.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program to instruct related hardware to implement the methods. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
In addition, the apparatuses, devices, and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television, and the like, or may be a large terminal device, such as a server, and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed by the embodiment of the invention can be applied to any one of the electronic terminal devices in the form of electronic hardware, computer software or a combination of the electronic hardware and the computer software.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A data processing method of a network card comprises the following steps:
receiving a data packet and extracting data characteristics in the data packet;
comparing the data characteristics in the data packet with the data characteristics in the cache to judge the type of the effective load data in the data packet;
and responding to the fact that the effective load data are to-be-stored data, extracting the effective load data in the data packet and sending the effective load data to a server.
2. The method of claim 1, further comprising the step of:
responding to the fact that the effective load data are configuration data, and judging whether the effective load data need to be processed by the server or not;
and responding to the fact that the effective load data needs to be processed by a server, extracting the effective load data and sending the effective load data to the server.
3. The method of claim 2, further comprising the step of:
in response to the payload data not requiring processing by the server, processing the payload data with a network card.
4. The method of claim 1, wherein the payload data in the data packet is extracted and sent to a server, further comprising:
judging whether the effective load data belongs to fragment data or not;
responding to the fact that the effective load data belong to the fragment data, and continuing to receive the data packet until the obtained plurality of effective load data can form complete data;
and recombining the plurality of payload data and then sending the recombined payload data to the server.
5. The method of claim 1, wherein the receiving the data packet comprises: receiving a data packet by using the FPGA;
the determining the type of the payload data in the data packet includes: and judging the type of the effective load data in the data packet according to the data characteristics in the cache of the FPGA.
6. The method of claim 5, wherein in response to the payload data being configuration data, determining whether the payload data requires processing by the server, further comprising:
and responding to the fact that the effective load data are configuration data, and sending the data packet to a microprocessor through the FPGA for processing.
7. The method of claim 6, further comprising:
and the microprocessor extracts the payload data in the data packet and judges whether the payload data needs to be processed by the server or not.
8. The method of claim 6, further comprising:
responding to the situation that the type of the effective load data cannot be judged, and sending the data packet to a microprocessor through the FPGA;
and after the data packet is processed by the microprocessor, updating the data characteristics of the data packet and the type of the corresponding payload data into the cache of the FPGA.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of the method according to any of claims 1-8.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method of any one of claims 1 to 8.
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| CN114005429A (en) * | 2021-10-14 | 2022-02-01 | 苏州浪潮智能科技有限公司 | Signal synthesis method, signal synthesis device, computer equipment and storage medium |
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| CN116827411A (en) * | 2023-06-27 | 2023-09-29 | 北京和德宇航技术有限公司 | Load data analysis method and device, electronic equipment and storage medium |
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