CN110752850A

CN110752850A - Method for quickly iterating LDPC code of MLC flash memory chip

Info

Publication number: CN110752850A
Application number: CN201910798178.8A
Authority: CN
Inventors: 韩国军; 郑敏华; 何瑞泉; 蔡国发; 方毅
Original assignee: Guangdong University of Technology
Current assignee: Zhejiang Changchun Technology Co ltd
Priority date: 2019-08-27
Filing date: 2019-08-27
Publication date: 2020-02-04
Anticipated expiration: 2039-08-27
Also published as: CN110752850B

Abstract

In order to solve the problem that an ECC scheme in the prior art is not enough to ensure the reliability of data on a chip, the invention provides a method for quickly iterating an LDPC code of an MLC flash memory chip, which comprises the following steps: obtaining LLR error probability: obtaining an iteration factor according to the LLR error probability: and obtaining an iteration number substituting algorithm. Except for the aliasing areas E2 of the high page, the aliasing areas E1 and E3 of the low page, the iteration times of other parts of the invention are reduced, and the adjustment is carried out along with the change of the channel, the error probabilities corresponding to the zone bits are different and can change along with the change of the channel, the adjustment of the iteration times is carried out on variable nodes with different error probabilities and different channel noises by utilizing the error probabilities, and the required iteration times are obtained by adding an exponential function. The invention can effectively and greatly reduce the complexity in decoding, has only a small amount of calculation complexity and no other real value comparison complexity, and simultaneously does not influence the decoding performance.

Description

Method for quickly iterating LDPC code of MLC flash memory chip

Technical Field

The invention relates to the field of MLC flash memory chip error correction, in particular to a method for quickly iterating LDPC codes of an MLC flash memory chip.

Background

Most advanced NAND flash memory chips suffer from significant channel noise damage, thus raising some data reliability problems that Low Density Parity Check (LDPC) codes are becoming the dominant error correction code in flash memory controllers in order to overcome. Thus, long Belief Propagation (BP) decoding delays begin to degrade system performance. Aslam proposes a low-complexity quantization perception belief propagation (QA-BP) decoding scheme, and only unreliable variable nodes corresponding to high error probability LLR values are updated in a non-uniform quantization channel through different error rates of log-likelihood ratios. On the basis, the invention calculates the corresponding iteration times according to different error probabilities of the log-likelihood ratio. Neither additional run operations nor real value comparisons are required. The decoding complexity can be greatly reduced, and the performance is not reduced.

With the increasing use of NAND flash in digital electronic products and high-performance enterprise data applications, it has become the most important data storage medium because it has the outstanding features of low cost, large storage capacity, low power consumption, high speed, etc. Read response time. However, due to continuous node scaling and multi-level cell (MLC) technology for meeting the ever-increasing memory size demands, several channel noise and interference effects have emerged over the past few years thereby reducing the reliability of flash data. As a direct consequence, the lifetime of modern flash memory chips is severely limited in terms of wear-out (number of Program and Erase (PE) operations) and retention time (duration of data storage). The limited number of PE cycles that a flash memory can handle is also referred to as memory endurance. These reliability problems pose a significant barrier to the further spread of flash memory usage in practical applications. Modern flash memory controllers widely employ Error Correction Codes (ECC) to improve data reliability. However, as storage capacity requirements tend to increase, conventional ECC schemes (e.g., Bose-Chaudhuri Hocquenghem (BCH) codes with hard-decision decoding) prove to be insufficient to ensure on-chip data reliability. In particular, Low Density Parity Check (LDPC) codes are attracting attention because of their excellent error correction capabilities over time.

Message passing may also perform parallel updates of all variable/check nodes simultaneously using the flooding plan, or sequential (serial) through one update node. However, serial BP scheduling has shown to converge (produce decoded results) faster than parallel scheduling. For SBP codes, it is described that the required number of message transmissions in forced-convergence (forced-convergence) can reduce convergence by selectively updating partial sets. At FC decoding, at each iteration, each is reliable comparing variable nodes to a predetermined threshold and selecting only less reliable variable nodes for further updating. Alternatively, an algorithm based on (lazy-schedule) forced decoding is also considered, but LS decoding requires an additional operation of calculating the convergence probability at runtime. Furthermore, FC and LS schemes followed by real-valued comparisons inherently add more complex computational load to each decoding iteration.

Disclosure of Invention

In order to solve the problem that an ECC scheme in the prior art is not enough to ensure the reliability of data on a chip, the invention provides a method for quickly iterating an LDPC code of an MLC flash memory chip.

The technical scheme adopted by the invention to solve the technical problems is as follows: a method for quickly iterating LDPC codes of an MLC flash memory chip is characterized by comprising the following steps:

s1, obtaining LLR error probability: setting a total of N flash memory cells in a page of the flash memory for four states, passing 6 quantization voltages { R }₁,R₂,R₃,R₄,R₅,R₆Divide the threshold voltage distribution of the four states into seven voltage intervals, excluding the epsilon of the upper page₂And epsilon of lower page₁，ε₃And the three bit aliasing areas calculate the voltage distribution error probability of other voltage intervals. (the following should be the probability of voltage distribution error for the upper and lower pages of the unaliased region, the aliased region does not perform the calculation):

P_e(L_msb∈D₁)＝(N₀₀(D₁)+N₀₁(D₁))/N(D₁) P_e(L_Lsb∈ D₁)＝(N₀₀(D₁)+N₁₀(D₁))/N(D₁)

P_e(L_msb∈E₁)＝(N₀₀(E₁)+N₀₁(E₁))/N(E₁) P_e(L_Lsb∈ D₂)＝(N₁₁(D₂)+N₀₁(D₂))/N(D₂)

P_e(L_msb∈D₂)＝(N₀₀(D₂)+N₀₁(D₂))/N(D₂) P_e(L_Lsb∈E₂)＝(N₁₁(E₂)+N₀₁(E₂))/N(E₂)

P_e(L_msb∈D₃)＝(N₁₁(D₃)+N₁₀(D₃))/N(D₃) P_e(L_Lsb∈ D₃)＝(N₁₁(D₃)+N₀₁(D₃))/N(D₃)

P_e(L_msb∈E₃)＝(N₁₁(E₃)+N₁₀(E₃))/(N(E₃) P_e(L_Lsb∈ D₄)＝(N₀₀(D₄)+N₁₀(D₄))/N(D₄)

P_e(L_msb∈D₄)＝(N₁₁(D₄)+N₁₀(D₄))/N(D₄)；

wherein, the bits of the upper page are 1, 1, 0, 0 in sequence, and the bits of the lower page are 1, 0, 0, 1 in sequence;

is a function of the voltage distribution of four combined states, R_n-1≤v≤R_nfor n＝1，2，3，4，5，6，7，R₀＝-∞，R₇＝+∞，

dv is the variable of the integral, { expression integrated };N₀₀representing the total number of errors under 00 combinations, and so on;

d1 is the interval corresponding to the state 11, and so on; e1 represents the interval of the first aliasing zone;

s2, obtaining an iteration number factor according to the LLR error probability: under the influence of the interference factor T, the error probability Pe takes its absolute value again through a logarithmic function, which is specifically as follows: | log10 (P)_e) The maximum iteration number I is set as the iteration number factor β_MAXSuch that the number of decoding iterations I required for a variable node in a certain non-aliasing interval (aliasing threshold voltage interval)_XComprises the following steps: i is_X＝I_MAXβ, wherein 0 ≦ β ≦ 1, and should have a positive correlation with Pe, β ═ f (| log10 (P)_e) | log10 (P)_e) I is a decreasing function, so f (log10 (P)_e) The above is satisfied when the base of the logarithmic function is greater than 0 and less than 1, and the decreasing trend is relatively flat, so that β will not be too far apart to affect the decoding performance.

I_X＝I_MAX*β.

S3, obtaining an iteration number substituting algorithm;

setting a vector U ═ U_i＝0|i＝1，...N}，u_iA flag bit of a certain variable node; according to the formula

Obtaining the number of iterations, wherein_XFor the number of iterations, I_maxTo set the maximum number of iterations.

In step S1, the MLC flash memory has 4 combinations: 11, 10, 00, 01; 8 threshold voltages R0, R1, R2, R3, R4, R5, R6 and R7 are set, and 7 voltage intervals C1, C2, C3, C4, C5, C6 and C7 are divided; the first bit of all the cells of the MLC flash memory is extracted and called the upper page, the second bit is the lower page, and the upper page and the lower page have N bits respectively.

Wherein the step S3 is executed by: setting the maximum number of iterations I_MAXK is the number of rounds of the current decoding iteration, 50. Each round finds u_iDecoding the variable node of 0, if the variable node meets the stop criterion, quitting decoding, otherwise, judging whether K is more than u_iVariable node iteration-free value I not equal to 0_MAX-I_xIf yes, the corresponding variable node u_iAfter 0, it participates in decoding until the stop criterion is met or k exceeds 50 times.

The invention has the beneficial effects that: except for the aliasing areas E2 of the high page, the aliasing areas E1 and E3 of the low page, the iteration times of other parts of the invention are reduced, and the adjustment is carried out along with the change of the channel, the error probabilities corresponding to the zone bits are different and can change along with the change of the channel, the adjustment of the iteration times is carried out on variable nodes with different error probabilities and different channel noises by utilizing the error probabilities, and the required iteration times are obtained by adding an exponential function. The invention can effectively and greatly reduce the complexity in decoding, has only a small amount of calculation complexity and no other real value comparison complexity, and simultaneously does not influence the decoding performance.

Drawings

Fig. 1 is a flash memory channel model.

FIG. 2 is a graph of threshold voltage distribution under the channel endurance noise of MLC-type flash memory.

Fig. 3 is a visual diagram of 4 voltage distribution functions of the MLC flash memory after 6 quantization.

FIG. 4 is an error rate for different regions over persistence time.

FIG. 5 is a comparison of the number of iterations of the QABP and QABP _ HL algorithms versus the BP algorithm with changes in PE.

FIG. 6 shows the QABP algorithm setting flag bits for variable nodes.

FIG. 7a is the flag bits for the high page variable node of the present invention.

FIG. 7b shows the flag bits for the low page variable node according to the present invention.

Fig. 8 is a graph of the magnitude change of the number of iterations with the probability of error.

Detailed Description

The present application is further described below with reference to the accompanying drawings.

As can be seen in FIG. 1, the channel has programming noise, random telegraph noise RTN and interference of persistent noise, the interference of programming noise being denoted as n_sInterference of random telegraph noise is denoted n_wThe interference of persistent noise is denoted as n_rInitial voltage of flash memory cell is marked as x_sThe read voltage is denoted as v, and the expression is as follows:

v＝x_s+n_s+n_w+n_r(1)

programming noise:

RTN noise:

setting sigma_w＝0.00025(PE)^0.62；

Retention (persistence) noise:

persistent noise is caused by electron leakage after cell programming, which is caused by electron trapping and is the main disturbance of flash memory. As the program/erase operation is repeated, the amount of trapped electrons increases with electrical stress, and the insulating properties of the oxide layer decrease. In addition, Trap Assist (TAT) tunneling is caused by trapped electrons forming an electron tunnel, and the TAT effect causes stored electrons in the floating gate to leak out faster. Thus, the threshold voltage of the memory cell shifts to a lower state over time. Persistent noise induced threshold voltage shift approximately follows a Gaussian distribution

Both random telegraph noise and persistent noise are affected by the number of program/erase cycles, a large number of P/E operations cause increased cell wear, and the constant loss of electrons for program and erase operations cause a reduction in the threshold voltage peak, i.e., data cannot be programmed to the highest state. Chip technologyThe size is reduced and the capacitance and the number of electrons of the flash memory cell are reduced. The most advanced MLC type flash memory cells store only about 100 electrons, so increasing or losing several electrons can significantly weaken the threshold voltage of the cell, affecting the memory state, resulting in limited data retention endurance.

Wherein

σ_r＝0.3|μ_r| (6)

The three noise disturbances experienced by the read voltage can be expressed as:

as shown in fig. 2, since the output voltages are all subjected to gaussian distribution, the output voltages are also gaussian models, as follows:

wherein

x_s11＝1.4,x_s10＝2.6,x_s00＝3.23,x_s01＝4.1,

σ_e＝0.35,σ_p＝0.1,α_i＝0.62,α₀＝0.30,

A_t＝0.000035,B_t＝0.000235,

The method for quickly iterating the LDPC code of the MLC flash memory chip is characterized by comprising the following steps of:

the first step is as follows: calculating LLR error probability:

as shown in fig. 3, setting the code length to N, which is also the number of memory cells of the flash memory, the flash memory of MLC can store two bits per cell, so there are 4 combinations (states) in total: 11, 10, 00, 01. (11 is an erasing state, the rest are programming states, and the voltages thereof are sorted from small to large) each memory cell has a corresponding voltage, 8 threshold voltages (R0, R1, R2, R3, R4, R5, R6 and R7) are arranged, 7 voltage intervals (C1, C2, C3, C4, C5, C6 and C7) are divided, and according to the voltage, the number of the memory cells corresponding to the voltage is taken as a variable, and a voltage threshold distribution graph is obtained. The voltage distribution of 4

states

11, 10, 00, 01 of the flash memory is divided into 7 intervals, and after channel interference, other states appear in the voltage intervals which do not belong to the state. The flash memory cell can store 2 bits, so the first bit of all the cells of the MLC flash memory is extracted and called as the upper page (msb), the second bit is the lower page (lsb), and the upper page and the lower page have N bits respectively. As shown in FIG. 1,. epsilon.1,. epsilon.2,. epsilon.3, are the aliasing regions (decision-prone intervals) for these 4 states. Wherein, the order of the high page bit is 1100, and the interval of aliasing between 1 and 0 is epsilon 2; the order of the lower page bits is 1001, and its aliasing regions are ε 1, ε 3.

The MLC flash channel is divided into 7 sections by using the mutual information to obtain six quantized voltages, and as shown in fig. 3, the bits of the upper page (MSB) are 1100 in order and the bits of the lower page (LSB) are 1001 in order.Is a function of the voltage distribution of the four states，R_n-1≤v≤R_nfor n＝1,2,3,4,5,6,7R₀＝-∞，R₇The LLR is calculated as + ∞:

as shown in fig. 4, the quantization voltage of the present invention varies with the channel variation, and as long as the channel parameter varies, the varied quantization voltage is found by mutual information, and the LLR (confidence) also varies with the channel variation. And calculating the error rate of each area of the high and low pages, wherein the error probability formula of the high and low pages is as follows:

Pe(Lmsb∈D1)＝(N00(D1)+N01(D1))/N(D1) Pe(LLsb∈1)＝(N00(D1)+N10(D1))/N(D1)

Pe(Lmsb∈E1)＝(N00(E1)+N01(E1))/N(E1) Pe(LLsb∈2)＝(N11(D2)+N01(D2))/N(D2)

Pe(Lmsb∈D2)＝(N00(D2)+N01(D2))/N(D2) Pe(LLsb∈2)＝(N11(E2)+N01(E2))/N(E2)

Pe(Lmsb∈D3)＝(N11(D3)+N10(D3))/N(D3) Pe(LLsb∈3)＝(N11(D3)+N01(D3))/N(D3)

Pe(Lmsb∈E3)＝(N11(E3)+N10(E3))/(N(E3) Pe(LLsb∈4)＝(N00(D4)+N10(D4))/N(D4)

Pe(Lmsb∈D4)＝(N11(D4)+N10(D4))/N(D4) (10)

examples are: error probability calculation for high Page C1:

the number N of flash memory cells in the C1 interval (C1) is calculated, and the state of the upper page in the C1 interval is 11, and the bit correspondence is 1, so that no error occurs in the C1 interval in the 10 state. The

state

00, 01 corresponding to the 0 bit is considered as an error when it occurs in the C1 interval. Thus, the sum of the numbers of 00, 01 states in the interval C1 is calculated: n00(C1) + N01 (C1).

The LLR error probability of the variable node of the upper page of this C1 region should be:

(N00(C1) + N01(C1))/N (C1). Wherein (C1) + N (C2) + N (C3) + N (C4) + N (C5) + N (C6) + N (C7) ═ N.

QABP: from fig. 4, it is shown that the error probability of the variable nodes in the D4 region is much lower than that of the variable nodes in the D1 of the upper page, including D2 and D3 of the upper page, D1, D2, D3 and D4 of the lower page. Therefore, the iteration times of variable nodes in the D1 and D4 regions of the high page are only reduced, and the other nodes are not processed, as shown in FIG. 6, the QABP algorithm marks the nodes. And the number of iterations of this reduction is set to 5 and does not vary with the channel variations. As can be seen from fig. 5, the complexity of the QA-BP algorithm is closer to that of the BP algorithm as the channel noise is larger.

The second step is that: calculating an iteration number factor (convergence factor) according to the LLR error probability:

except for the aliasing zone E2 of the upper page, the aliasing zone E1 of the lower page and E3 of the lower page, the number of iterations is reduced and is adjusted along with the change of the channel, as shown in FIG. 7a and FIG. 7b, the left side is the flag bit set by the algorithm for the variable node of the upper page, and the right side is the flag bit set by the algorithm for the variable node of the lower page. The log-likelihood ratio LLR is an initial value when the variable node V is decoded (the numbers of LLRs and V are both N), and plays a key role in decoding performance. The log-likelihood ratio is calculated from the voltage distributions of the above four states, and is also divided into upper and lower pages. The higher the error probability, the higher the probability that the LLR corresponding to the section having the higher error probability will be erroneous. The variable nodes with higher error probabilities need more iterations to converge, and the variable nodes with lower error probabilities converge faster and therefore do not need as many iterations as other variable nodes with higher error probabilities. The method is provided for calculating the number of iterations required by the variable node by using the error probability of the LLR of the variable node.

As shown in Table I, the error probability of the high page and the low page in some threshold voltage interval is very different in the same disturbance factor, but the iteration number is not different by several orders of magnitude, so some calculation operation is needed to make f (Pe) in one order of magnitude, and the absolute value of the logarithm function can be in another order of magnitude, but the iteration number factor β (0 ≦ β ≦ 1) so that an exponential function is needed to be decreased to ensure that 0 ≦ β ≦ 1.

Table one step of processing the LLR error probability of the low page variable node when T ═ 1 × 10^ 6:

table two lists the error probability of different flag bits for a higher page when T1 x 10 x 6, and the calculated value by base 10 logarithm. Table 2 lists the error probability of the high page D3 region under different channel noise and its iteration factor.

TABLE II, T1 x 10^6, error probability of different flag bits of high page and quantization value thereof

Error probability and quantized value of table three high page D3 area under different channel noises

The third step: obtaining an iteration number substituting algorithm:

when the error probability is calculated by the logarithm with the base number of 10, the error probability of each flag bit is not different so much, and is different by a few digits, which is equivalent to a quantization level. The error probability is calculated as a quantization level of the error probability by the base 10 logarithm. However, the difference between the quantization levels is still somewhat large, and in order to reduce the difference and make the error probability more sensitive, an exponential function is added. Setting a vector U ═ U_i＝0|i＝1，...N}，u_iIs a flag bit of a certain variable node. The variable nodes do not do any treatment on the flag bits of epsilon 1 of the upper page and epsilon 2 and epsilon 3 of the lower page. And marking the flag bits of the variable nodes of the upper page as {1, 2, 3, 5, 6, 7} to obtain {1, 2, 3, 0, 5, 6, 7} and marking the flag bits of the variable nodes of the lower page as {1, 0, 3, 4, 5, 0, 7 }. And (3) assigning the iteration times of the zone bits of which the upper page and the lower page are not 0:

high page { I_{msb_1}，I_{msb_2}，I_{msb_3}，I_{msb_5}，I_{msb_6}，I_{msb_7}}，

Low page { I_{low_1}，I_{low_3}，I_{low_4}，I_{low_5}，I_{low_7}}。

The algorithm process is as follows: setting the maximum number of iterations I_MAXK is the number of rounds of the current decoding iteration, 50. Each round finds u_iDecoding the variable node of 0, if the variable node meets the stop criterion, quitting decoding, otherwise, judging whether K is more than u_iVariable node iteration-free value I not equal to 0_MAX-I_xIf yes, the corresponding variable node u_iAfter 0, it participates in decoding until the stop criterion is met or k exceeds 50 times.

Examples are: as shown in FIG. 8, I_{msb_3}That corresponds to the variable node 10 times before (I)_MAX-40) has not been decoded, u _i3. When K phi 10, u _i3 to u _i0 and the corresponding variable node participates in the decoding.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A method for quickly iterating LDPC codes of an MLC flash memory chip is characterized by comprising the following steps:

s1, obtaining LLR error probability: setting a total of N flash memory cells in a page of the flash memory for four states, passing 6 quantization voltages { R }₁,R₂,R₃,R₄,R₅,R₆Divide the threshold voltage distribution of the four states into seven voltage intervals, excluding the epsilon of the upper page₂And epsilon of lower page₁，ε₃The three bit aliasing regions calculate the voltage distribution error probability of other voltage intervals:

P_e(L_msb∈D₁)＝(N₀₀(D₁)+N₀₁(D₁))/N(D₁) P_e(L_Lsb∈D₁)＝(N₀₀(D₁)+N₁₀(D₁))/N(D₁)

P_e(L_msb∈E₁)＝(N₀₀(E₁)+N₀₁(E₁))/N(E₁) P_e(L_Lsb∈D₂)＝(N₁₁(D₂)+N₀₁(D₂))/N(D₂)

P_e(L_msb∈D₃)＝(N₁₁(D₃)+N₁₀(D₃))/N(D₃) P_e(L_Lsb∈D₃)＝(N₁₁(D₃)+N₀₁(D₃))/N(D₃)

P_e(L_msb∈E₃)＝(N₁₁(E₃)+N₁₀(E₃))/(N(E₃) P_e(L_Lsb∈D₄)＝(N₀₀(D₄)+N₁₀(D₄))/N(D₄)

P_e(L_msb∈D₄)＝(N₁₁(D₄)+N₁₀(D₄))/N(D₄)；

is a function of the voltage distribution of four combined states, R_n-1≤v≤R_nfor n＝1,2,3,4,5,6,7，R₀＝-∞，R₇＝+∞，

dv is the integrated variable; n is a radical of₀₀Representing the total number of errors in the 00 state, and so on; d1 is the interval corresponding to the state 11, and so on; e1 represents the interval of the first aliasing zone;

s2, obtaining an iteration number factor according to the LLR error probability: under the influence of the interference factor T, the error probability Pe takes its absolute value (decreasing function) again through a logarithmic function, specifically as follows: | log10 (P)_e) The maximum iteration number I is set as the iteration number factor β_MAXThe scaling factor of (2) is such that the number of decoding iterations Ix required for a variable node in a certain non-aliasing interval is: i is_X＝I_MAXβ, wherein 0 ≦ β ≦ 1, and should have a positive correlation with Pe, β ═ f (| log10 (P)_e) | log10 (P)_e) I is a decreasing function, so f (log10 (P)_e) The above is satisfied when the base of the logarithmic function is greater than 0 and less than 1, and the decreasing trend is relatively gentle, so that β is not too different to affect the decoding performance:

0＜α＜1，I_X＝I_MAX*β.

s3, obtaining an iteration number substituting algorithm;

2. The method of claim 1, wherein in step S1, the MLC flash memory has 4 states in total: 11, 10, 00, 01; 8 threshold voltages R0, R1, R2, R3, R4, R5, R6 and R7 are set, and 7 voltage intervals C1, C2, C3, C4, C5, C6 and C7 are divided; the first bit of all the cells of the MLC flash memory is extracted and called the upper page, the second bit is the lower page, and the upper page and the lower page have N bits respectively.

3. The method of claim 1, wherein the step S3 is performed by: setting the maximum number of iterations I_MAXK is the number of rounds of the current decoding iteration, 50. Each round finds u_iDecoding the variable node of 0, if the variable node meets the stop criterion, quitting decoding, otherwise, judging whether K is more than u_iVariable node iteration-free value I not equal to 0_MAX-I_xIf yes, the corresponding variable node u_iAfter 0, it participates in decoding until the stop criterion is met or k exceeds 50 times.