CN110752278A - Light emitting diode and manufacturing method thereof - Google Patents
Light emitting diode and manufacturing method thereof Download PDFInfo
- Publication number
- CN110752278A CN110752278A CN201911078014.4A CN201911078014A CN110752278A CN 110752278 A CN110752278 A CN 110752278A CN 201911078014 A CN201911078014 A CN 201911078014A CN 110752278 A CN110752278 A CN 110752278A
- Authority
- CN
- China
- Prior art keywords
- layer
- type
- type electrode
- electrode
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/387—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
Abstract
The invention provides a light emitting diode and a manufacturing method thereof, wherein an epitaxial layer structure of the light emitting diode comprises: the N-type semiconductor layer, the active region and the P-type semiconductor layer are sequentially overlapped on the substrate from bottom to top; firstly, overlapping positions of an N-type electrode expansion strip and a P-type electrode expansion strip in the horizontal direction is arranged, so that the light blocking area of the electrodes is reduced; secondly, a plurality of conductive through holes penetrating through the isolation layers are formed in specific positions of the second isolation layer and the third isolation layer, so that the current expansion effect is improved, and the luminous efficiency is improved; the N-type electrode is insulated from the first transparent conducting layer and the second transparent conducting layer through the first isolating layer and the third isolating layer, and electric leakage of the light-emitting diode is effectively avoided.
Description
Technical Field
The invention belongs to the field of light emitting diodes, and particularly relates to a light emitting diode and a manufacturing method thereof.
Background
Since Light Emitting Diodes (LEDs) have advantages of high brightness, small size, and low power consumption, they are regarded as a new generation of lighting tools, and in recent years, they have been rapidly applied and popularized in more fields. However, since the conventional semiconductor chip of the light emitting diode still has a problem of low light emitting efficiency, how to improve the light emitting efficiency of the semiconductor chip of the light emitting diode has become one of the most important issues in the present scientific research field.
The existing chip structure still has some problems: as a traditional front-mounted LED chip, P, N welding table electrodes and P, N cross-opposite extension electrodes are adopted for current transmission, and a large light blocking area exists. The most common method in the prior art is to arrange a current blocking area (dielectric layer) in the area under the electrode to block the transmission capability of the current under the welding table electrode, thereby improving the current density of the non-welding table electrode area, increasing the luminous capability of the active layer and reducing the problem of light blocking of the welding table electrode. However, due to the dielectric layer insulation, the dielectric layer is an oxide, and the existence of the oxide layers prevents the uniform interaction between the semiconductor and the metal layer.
Disclosure of Invention
In view of this, the present invention provides a light emitting diode and a method for manufacturing the same, which can reduce light blocking of an electrode and increase light emitting area of the light emitting diode.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a light emitting diode comprising:
a substrate;
the epitaxial layer structure is arranged on the surface of the substrate; the epitaxial layer structure includes: the N-type semiconductor layer, the active region and the P-type semiconductor layer are sequentially overlapped on the substrate from bottom to top;
the upper surface of the P-type semiconductor layer is provided with a groove extending towards the N-type semiconductor layer and exposing the N-type semiconductor layer; an N-type pad electrode and an N-type electrode expansion strip are arranged on the surface of the N-type semiconductor layer in the groove; the N-type pad electrode and the N-type electrode extension strip are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove;
a first isolating layer is arranged between the side wall of the groove and the N-type electrode and on the upper surface of the N-type electrode extension strip; a first transparent conducting layer is arranged on one side of the first isolating layer, which is far away from the upper surface of the N-type electrode extension strip, and the P-type semiconductor layer, and the first transparent conducting layer is electrically connected with the P-type semiconductor layer; the first transparent conducting layer is provided with a P-type electrode extension strip and a P-type pad electrode, and the P-type pad electrode and the P-type electrode extension strip are electrically connected to form a P-type electrode;
the N-type electrode expansion strip and the P-type electrode expansion strip are overlapped in the horizontal direction;
and the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer are set.
Preferably, a second isolation layer is arranged on the upper surface of the P-type semiconductor layer; the second isolation layer is provided with a plurality of first conductive through holes penetrating through the second isolation layer; the first transparent conducting layer is arranged on the P-type semiconductor layer through the first conducting through hole and is electrically connected with the P-type semiconductor layer; the first isolation layer is arranged between the first transparent conducting layer and the N-type pad electrode.
Preferably, the upper surface of the N-type electrode extension bar is flush with the upper surface of the P-type semiconductor layer, and the second isolation layer is integrally disposed with the first isolation layer.
Preferably, the solar cell further comprises a third isolating layer and a second transparent conducting layer; the third isolating layer is arranged on the upper surface of the first transparent conducting layer; a plurality of second conductive through holes penetrating through the third isolation layer are formed in the third isolation layer corresponding to the positions where the N-type electrode extension strips are not arranged; the second transparent conducting layer is arranged on the upper surface of the third isolating layer; the P-type electrode extension bar and the P-type pad electrode are arranged on the second transparent conducting layer; the second transparent conducting layer is arranged on the first transparent conducting layer through the second conducting through hole and is electrically connected with the first transparent conducting layer; and the third isolating layer is arranged between the N-type pad electrode and the first transparent conducting layer and between the N-type pad electrode and the second transparent conducting layer.
Preferably, an upper surface of the first isolation layer is flush with an upper surface of the P-type semiconductor layer.
Preferably, the first conductive via has at least two different via sizes, the via size far away from the N-type electrode spreading strip is larger than the via size near the N-type electrode spreading strip; the second conductive through hole has at least two different through hole sizes, and the through hole size far away from the N-type electrode extension strip is larger than the through hole size close to the N-type electrode extension strip.
The invention also provides a manufacturing method of the light emitting diode, which comprises the following steps:
step S1, providing a substrate, and forming an epitaxial layer structure on the substrate, wherein the epitaxial layer structure comprises an N-type semiconductor layer, an active region and a P-type semiconductor layer which are sequentially formed on the substrate from bottom to top;
step S2, forming a groove extending toward the N-type semiconductor layer on the upper surface of the P-type semiconductor layer, and exposing the N-type semiconductor layer;
step S3, forming an N-type pad electrode and an N-type electrode expansion strip on the surface of the N-type semiconductor layer in the groove; the N-type pad electrode and the N-type electrode extension strip are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove;
step S4, arranging a first isolating layer between the side wall of the groove and the N-type electrode and on the upper surface of the N-type electrode expansion strip;
step S5, arranging a first transparent conducting layer on one side of the first isolating layer, which is far away from the upper surface of the N-type electrode extension strip, and the P-type semiconductor layer, wherein the first transparent conducting layer is electrically connected with the P-type semiconductor layer;
step S6, arranging a P-type electrode expansion strip and a P-type pad electrode on the first transparent conductive layer, wherein the P-type pad electrode and the P-type electrode expansion strip are electrically connected to form a P-type electrode; the N-type electrode expansion strip and the P-type electrode expansion strip are overlapped in the horizontal direction; and the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer are set.
Preferably, the upper surface of the N-type electrode extension strip is flush with the upper surface of the P-type semiconductor layer;
the step S4, while providing the first isolation layer, further includes a step S11 of forming a second isolation layer integrally formed with the first isolation layer on the upper surface of the P-type semiconductor layer; forming a plurality of first conductive through holes penetrating through the second isolation layer on the second isolation layer;
step S5 specifically includes: step S12, disposing a first transparent conductive layer on the side of the first isolation layer away from the upper surface of the N-type electrode extension bar and the second isolation layer, wherein the first transparent conductive layer is disposed on the P-type semiconductor layer through the first conductive via and electrically connected to the P-type semiconductor layer; the first isolation layer is disposed between the first transparent conductive layer and the N-type pad electrode.
Preferably, the upper surface of the first isolation layer is flush with the upper surface of the P-type semiconductor layer;
after step S5 and before step S6, the method further includes: step S21, forming a third isolation layer on the upper surface of the first transparent conductive layer; forming a plurality of second conductive through holes penetrating through the third isolation layer at positions, corresponding to the third isolation layer, where the N-type electrode extension strips are not arranged;
step S22, forming a second transparent conductive layer on the upper surface of the third isolation layer;
step S6 specifically includes: step S23, forming the P-type electrode extension bar and the P-type pad electrode on the second transparent conductive layer; the second transparent conducting layer is arranged on the first transparent conducting layer through the second conducting through hole and is electrically connected with the first transparent conducting layer.
Preferably, step S22 is followed by: and a third isolating layer is arranged between the N-type pad electrode and the first transparent conducting layer and between the N-type pad electrode and the second transparent conducting layer.
Through the technical scheme, the following effects are achieved:
1. the light blocking area of the electrode is reduced by arranging the overlapping position of the N-type electrode expansion strip and the P-type electrode expansion strip in the horizontal direction;
2. by arranging the first isolation layer and the third isolation layer, the N-type electrode is insulated from the active region, the P-type semiconductor layer, the first transparent conducting layer and the second transparent conducting layer, so that electric leakage of the light-emitting diode is effectively avoided;
3. the second isolation layer is provided with a plurality of first conductive through holes penetrating through the second isolation layer, so that the current expansion effect is improved, and the light emitting efficiency of the diode is improved;
4. through being equipped with the second transparent conducting layer on third isolation layer upper surface, the second transparent conducting layer is located on the first transparent conducting layer and is formed the electricity with first transparent conducting layer through second electrically conductive through-hole and be connected, has increased the electric current extension area, makes the electric current extension effect better, further improves emitting diode efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a light emitting diode according to an embodiment of the present invention;
fig. 2 is a top view of a light emitting diode according to an embodiment of the present invention;
fig. 3 to fig. 8 are schematic structural diagrams corresponding to steps of a method for manufacturing a light emitting diode according to embodiment 2 of the present invention;
fig. 9 to fig. 16 are schematic structural diagrams corresponding to steps of a method for manufacturing a light emitting diode according to embodiment 4 of the present invention;
fig. 17 to fig. 26 are schematic structural diagrams corresponding to steps of a method for manufacturing a light emitting diode according to embodiment 6 of the present invention.
The symbols in the drawings illustrate that:
101. the semiconductor device comprises a substrate, 102, an N-type semiconductor layer, 103, an active region, 104, a P-type semiconductor layer, 105, an N-type pad electrode, 106, an N-type electrode extension strip, 107, a first isolation layer, 108, a first transparent conducting layer, 109, a P-type pad electrode, 110, a P-type electrode extension strip, 111, a second isolation layer, 112, a third isolation layer, 113, a second transparent conducting layer, A, a groove, B, a first conducting through hole, C and a second conducting through hole.
Detailed Description
For the clarity of the disclosure, the following description will be made with reference to the accompanying drawings. The invention is not limited to this specific embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The light emitting diode provided by the present embodiment, as shown in fig. 1 and fig. 2, includes:
a substrate 101;
an epitaxial layer structure disposed on the surface of the substrate 101; the epitaxial layer structure includes: the N-type semiconductor layer 102, the active region 103 and the P-type semiconductor layer 104 are sequentially overlapped on the substrate 101 from bottom to top;
a groove A extending towards the N-type semiconductor layer 102 is formed in the upper surface of the P-type semiconductor layer 104, and the N-type semiconductor layer 102 is exposed; an N-type pad electrode 105 and an N-type electrode expansion strip 106 are arranged on the surface of the N-type semiconductor layer 102 in the groove A; the N-type pad electrode 105 and the N-type electrode expansion strip 106 are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove A;
a first isolation layer 107 is arranged between the side wall of the groove A and the N-type electrode and on the upper surface of the N-type electrode expansion strip 106; a first transparent conducting layer 108 is arranged on one side of the first isolation layer 107, which is far away from the upper surface of the N-type electrode extension bar 106, and the P-type semiconductor layer 104, and the first transparent conducting layer 108 is electrically connected with the P-type semiconductor layer 104; the first transparent conductive layer 108 is provided with a P-type electrode extension bar 110 and a P-type pad electrode 109, and the P-type pad electrode 109 and the P-type electrode extension bar 110 are electrically connected to form a P-type electrode;
the N-type electrode extension bar 106 and the P-type electrode extension bar 110 are overlapped in the horizontal direction;
the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer 108 are set.
In the embodiment, the light blocking area of the electrode can be reduced by arranging the N-type electrode extension strips 106 and the P-type electrode extension strips 110 to be overlapped in the horizontal direction; a first isolation layer 107 is disposed between the sidewall of the recess a and the N-type electrode and on the upper surface of the N-type electrode extension bar 106, so that the N-type electrode is insulated from the active region 103, the P-type semiconductor layer 104, and the first transparent conductive layer 108, thereby effectively avoiding the electrical leakage of the light emitting diode.
Example 2
The present embodiment provides a method for manufacturing a light emitting diode, as shown in fig. 3 to 8, for manufacturing the light emitting diode of embodiment 1, the method includes the following steps:
step S101, providing a substrate 101, and forming an epitaxial layer structure on the substrate 101, wherein the epitaxial layer structure comprises an N-type semiconductor layer 102, an active region 103 and a P-type semiconductor layer 104 which are sequentially formed on the substrate 101 from bottom to top;
step S102, forming a groove a extending to the N-type semiconductor layer 102 on the upper surface of the P-type semiconductor layer 104, and exposing the N-type semiconductor layer 102;
step S103, forming an N-type pad electrode 105 and an N-type electrode expansion strip 106 on the surface of the N-type semiconductor layer 102 in the groove A; the N-type pad electrode 105 and the N-type electrode expansion strip 106 are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove A;
step S104, arranging a first isolation layer 107 between the side wall of the groove A and the N-type electrode and on the upper surface of the N-type electrode expansion strip 106;
step S105, disposing a first transparent conductive layer 108 on a side of the first isolation layer 107 away from the upper surface of the N-type electrode extension bar 106 and on the P-type semiconductor layer 104, wherein the first transparent conductive layer 108 is electrically connected to the P-type semiconductor layer 104;
step S106, arranging a P-type electrode expansion strip 110 and a P-type pad electrode 109 on the first transparent conductive layer 108, wherein the P-type pad electrode 109 and the P-type electrode expansion strip 110 are electrically connected to form a P-type electrode; the N-type electrode extension bar 106 and the P-type electrode extension bar 110 are overlapped in the horizontal direction; the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer 108 are set.
Example 3
The light emitting diode provided by the present embodiment, as shown in fig. 16, includes:
a substrate 101;
an epitaxial layer structure disposed on the surface of the substrate 101; the epitaxial layer structure includes: the N-type semiconductor layer 102, the active region 103 and the P-type semiconductor layer 104 are sequentially overlapped on the substrate 101 from bottom to top;
a groove A extending towards the N-type semiconductor layer 102 is formed in the upper surface of the P-type semiconductor layer 104, and the N-type semiconductor layer 102 is exposed; an N-type pad electrode 105 and an N-type electrode expansion strip 106 are arranged on the surface of the N-type semiconductor layer 102 in the groove A; the upper surfaces of the N-type electrode extension strips 106 are flush with the upper surface of the P-type semiconductor layer 104; the N-type pad electrode 105 and the N-type electrode expansion strip 106 are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove A;
a first isolation layer 107 is arranged between the side wall of the groove A and the N-type electrode and on the upper surface of the N-type electrode expansion strip 106; a second isolation layer 111 is arranged on the upper surface of the P-type semiconductor layer 104; the second barrier layer 111 is integrally provided with the first barrier layer 107; as shown in fig. 13, the second isolation layer 111 is provided with a plurality of first conductive vias B penetrating through the second isolation layer 111, the first conductive vias B have at least two different via sizes, the via size far away from the N-type electrode spreading bar 106 is larger than the via size near the N-type electrode spreading bar 106, the current can be controlled by adjusting the size, arrangement and number of the vias, and the arrangement, number and shape of the first conductive vias B are not limited to the case shown in fig. 13; a first transparent conducting layer 108 is arranged on one side of the first isolation layer 107, which is far away from the upper surface of the N-type electrode extension bar 106, and on the P-type semiconductor layer 104, and the first isolation layer 107 is arranged between the first transparent conducting layer 108 and the N-type pad electrode 105; FIG. 2 is a top view of the present embodiment, and FIG. 15 is a schematic cross-sectional view taken along line AA-AA in FIG. 2; as shown in fig. 15, the first transparent conductive layer 108 is disposed on the P-type semiconductor layer 104 through the first conductive via B and electrically connected to the P-type semiconductor layer 104; the first transparent conductive layer 108 is provided with a P-type electrode extension bar 110 and a P-type pad electrode 109, and the P-type pad electrode 109 and the P-type electrode extension bar 110 are electrically connected to form a P-type electrode;
the N-type electrode extension bar 106 and the P-type electrode extension bar 110 are overlapped in the horizontal direction;
the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer 108 are set.
On the basis of the foregoing embodiment 1, the second isolation layer 111 is disposed on the upper surface of the P-type semiconductor layer 104, and the second isolation layer 111 is disposed with a plurality of first conductive vias B penetrating through the second isolation layer 111, so as to improve the current spreading effect and improve the light emitting efficiency of the diode.
Example 4
The present embodiment provides a method for manufacturing a light emitting diode, as shown in fig. 9 to 16, for manufacturing the light emitting diode of embodiment 3, the method includes the following steps:
step S201, providing a substrate 101, and forming an epitaxial layer structure on the substrate 101, where the epitaxial layer structure includes an N-type semiconductor layer 102, an active region 103, and a P-type semiconductor layer 104, which are sequentially formed on the substrate 101 from bottom to top;
step S202, forming a groove a extending toward the N-type semiconductor layer 102 on the upper surface of the P-type semiconductor layer 104, and exposing the N-type semiconductor layer 102;
step S203, forming an N-type pad electrode 105 and an N-type electrode expansion bar 106 on the surface of the N-type semiconductor layer 102 in the groove A; the upper surfaces of the N-type electrode extension strips 106 are flush with the upper surface of the P-type semiconductor layer 104; the N-type pad electrode 105 and the N-type electrode expansion strip 106 are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove A;
step S204, arranging a first isolation layer 107 between the side wall of the groove A and the N-type electrode and on the upper surface of the N-type electrode expansion strip 106; forming a second isolation layer 111 integrally formed with the first isolation layer 107 on the upper surface of the P-type semiconductor layer 104 while the first isolation layer 107 is disposed; as shown in fig. 13, a plurality of first conductive vias B penetrating through the second isolation layer 111 are formed in the second isolation layer 111;
step S205, disposing a first transparent conductive layer 108 on a side of the first isolation layer 107 away from the upper surface of the N-type electrode extension bar 106 and the second isolation layer 111, as shown in fig. 2, which is a top view of the present embodiment, fig. 15 is a schematic cross-sectional view along line AA-AA in fig. 2, as shown in fig. 15, the first transparent conductive layer 108 is disposed on the P-type semiconductor layer 104 through the first conductive via B and electrically connected to the P-type semiconductor layer 104; the first isolation layer 107 is provided between the first transparent conductive layer 108 and the N-type pad electrode 105;
step S206, providing a P-type electrode extension bar 110 and a P-type pad electrode 109 on the first transparent conductive layer 108, and electrically connecting the P-type pad electrode 109 and the P-type electrode extension bar 110 to form a P-type electrode; the N-type electrode extension bar 106 and the P-type electrode extension bar 110 are overlapped in the horizontal direction; the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer 108 are set.
Example 5
The light emitting diode provided by the present embodiment, as shown in fig. 26, includes:
a substrate 101;
an epitaxial layer structure disposed on the surface of the substrate 101; the epitaxial layer structure includes: the N-type semiconductor layer 102, the active region 103 and the P-type semiconductor layer 104 are sequentially overlapped on the substrate 101 from bottom to top;
a groove A extending towards the N-type semiconductor layer 102 is formed in the upper surface of the P-type semiconductor layer 104, and the N-type semiconductor layer 102 is exposed; an N-type pad electrode 105 and an N-type electrode expansion strip 106 are arranged on the surface of the N-type semiconductor layer 102 in the groove A; the N-type pad electrode 105 and the N-type electrode expansion strip 106 are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove A;
a first isolation layer 107 is arranged between the side wall of the groove A and the N-type electrode and on the upper surface of the N-type electrode expansion strip 106; the upper surface of the first isolation layer 107 is flush with the upper surface of the P-type semiconductor layer 104; a first transparent conducting layer 108 is arranged on one side of the first isolation layer 107, which is far away from the upper surface of the N-type electrode extension bar 106, and the P-type semiconductor layer 104, and the first transparent conducting layer 108 is electrically connected with the P-type semiconductor layer 104; the third isolation layer 112 is disposed on the upper surface of the first transparent conductive layer 108; as shown in fig. 23, a plurality of second conductive vias C penetrating through the third isolation layer 112 are disposed at positions of the third isolation layer 112 corresponding to positions where the N-type electrode spreading bars 106 are not disposed, where the second conductive vias C have at least two different via sizes, the via size far away from the N-type electrode spreading bars 106 is larger than the via size near the N-type electrode spreading bars 106, and the current magnitude can be controlled by adjusting the via size, arrangement, and number, and the arrangement, number, and shape of the second conductive vias C are not limited to the cases shown in fig. 23; the second transparent conductive layer 113 is arranged on the upper surface of the third isolation layer 112; FIG. 2 is a top view of the present embodiment, and FIG. 25 is a schematic cross-sectional view taken along line AA-AA in FIG. 2; as shown in fig. 25, the second transparent conductive layer 113 is disposed on the first transparent conductive layer 108 through the second conductive via C and electrically connected to the first transparent conductive layer 108; the P-type electrode extension bar 110 and the P-type pad electrode 109 are arranged on the second transparent conductive layer 113; the P-type pad electrode 109 and the P-type electrode extension bar 110 are electrically connected to form a P-type electrode; the third isolation layer 112 is disposed between the N-type pad electrode 105 and the first and second transparent conductive layers 108 and 113;
the N-type electrode extension bar 106 and the P-type electrode extension bar 110 are overlapped in the horizontal direction;
the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer 108 are set.
In this embodiment, on the basis of the foregoing embodiment 1, the third isolation layer 112 is disposed on the upper surface of the first transparent conductive layer 108, a plurality of second conductive through holes C penetrating through the third isolation layer 112 are disposed at positions of the third isolation layer 112 corresponding to the positions where the N-type electrode extension bars 106 are not disposed, so as to improve the current extension effect and improve the light emitting efficiency of the diode, and the current magnitude can be controlled by adjusting the size, arrangement manner, and number of the through holes; a second transparent conducting layer 113 is arranged on the upper surface of the third isolating layer 112, and the second transparent conducting layer 113 is arranged on the first transparent conducting layer 108 through a second conducting through hole C and is electrically connected with the first transparent conducting layer 108, so that the current spreading area is increased, the current spreading effect is better, and the efficiency of the light-emitting diode is further improved; a third isolation layer 112 is disposed between the N-type pad electrode 105 and the first transparent conductive layer 108 and the second transparent conductive layer 113, so that the N-type pad electrode is insulated from the active region 103, the P-type semiconductor layer 104, the first transparent conductive layer 108, and the second transparent conductive layer 113, thereby effectively avoiding the electrical leakage of the led.
Example 6
The present embodiment provides a method for manufacturing a light emitting diode, as shown in fig. 17 to 26, for manufacturing the light emitting diode of embodiment 5, the method includes the following steps:
step S301, providing a substrate 101, and forming an epitaxial layer structure on the substrate 101, wherein the epitaxial layer structure comprises an N-type semiconductor layer 102, an active region 103 and a P-type semiconductor layer 104 which are sequentially formed on the substrate 101 from bottom to top;
step S302, forming a groove a extending toward the N-type semiconductor layer 102 on the upper surface of the P-type semiconductor layer 104, and exposing the N-type semiconductor layer 102;
step S303, forming an N-type pad electrode 105 and an N-type electrode expansion bar 106 on the surface of the N-type semiconductor layer 102 in the groove A; the N-type pad electrode 105 and the N-type electrode expansion strip 106 are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove A;
step S304, arranging a first isolation layer 107 between the side wall of the groove A and the N-type electrode and on the upper surface of the N-type electrode expansion strip 106; the upper surface of the first isolation layer 107 is flush with the upper surface of the P-type semiconductor layer 104;
step S305, disposing a first transparent conductive layer 108 on a side of the first isolation layer 107 away from the upper surface of the N-type electrode extension bar 106 and the P-type semiconductor layer 104, wherein the first transparent conductive layer 108 is electrically connected to the P-type semiconductor layer 104;
step S306, forming a third isolation layer 112 on the upper surface of the first transparent conductive layer 108; as shown in fig. 23, a plurality of second conductive vias C penetrating through the third isolation layer 112 are formed at positions of the third isolation layer 112 corresponding to the positions where the N-type electrode extension bars 106 are not disposed;
step 307, forming a second transparent conductive layer 113 on the upper surface of the third isolation layer 112; FIG. 2 is a top view of the present embodiment, and FIG. 25 is a schematic cross-sectional view taken along line AA-AA in FIG. 2; as shown in fig. 25, the second transparent conductive layer 113 is disposed on the first transparent conductive layer 108 through the second conductive via C and electrically connected to the first transparent conductive layer 108;
step S308, forming the P-type electrode extension bar 110 and the P-type pad electrode 109 on the second transparent conductive layer 113, and electrically connecting the P-type pad electrode 109 and the P-type electrode extension bar 110 to form a P-type electrode;
the N-type electrode extension bar 106 and the P-type electrode extension bar 110 are overlapped in the horizontal direction;
the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer 108 are set;
a third isolation layer 112 is disposed between the N-type pad electrode 105 and the first and second transparent conductive layers 108 and 113.
In summary, through the above technical solution, the following effects are achieved:
1. the light blocking area of the electrode is reduced by arranging the overlapping position of the N-type electrode expansion strip and the P-type electrode expansion strip in the horizontal direction;
2. through setting up first isolation layer, third isolation layer, make N type electrode insulation in active area, P type semiconductor layer, first transparent conducting layer, second transparent conducting layer, effectively avoid emitting diode's electric leakage.
3. The second isolation layer is provided with a plurality of first conductive through holes penetrating through the second isolation layer, so that the current expansion effect is improved, the light emitting efficiency of the diode is improved, and the current can be controlled by adjusting the size, the arrangement mode and the number of the through holes;
4. through being equipped with the second transparent conducting layer on third isolation layer upper surface, the second transparent conducting layer is located on the first transparent conducting layer and is formed the electricity with first transparent conducting layer through second electrically conductive through-hole and be connected, has increased the electric current extension area, makes the electric current extension effect better, further improves emitting diode efficiency.
It will be understood by those skilled in the art that in the present disclosure, the terms "transverse," "longitudinal," "upper," "lower," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present invention and simplicity in description, but do not indicate or imply that the referenced devices or components must be in a particular orientation, constructed and operated in a particular orientation, and thus the terms should not be construed as limiting the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A light emitting diode, comprising:
a substrate;
the epitaxial layer structure is arranged on the surface of the substrate; the epitaxial layer structure includes: the N-type semiconductor layer, the active region and the P-type semiconductor layer are sequentially overlapped on the substrate from bottom to top;
the upper surface of the P-type semiconductor layer is provided with a groove extending towards the N-type semiconductor layer and exposing the N-type semiconductor layer; an N-type pad electrode and an N-type electrode expansion strip are arranged on the surface of the N-type semiconductor layer in the groove; the N-type pad electrode and the N-type electrode extension strip are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove;
a first isolating layer is arranged between the side wall of the groove and the N-type electrode and on the upper surface of the N-type electrode extension strip; a first transparent conducting layer is arranged on one side of the first isolating layer, which is far away from the upper surface of the N-type electrode extension strip, and the P-type semiconductor layer, and the first transparent conducting layer is electrically connected with the P-type semiconductor layer; the first transparent conducting layer is provided with a P-type electrode extension strip and a P-type pad electrode, and the P-type pad electrode and the P-type electrode extension strip are electrically connected to form a P-type electrode;
the N-type electrode expansion strip and the P-type electrode expansion strip are overlapped in the horizontal direction;
and the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer are set.
2. The led of claim 1, wherein: a second isolation layer is arranged on the upper surface of the P-type semiconductor layer; the second isolation layer is provided with a plurality of first conductive through holes penetrating through the second isolation layer; the first transparent conducting layer is arranged on the P-type semiconductor layer through the first conducting through hole and is electrically connected with the P-type semiconductor layer; the first isolation layer is arranged between the first transparent conducting layer and the N-type pad electrode.
3. The led of claim 2, wherein the top surface of the N-type electrode extension bar is flush with the top surface of the P-type semiconductor layer, and the second isolation layer is integrally formed with the first isolation layer.
4. The led of claim 1, wherein: the transparent conductive film further comprises a third isolating layer and a second transparent conductive layer; the third isolating layer is arranged on the upper surface of the first transparent conducting layer; a plurality of second conductive through holes penetrating through the third isolation layer are formed in the third isolation layer corresponding to the positions where the N-type electrode extension strips are not arranged; the second transparent conducting layer is arranged on the upper surface of the third isolating layer; the P-type electrode extension bar and the P-type pad electrode are arranged on the second transparent conducting layer; the second transparent conducting layer is arranged on the first transparent conducting layer through the second conducting through hole and is electrically connected with the first transparent conducting layer; and the third isolating layer is arranged between the N-type pad electrode and the first transparent conducting layer and between the N-type pad electrode and the second transparent conducting layer.
5. The LED of claim 4, wherein the upper surface of the first isolation layer is flush with the upper surface of the P-type semiconductor layer.
6. The light-emitting diode according to any one of claims 2 to 5, wherein: the first conductive through hole has at least two different through hole sizes, and the size of the through hole far away from the N-type electrode expansion strip is larger than that of the through hole close to the N-type electrode expansion strip; the second conductive through hole has at least two different through hole sizes, and the through hole size far away from the N-type electrode extension strip is larger than the through hole size close to the N-type electrode extension strip.
7. A method for manufacturing a light emitting diode according to claim 1, wherein the method comprises the following steps:
step S1, providing a substrate, and forming an epitaxial layer structure on the substrate, wherein the epitaxial layer structure comprises an N-type semiconductor layer, an active region and a P-type semiconductor layer which are sequentially formed on the substrate from bottom to top;
step S2, forming a groove extending toward the N-type semiconductor layer on the upper surface of the P-type semiconductor layer, and exposing the N-type semiconductor layer;
step S3, forming an N-type pad electrode and an N-type electrode expansion strip on the surface of the N-type semiconductor layer in the groove; the N-type pad electrode and the N-type electrode extension strip are electrically connected to form an N-type electrode, and the N-type electrode is arranged at a distance from the side wall of the groove;
step S4, arranging a first isolating layer between the side wall of the groove and the N-type electrode and on the upper surface of the N-type electrode expansion strip;
step S5, arranging a first transparent conducting layer on one side of the first isolating layer, which is far away from the upper surface of the N-type electrode extension strip, and the P-type semiconductor layer, wherein the first transparent conducting layer is electrically connected with the P-type semiconductor layer;
step S6, arranging a P-type electrode expansion strip and a P-type pad electrode on the first transparent conductive layer, wherein the P-type pad electrode and the P-type electrode expansion strip are electrically connected to form a P-type electrode; the N-type electrode expansion strip and the P-type electrode expansion strip are overlapped in the horizontal direction; and the distances between the N-type electrode and the P-type electrode and between the N-type electrode and the first transparent conductive layer are set.
8. The method according to claim 7, wherein the upper surface of the N-type electrode extension bar is flush with the upper surface of the P-type semiconductor layer;
the step S4, while providing the first isolation layer, further includes a step S11 of forming a second isolation layer integrally formed with the first isolation layer on the upper surface of the P-type semiconductor layer; forming a plurality of first conductive through holes penetrating through the second isolation layer on the second isolation layer;
step S5 specifically includes: step S12, disposing a first transparent conductive layer on the side of the first isolation layer away from the upper surface of the N-type electrode extension bar and the second isolation layer, wherein the first transparent conductive layer is disposed on the P-type semiconductor layer through the first conductive via and electrically connected to the P-type semiconductor layer; the first isolation layer is disposed between the first transparent conductive layer and the N-type pad electrode.
9. The method of claim 7, wherein the method comprises the steps of:
the upper surface of the first isolation layer is flush with the upper surface of the P-type semiconductor layer;
after step S5 and before step S6, the method further includes: step S21, forming a third isolation layer on the upper surface of the first transparent conductive layer; forming a plurality of second conductive through holes penetrating through the third isolation layer at positions, corresponding to the third isolation layer, where the N-type electrode extension strips are not arranged;
step S22, forming a second transparent conductive layer on the upper surface of the third isolation layer;
step S6 specifically includes: step S23, forming the P-type electrode extension bar and the P-type pad electrode on the second transparent conductive layer; the second transparent conducting layer is arranged on the first transparent conducting layer through the second conducting through hole and is electrically connected with the first transparent conducting layer.
10. The method of claim 9, further comprising, after step S22: and a third isolating layer is arranged between the N-type pad electrode and the first transparent conducting layer and between the N-type pad electrode and the second transparent conducting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911078014.4A CN110752278A (en) | 2019-11-06 | 2019-11-06 | Light emitting diode and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911078014.4A CN110752278A (en) | 2019-11-06 | 2019-11-06 | Light emitting diode and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110752278A true CN110752278A (en) | 2020-02-04 |
Family
ID=69282439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911078014.4A Pending CN110752278A (en) | 2019-11-06 | 2019-11-06 | Light emitting diode and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110752278A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114171646A (en) * | 2020-09-11 | 2022-03-11 | 成都辰显光电有限公司 | Micro light-emitting diode and preparation method thereof |
-
2019
- 2019-11-06 CN CN201911078014.4A patent/CN110752278A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114171646A (en) * | 2020-09-11 | 2022-03-11 | 成都辰显光电有限公司 | Micro light-emitting diode and preparation method thereof |
| CN114171646B (en) * | 2020-09-11 | 2023-05-26 | 成都辰显光电有限公司 | Micro light emitting diode and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102683534B (en) | Vertical type alternating-current light-emitting diode device and manufacturing method thereof | |
| CN103515365B (en) | A kind of high-power compression joint type IGBT device | |
| CN104620399A (en) | Wafer level light-emitting diode array | |
| JP2013522905A (en) | Improved multi-junction LED | |
| CN107689408A (en) | Light emitting diode flip crystal grain and display | |
| CN106981550B (en) | Easy-packaging easy-heat-dissipation inverted high-voltage LED chip | |
| CN101188345A (en) | Semiconductor laser array and its making method | |
| CN203481226U (en) | Large power crimping type IGBT device | |
| CN204289528U (en) | A kind of high voltage LED chip with triangle echo area | |
| CN110752278A (en) | Light emitting diode and manufacturing method thereof | |
| CN103618042B (en) | A kind of semiconductor light-emitting diode chip | |
| CN103579438A (en) | Light-emitting component and manufacturing method thereof | |
| CN102820315B (en) | A kind of directly micro-array of display device of light emitting-type and preparation method thereof | |
| CN210866229U (en) | Light-emitting diode | |
| TWI496299B (en) | Electrode structure and solar cell using the same | |
| US20110180136A1 (en) | Thin film solar cell structure and method of patterning electrode of the same | |
| CN102237353A (en) | LED (light emitting diode) packaging structure and manufacturing method thereof | |
| CN204538077U (en) | LED chip and use the light-emitting device of this LED chip | |
| CN103047575B (en) | Light-emitting diode light bar and manufacture method thereof | |
| CN101982875B (en) | Packaging structure of N substrate diode half bridges with common anodes in TO-220 | |
| CN107516702A (en) | Hinder flip LED chips in a kind of anti-top | |
| CN106206883A (en) | A kind of upside-down mounting high voltage LED chip | |
| CN103594591B (en) | There is the manufacture method of the inverted light-emitting diode (LED) of transparency electrode | |
| CN203589085U (en) | Semiconductor LED chip | |
| CN204460062U (en) | Light source, lighting device can be cut |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |