CN110751922B - Display panel and display device - Google Patents
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- CN110751922B CN110751922B CN201911063328.7A CN201911063328A CN110751922B CN 110751922 B CN110751922 B CN 110751922B CN 201911063328 A CN201911063328 A CN 201911063328A CN 110751922 B CN110751922 B CN 110751922B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2003—Display of colours
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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Abstract
The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and effectively improves the phenomenon of color cast. The display panel includes: a substrate base plate; a display area and a non-display area; the pixel array comprises a first pixel array and a second pixel array, the first pixel array comprises a first sub-pixel, the second pixel array comprises a second sub-pixel, and the luminous efficiency of the first sub-pixel is greater than that of the second sub-pixel; a data line connected to the pixel column; the power signal line comprises a longitudinal power signal line, the longitudinal power signal line comprises a first longitudinal power line and a second longitudinal power line, the first longitudinal power line is connected with the first pixel column, and the second longitudinal power line is connected with the second pixel column; and the compensation signal line comprises a first compensation signal line, the first compensation signal line is connected with the first longitudinal power line, and the first compensation signal line and the first longitudinal power line connected with the first compensation signal line are overlapped in a direction perpendicular to the plane of the substrate base plate.
Description
[ technical field ] A
The invention relates to the technical field of display, in particular to a display panel and a display device.
[ background of the invention ]
The display panel is provided with sub-pixels with multiple colors, such as a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the color of light emitted by the display panel can be adjusted by respectively adjusting the light emitting brightness of the sub-pixels with the colors. However, the current display panel has a significant color shift phenomenon when displaying a picture, for example, when the display panel displays a white picture, the top area of the display panel is blue and the bottom area of the display panel is yellow, thereby affecting the display quality.
[ summary of the invention ]
In view of this, embodiments of the present invention provide a display panel and a display device, which can effectively improve the color shift phenomenon.
In one aspect, an embodiment of the present invention provides a display panel, including:
a base substrate;
a display area and a non-display area surrounding the display area;
a plurality of pixel columns arranged in a first direction, the pixel columns including a first pixel column and a second pixel column, wherein the first pixel column includes a plurality of first sub-pixels arranged in a second direction, the second pixel column includes a plurality of second sub-pixels arranged in the second direction, the first sub-pixels have a light emitting efficiency greater than that of the second sub-pixels, and the first direction intersects the second direction;
a data line extending in the second direction, the data line being electrically connected to the pixel column;
a power supply signal line including a longitudinal power supply signal line extending in the second direction, the longitudinal power supply signal line including a first longitudinal power supply line electrically connected to the first pixel column and a second longitudinal power supply line electrically connected to the second pixel column;
the compensation signal line comprises a first compensation signal line which is electrically connected with a first longitudinal power line, and the first compensation signal line and the first longitudinal power line which is electrically connected with the first compensation signal line are overlapped in a direction perpendicular to the plane of the substrate base plate.
In another aspect, an embodiment of the present invention provides a display device, including the display panel described above.
One of the above technical solutions has the following beneficial effects:
in the technical solution provided by the embodiment of the present invention, the first compensation signal line is electrically connected to the first longitudinal power line, and the first compensation signal line is overlapped with the first longitudinal power line electrically connected thereto in a direction perpendicular to the plane of the substrate, so that the first compensation signal line and the first longitudinal power line are connected in parallel, the cross-sectional area of the signal line equivalent to the first compensation signal line and the first longitudinal power line after the parallel connection is increased, the resistance of the signal line is reduced, and the attenuation degree of the power signal when transmitted on the first longitudinal power line is reduced. According to the formula of the driving current
Wherein, μ n As a migration rate of electrons, C ox Is the capacitance of the gate oxide layer in unit area,
is the channel width-to-length ratio, PVDD is the power supply signal, V data For the data signal, the driving current I and the power signal PVDD are in a direct proportion relationship, and the attenuation degree of the power signal corresponding to the first pixel column is reduced, that is, the attenuation degree of the driving current corresponding to the first pixel column is correspondingly reduced. After the attenuation degree of the driving current corresponding to the first pixel column is reduced, the driving current provided by the driving chip to the first sub-pixel in the bottom display area does not need to have too much difference with the driving current corresponding to the first sub-pixel in the middle display area, so that the degree of the driving current corresponding to the first sub-pixel in the bottom display area compared with the degree of the driving current corresponding to the first sub-pixel in the middle display area approaches the degree of the driving current corresponding to the second sub-pixel in the bottom display area compared with the degree of the driving current corresponding to the second sub-pixel in the middle display area, the color presented in the bottom display area approaches the color presented in the middle display area, and the color deviation of the bottom display area is effectively improved. Similarly, when the driving current is transmitted to the top display region, since the attenuation degree of the driving current corresponding to the first pixel row is reduced, the degree of the driving current corresponding to the first sub-pixel in the top display region being smaller than the degree of the driving current corresponding to the first sub-pixel in the middle display region approaches to the degree of the driving current corresponding to the second sub-pixel in the top display region being smaller than the degree of the driving current corresponding to the second sub-pixel in the middle display region, so that the color displayed in the top display region approaches to the color displayed in the middle display region, thereby effectively improving the color cast of the top display region.
Therefore, by adopting the technical scheme provided by the embodiment of the invention, the first longitudinal power line is compensated by utilizing the first compensation signal line, so that the attenuation degree of the driving current corresponding to the first pixel column can be effectively reduced, the color cast phenomenon can be effectively improved, and the display performance can be optimized.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a compensation signal line according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view taken along line A1-A2 of FIG. 2;
fig. 4 is a schematic structural diagram of a display panel according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of another structure of a compensation signal line according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view taken along line B1-B2 of FIG. 5;
FIG. 7 is a schematic diagram of another structure of a compensation signal line according to an embodiment of the present invention;
FIG. 8 is a cross-sectional view taken along the line C1-C2 of FIG. 7;
FIG. 9 is a schematic diagram of another structure of a compensation signal line according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of another structure of a compensation signal line according to an embodiment of the present invention;
fig. 11 is a schematic diagram illustrating a position of a first compensation signal line according to an embodiment of the invention;
FIG. 12 is a schematic diagram illustrating another exemplary position of a first compensation signal line according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.
[ detailed description ] A
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely a relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.
Before explaining the technical scheme provided by the embodiment of the invention, the invention firstly explains the principle of color cast phenomenon:
taking the display panel including the red sub-pixel, the green sub-pixel and the blue sub-pixel as an example, the driving chip is controlled to provide the data signals to the sub-pixels of each color, so as to adjust the magnitude of the driving current corresponding to the sub-pixels of each color, thereby adjusting the luminance of the sub-pixels of each color, and further adjusting the color of the light emitted by the display panel. For example, when the red sub-pixel displays 200nits, the green sub-pixel displays 520nits, and the blue sub-pixel displays 50nits, the display panel will emit white light. Due to the characteristics of the light emitting material, the light emitting efficiency of the blue sub-pixel is much smaller than that of the red sub-pixel and the green sub-pixel, for example, the light emitting efficiency of the red sub-pixel and the green sub-pixel is 40lm/w and 120lm/w, respectively, while the light emitting efficiency of the blue sub-pixel is only 5lm/w, and since the driving current is inversely proportional to the light emitting efficiency, when the display panel is driven to emit white light with a certain luminance, the driving current corresponding to the blue sub-pixel is larger than the driving current corresponding to the red sub-pixel and the green sub-pixel, and exemplarily, the driving current corresponding to the red sub-pixel is Ir = a, the driving current corresponding to the green sub-pixel is Ig = B, and the driving current corresponding to the blue sub-pixel is Ib = C, ir: ig: ib =1.
It will be appreciated that there is inevitable attenuation of the data signal during transmission, resulting in attenuation of the drive current. In order to improve the viewing experience of a user, in the display region, at least the accurate luminance of the middle display region is required to be ensured, so that the driving current Ir1 provided by the driving chip to the red sub-pixel in the bottom display region (the side of the display region close to the driving chip) needs to be greater than a, the driving current Ig1 provided by the driving chip to the green sub-pixel in the bottom display region needs to be greater than B, and the driving current Ib1 provided by the driving chip to the blue sub-pixel in the bottom display region needs to be greater than C, so that the driving current Ir2= a corresponding to the red sub-pixel, the driving current Ig2= B corresponding to the green sub-pixel, and the driving current Ib2= C corresponding to the blue sub-pixel in the middle display region can be ensured. Further, since the attenuation degree of the driving current is inversely proportional to the magnitude of the driving current, i.e., the attenuation degree of the driving current Ib corresponding to the blue sub-pixel is smaller than the attenuation degree of the driving currents Ir and Ig corresponding to the red sub-pixel and the green sub-pixel during transmission, the increase degree of Ib1 compared to C is smaller than the increase degree of Ir1 compared to a and the increase degree of Ig1 compared to B, for example, the driving currents Ir1 corresponding to the red sub-pixel, the green sub-pixel and the blue sub-pixel in the bottom display region: ig1: ib1= 1.1. Similarly, when the driving current is transmitted to the top display area (the side far from the driving chip in the display area), the side far from the driving chip, that is, the driving current Ir3 corresponding to the red sub-pixel, the green sub-pixel and the blue sub-pixel in the top display area: ig3: ib3= 0.8.
Based on this, an embodiment of the present invention provides a display panel, as shown in fig. 1 to fig. 3, fig. 1 is a schematic structural diagram of the display panel provided in the embodiment of the present invention, fig. 2 is a schematic structural diagram of a compensation signal line provided in the embodiment of the present invention, fig. 3 is a cross-sectional view of fig. 2 along a direction A1-A2, and the display panel includes: a base substrate 1; a display area 2 and a non-display area 3 surrounding the display area 2; a plurality of pixel columns 4, the pixel columns 4 being arranged in a first direction, the pixel columns 4 including a first pixel column 5 and a second pixel column 6, wherein the first pixel column 5 includes a plurality of first sub-pixels 7 arranged in a second direction, the second pixel column 6 includes a plurality of second sub-pixels 8 arranged in the second direction, the first sub-pixels 7 have a greater luminous efficiency than the second sub-pixels 8, and the first direction intersects the second direction; a data line 9, the data line 9 extending along a second direction, the data line 9 being electrically connected to the pixel column 4; a power supply signal line 10, the power supply signal line 10 including a longitudinal power supply signal line 11 extending in the second direction, the longitudinal power supply signal line 11 including a first longitudinal power supply line 12 and a second longitudinal power supply line 13, the first longitudinal power supply line 12 being electrically connected to the first pixel column 5, the second longitudinal power supply line 13 being electrically connected to the second pixel column 6; the compensation signal line 14, the compensation signal line 14 includes a first compensation signal line 15, the first compensation signal line 15 is electrically connected with the first longitudinal power line 12, and in the direction perpendicular to the plane of the substrate base plate 1, the first compensation signal line 15 overlaps with the first longitudinal power line 12 electrically connected therewith.
It should be noted that a power signal bus is further disposed in the display panel, one end of the vertical power signal line 11 is electrically connected to the power signal bus, and a power signal provided by the power signal bus is transmitted to the corresponding sub-pixel via the vertical power signal line 11. The first compensation signal line 15 is electrically connected to the first longitudinal power line 12, specifically, two ends of the first compensation signal line 15 are electrically connected to the first longitudinal power line 12 through via holes, or one end of the first compensation signal line 15 is electrically connected to the power signal bus, and the other end is electrically connected to the first longitudinal power line 12 through a via hole.
In the display panel provided by the embodiment of the invention, the first compensation signal line 15 is electrically connected with the first longitudinal power line 12, and in the direction perpendicular to the plane of the substrate base plate 1, the first compensation signal line 15 is overlapped with the first longitudinal power line 12 electrically connected with the first compensation signal line 15, so that the first compensation signal line and the first longitudinal power line 12 are connected in parallel, the cross-sectional area of the equivalent signal line of the first compensation signal line 15 and the first longitudinal power line 12 after being connected in parallel is increased, the resistance of the signal line is reduced, and the attenuation degree of the power signal when being transmitted on the first longitudinal power line 12 is reduced. According to the formula of the drive current
Wherein, μ n As a migration rate of electrons, C ox Is the capacitance of the gate oxide layer in unit area,
is the channel width-to-length ratio, PVDD is the power supply signal, V data For the data signal, the driving current I and the power signal PVDD are in a proportional relationship, and the attenuation degree of the power signal corresponding to the first pixel column 5 is reduced, that is, the attenuation degree of the driving current corresponding to the first pixel column 5 is correspondingly reduced.
In combination with the above analysis of the driving currents of the bottom display region, the middle display region and the top display region, after reducing the attenuation degree of the driving current corresponding to the first pixel column 5, the driving current provided by the driving chip to the first sub-pixel 7 in the bottom display region does not need to be different from the driving current corresponding to the first sub-pixel 7 in the middle display region, so that the driving current corresponding to the first sub-pixel 7 in the bottom display region is larger than the driving current corresponding to the first sub-pixel 7 in the middle display region, and approaches to the driving current corresponding to the second sub-pixel 8 in the bottom display region, and as an example, the ratio of the driving currents corresponding to the first sub-pixel 7 and the second sub-pixel 8 in the middle display region is 1.1.2, if the first compensation signal line 15 is not provided, the ratio of the driving currents corresponding to the first sub-pixel 7 and the second sub-pixel 8 in the bottom display region needs to be 1.1.01, and the color ratio of the driving currents corresponding to the second sub-pixel 8 in the middle display region is improved, so that the bottom display region exhibits an effective color ratio of the first sub-pixel 7.01 and the bottom display region. Similarly, when the driving current is transmitted to the top display region, since the attenuation degree of the driving current corresponding to the first pixel column 5 is reduced, the driving current corresponding to the first sub-pixel 7 in the top display region is smaller than the driving current corresponding to the first sub-pixel 7 in the middle display region, and approaches to the smaller degree of the driving current corresponding to the second sub-pixel 8 in the top display region than the driving current corresponding to the second sub-pixel 8 in the middle display region, for example, if the first compensation signal line 15 is not provided, the ratio of the driving currents corresponding to the first sub-pixel 7 and the second sub-pixel 8 in the top display region is 0.8.
It can be seen that, with the display panel provided in the embodiment of the present invention, the first compensation signal line 15 is used to compensate the first vertical power line 12, so that the attenuation degree of the driving current corresponding to the first pixel column 5 can be effectively reduced, the color shift phenomenon can be effectively improved, and the display performance can be optimized.
Optionally, referring to fig. 1 again, the first sub-pixels 7 include red sub-pixels and/or green sub-pixels, and the second sub-pixels 8 include blue sub-pixels. When the display panel comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel, the phenomenon that the bottom display area is yellow and the top display area is blue can be effectively improved by arranging the first compensation signal line 15.
Alternatively, as shown in fig. 4 to 6, fig. 4 is another schematic structural diagram of a display panel according to an embodiment of the present invention, fig. 5 is another schematic structural diagram of a compensation signal line according to an embodiment of the present invention, fig. 6 is a cross-sectional view of fig. 5 along a direction B1-B2, and the display area 2 includes a first display area 16 and a second display area 17 arranged along a first direction; the non-display area 3 includes a first non-display area 18 and a second non-display area 19 oppositely disposed in the second direction, wherein the second non-display area 19 includes a fan-out area 20 and a chip bonding area 21 arranged in the second direction; the data lines 9 include a first data line 22 and a second data line 23, wherein the first data line 22 is located in the first display region 16, and the second data line 23 is located in the second display region 17; the fan-out area 20 comprises a first connecting line 24 and a second connecting line 25, one end of the first connecting line 24 is electrically connected with the first data line 22, the other end of the first connecting line 24 is electrically connected with the chip binding area 21, one end of the second connecting line 25 is electrically connected with the second data line 23, the other end of the second connecting line 25 is electrically connected with the chip binding area 21, and the length of the first connecting line 24 is greater than that of the second connecting line 25; the first longitudinal power line 12 includes a first sub power line 26 and a second sub power line 27, wherein the first sub power line 26 is located in the first display region 16, and the second sub power line 27 is located in the second display region 17. The compensation signal line 14 further includes a second compensation signal line 28, the second compensation signal line 28 being electrically connected to the first sub power supply line 26, the second compensation signal line 28 overlapping the first sub power supply line 26 electrically connected thereto in a direction perpendicular to the plane of the substrate base 1.
The second compensation signal line 28 is electrically connected to the first sub power line 26, specifically, two ends of the second compensation signal line 28 are electrically connected to the first sub power line 26 through via holes, respectively, or one end of the second compensation signal line 28 is electrically connected to the power signal bus, and the other end is electrically connected to the first sub power line 26 through a via hole.
Note that, the data signal andthe voltage drop of the power supply signal exists in the transmission process, and the actual driving current received by the sub-pixel
Where Δ V is the overall voltage drop of the data signal and the power signal. The first connection line 24 electrically connected to the first data line 22 is longer than the second data line 23, so that the load of the total data signal transmission line formed by the first connection line 24 and the first data line 22 is larger, so that the attenuation degree of the data signal is larger when the data signal is transmitted on the first connection line 24 and the first data line 22, thereby causing the voltage drop of the data signal when the data signal is transmitted on the first data line 22 to be larger than the voltage drop of the data signal when the data signal is transmitted on the second data line 23, that is, the voltage drop of the data signal corresponding to the first pixel column 5 in the first display region 16 is larger than the voltage drop of the data signal corresponding to the first pixel column 5 in the second display region 17. By connecting the second compensation signal line 28 in parallel to the first sub power signal line 10, the resistance of the first sub power line 26 can be reduced, so that the voltage drop of the power signal transmitted on the first sub power line 26 is reduced, Δ V corresponding to the first pixel column 5 in the first display area 16 and Δ V corresponding to the first pixel column 5 in the second display area 17 tend to be consistent, the light emitting luminance of the first pixel column 5 in the first display area 16 and the light emitting luminance of the first pixel column 5 in the second display area 17 tend to be consistent, and the display uniformity is improved.
Alternatively, referring to fig. 4, as shown in fig. 7 and 8, fig. 7 is a schematic structural diagram of a compensation signal line according to an embodiment of the present invention, fig. 8 is a cross-sectional view taken along a direction C1-C2 of fig. 7, and the display area 2 includes a first display area 16 and a second display area 17 arranged along a first direction; the non-display area 3 includes a first non-display area 18 and a second non-display area 19 oppositely arranged in a second direction, wherein the second non-display area 19 includes a fan-out area 20 and a chip bonding area 21 arranged in the second direction; the data lines 9 include a first data line 22 and a second data line 23, wherein the first data line 22 is located in the first display region 16, and the second data line 23 is located in the second display region 17; the fan-out area 20 comprises a first connecting line 24 and a second connecting line 25, one end of the first connecting line 24 is electrically connected with the first data line 22, the other end of the first connecting line 24 is electrically connected with the chip binding area 21, one end of the second connecting line 25 is electrically connected with the second data line 23, the other end of the second connecting line 25 is electrically connected with the chip binding area 21, and the length of the first connecting line 24 is greater than that of the second connecting line 25; the second longitudinal power line 13 includes a third sub power line 29 and a fourth sub power line 30, wherein the third sub power line 29 is located in the first display region 16, and the fourth sub power line 30 is located in the second display region 17. The compensation signal line 14 further includes a third compensation signal line 31, the third compensation signal line 31 is electrically connected to the third sub power supply line 29, and the third compensation signal line 31 overlaps the third sub power supply line 29 electrically connected thereto in a direction perpendicular to the plane of the substrate base plate 1.
The third compensation signal line 31 and the third sub power line 29 may be electrically connected, specifically, two ends of the third compensation signal line 31 are electrically connected to the third sub power line 29 through via holes, respectively, or one end of the third compensation signal line 31 is electrically connected to the power signal bus, and the other end is electrically connected to the third sub power line 29 through a via hole.
Compared to the second data line 23, the first connection line 24 electrically connected to the first data line 22 is longer in length, and therefore the attenuation degree of the data signal is greater when the data signal is transmitted on the first connection line 24 and the first data line 22, so that the voltage drop of the data signal when the data signal is transmitted on the first data line 22 is greater than that when the data signal is transmitted on the second data line 23, that is, the voltage drop of the data signal corresponding to the second sub-pixel 8 column in the first display area 16 is greater than that of the data signal corresponding to the second sub-pixel 8 column in the second display area 17. By connecting the third compensation signal line 31 in parallel to the third sub-power signal line 10, the resistance of the third sub-power signal line 10 can be reduced, so that the voltage drop of the power signal transmitted on the third sub-power signal line 10 is reduced, Δ V corresponding to the second pixel column 6 in the first display area 16 and Δ V corresponding to the second pixel column 6 in the second display area 17 tend to be consistent, the light emitting luminance of the second pixel column 6 in the first display area 16 and the second display area 17 tends to be consistent, and the display uniformity is improved.
Alternatively, as shown in fig. 9, fig. 9 is a schematic diagram of another structure of the compensation signal line provided by the embodiment of the present invention, in which the first connection line 24 includes a first sub-connection line 32 and a second sub-connection line 33, and a length of the first sub-connection line 32 is smaller than a length of the second sub-connection line 33; the first data line 22 comprises a first sub data line 34 and a second sub data line 35, the first sub data line 34 is electrically connected with the first sub connecting line 32, and the second sub data line 35 is electrically connected with the second sub connecting line 33; the first sub power line 26 includes a first sub power line 36 and a first second sub power line 37, the first sub power line 36 and the first sub data line 34 are electrically connected to the same first pixel row 5, and the first second sub power line 37 and the second sub data line 35 are electrically connected to the same first pixel row 5; the second compensation signal line 28 includes a second compensation line 38 and a second compensation line 39, the second compensation line 38 is electrically connected to the first power line 36, the second compensation line 39 is electrically connected to the first second power line 37, and the length of the second compensation line 38 is smaller than that of the second compensation line 39.
It should be noted that the first sub-connection lines 32 and the second sub-connection lines 33 are not specific to any two first connection lines 24, and in any two first connection lines 24, the first connection line 24 with the longer length is the first sub-connection line 32, and the first connection line 24 with the shorter length is the second sub-connection line 33. Since the length of the first sub-link line 32 is smaller than that of the second sub-link line 33, a voltage drop of the data signal on the first sub-data line 34 is smaller than that of the data signal on the second sub-data line 35. When the length of the second compensation line 38 is smaller than the length of the second minor compensation line 39, the resistance of the second compensation line 38 to the first power line 36 is reduced to a smaller extent than the resistance of the second minor compensation line 39 to the first second power line 37, so that the voltage drop of the power signal on the first power line 36 is larger than the voltage drop of the power signal on the first second power line 37, since the first sub-data line 34 and the first sub-power line 36 correspond to the same first pixel column 5, and the second sub-data line 35 and the first second sub-power line 37 correspond to the same first pixel column 5, the overall voltage drops of the data signals and the power signals corresponding to the two first pixel columns 5 tend to be consistent, thereby ensuring the uniformity of light emission between different first pixel columns 5 in the first display area 16.
Further, since the voltage drop of the power signal is larger toward the top display area, in order to reduce the voltage drop of the power signal in the top display area to a greater extent, please refer to fig. 9 again, the second compensation line 38 and the second compensation line 39 are aligned toward the end of the first non-display area 18, so as to reduce the attenuation of the power signal on the first power line 36 and the first second power line 37 in the top display area.
It should be noted that, in other alternative embodiments of the present invention, the load of different first sub power lines 26 can be adjusted by adjusting the line width and the manufacturing material of the second compensation signal line 28 electrically connected to different first sub power lines 26.
Optionally, as shown in fig. 10, fig. 10 is another schematic structural diagram of the compensation signal line provided in the embodiment of the present invention, where the non-display area 3 includes a first non-display area 18 and a second non-display area 19 that are oppositely disposed in the second direction, where the second non-display area 19 includes a fan-out area 20 and a chip bonding area 21 that are arranged along the second direction; the power supply signal line 10 further includes a lateral power supply signal line 40 extending in the first direction, the lateral power supply signal line 40 including a first lateral power supply line 41 and a second lateral power supply line 42, the first lateral power supply line 41 being located on a side of the second lateral power supply line 42 away from the chip bonding area 21. The display panel further includes: a fourth compensation signal line 43, the fourth compensation signal line 43 being electrically connected to the first lateral power line 41, the fourth compensation signal line 43 overlapping the first lateral power line 41 electrically connected thereto in a direction perpendicular to the plane of the substrate base 1. Specifically, the fourth compensation signal line 43 is electrically connected to the first horizontal power line 41, and two ends of the fourth compensation signal line 43 are electrically connected to the first horizontal power line 41 through vias.
The more the power signal is transmitted toward the first non-display region 18, the larger the voltage drop is, and therefore, by further correspondingly arranging the fourth compensation signal line 43 in parallel to the first transverse power line 41 in the top display region, the load of the first transverse power signal line 40 can be reduced, thereby effectively reducing the voltage drop of the power signal in the top display region and avoiding the overlarge difference between the power signals in the top display region and the bottom display region.
Optionally, the first compensation signal line 15 may be a single-layer metal trace or a multi-layer metal trace. When the first compensation signal line 15 is a single-layer metal trace, the thickness of the first compensation signal line 15 can be reduced, and the influence of the first compensation signal line 15 on the thickness of the display panel is further reduced.
Optionally, as shown in fig. 11, fig. 11 is a schematic diagram of a film position of the first compensation signal line provided in the embodiment of the present invention, and the display panel further includes a gate line 44 extending along a first direction; the data line 9 and the first longitudinal power line 12 are arranged in the same layer, and the data line 9 and the first longitudinal power line 12 are positioned on one side of the grid line 44, which faces away from the substrate base plate 1; the first compensation signal line 15 is located on a side of the first longitudinal power line 12 facing away from the substrate base plate 1. With this arrangement, the first compensation signal line 15 is far from the gate line 44, so that the coupling between the first compensation signal line 15 and the gate line 44 can be reduced, and the influence of the coupling capacitance on the scan signal transmitted on the gate line 44 can be reduced.
Further, as shown in fig. 12, fig. 12 is another schematic diagram of the position of the film layer of the first compensation signal line according to the embodiment of the present invention, the display panel further includes a planarization layer 45, and the planarization layer 45 is located on a side of the data line 9 opposite to the substrate base plate 1; a light-emitting element 46, wherein the light-emitting element 46 comprises an anode 47, a light-emitting layer 48 and a cathode 49 which are arranged in a stacked manner, wherein the anode 47 is positioned on the side of the planarization layer 45 opposite to the substrate base plate 1; the first compensation signal line 15 is provided in the same layer as the anode 47. It is understood that the display panel further includes a transistor 50, and the transistor 50 includes an active layer 51, a gate electrode 52, and a source/drain electrode 53, which are stacked, wherein the gate electrode 52 is disposed on the same layer as the gate line 44, and the source/drain electrode 53 is disposed on the same layer as the data line 9 and the first longitudinal power line 12.
The first compensation signal line 15 and the anode 47 are arranged in the same layer, on one hand, the first compensation signal line 15 and the anode 47 can be formed by the same composition process, so that the process flow is simplified, and on the other hand, the first compensation signal line 15 and the metal wiring in the display panel, such as the gate line 44, the data line 9, the gate electrode 52 and the source/drain electrode 53, are at least provided with the planarization layer 45 at intervals, and because the planarization layer 45 has a larger thickness, the larger interval between the first compensation signal line 15 and the metal wiring can be ensured, and the coupling between the first compensation signal line 15 and other metal wiring is reduced.
Alternatively, the first compensation signal line 15 may not be disposed on the same layer as the existing film layer in the display panel, and the first compensation signal line 15 is separately disposed on one layer, for example, the first compensation signal line 15 is disposed between the gate line 44 and the first vertical power line 12, or the first compensation signal line 15 is disposed between the first vertical power line 12 and the anode 47.
Optionally, in a direction perpendicular to the plane of the substrate base plate 1, the first longitudinal power line 12 completely covers the first compensation signal line 15, that is, the width of the first compensation signal line 15 in the direction perpendicular to the extending direction thereof is less than or equal to the width of the first longitudinal power line 12 in the direction perpendicular to the extending direction thereof, so as to avoid the first compensation signal line 15 being too wide and reduce the coupling between the first compensation signal line 15 and other metal traces on the premise that the first compensation signal line 15 is used to reduce the load of the first longitudinal power line 12.
As shown in fig. 13, fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device includes the display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 13 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
Since the display device provided by the embodiment of the present invention includes the display panel 100, by using the display device, the first compensation signal line 15 to compensate the first vertical power line 12, the attenuation degree of the driving current corresponding to the first pixel column 5 can be effectively reduced, so that the color shift phenomenon can be effectively improved, and the display performance can be optimized.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
1. A display panel, comprising:
a substrate base plate;
a display area and a non-display area surrounding the display area;
a plurality of pixel columns arranged in a first direction, the pixel columns including a first pixel column and a second pixel column, wherein the first pixel column includes a plurality of first sub-pixels arranged in a second direction, the second pixel column includes a plurality of second sub-pixels arranged in the second direction, the first sub-pixels have a light emitting efficiency greater than that of the second sub-pixels, and the first direction intersects the second direction;
a data line extending in the second direction, the data line being electrically connected to the pixel column;
a power supply signal line including a longitudinal power supply signal line extending in the second direction, the longitudinal power supply signal line including a first longitudinal power supply line electrically connected to the first pixel column and a second longitudinal power supply line electrically connected to the second pixel column;
compensation signal lines including a first compensation signal line electrically connected to a first longitudinal power line, the first compensation signal line overlapping the first longitudinal power line electrically connected thereto in a direction perpendicular to a plane in which the substrate base plate is located;
the non-display area comprises a first non-display area and a second non-display area which are oppositely arranged in the second direction, wherein the second non-display area comprises a fan-out area and a chip binding area which are arranged along the second direction;
the power signal line further comprises a transverse power signal line extending along the first direction, the transverse power signal line comprises a first transverse power line and a second transverse power line, and the first transverse power line is positioned on one side of the second transverse power line far away from the chip binding area;
the display panel further includes:
a fourth compensation signal line electrically connected to the first lateral power line, the fourth compensation signal line overlapping the first lateral power line electrically connected thereto in a direction perpendicular to a plane of the substrate base.
2. The display panel according to claim 1, wherein the plurality of first sub-pixels comprise red sub-pixels and/or green sub-pixels, and the plurality of second sub-pixels comprise blue sub-pixels.
3. The display panel according to claim 1,
the display area comprises a first display area and a second display area which are arranged along the first direction;
the data lines comprise first data lines and second data lines, wherein the first data lines are positioned in the first display area, and the second data lines are positioned in the second display area;
the fan-out area comprises a first connecting line and a second connecting line, one end of the first connecting line is electrically connected with the first data line, the other end of the first connecting line is electrically connected with the chip binding area, one end of the second connecting line is electrically connected with the second data line, the other end of the second connecting line is electrically connected with the chip binding area, and the length of the first connecting line is greater than that of the second connecting line;
the first longitudinal power line comprises a first sub power line and a second sub power line, wherein the first sub power line is positioned in the first display area, and the second sub power line is positioned in the second display area;
the compensation signal line further comprises a second compensation signal line electrically connected with the first sub power line, and the second compensation signal line is overlapped with the first sub power line electrically connected with the second compensation signal line in the direction perpendicular to the plane of the substrate base plate.
4. The display panel according to claim 1,
the display area comprises a first display area and a second display area which are arranged along the first direction;
the data lines comprise first data lines and second data lines, wherein the first data lines are positioned in the first display area, and the second data lines are positioned in the second display area;
the fan-out area comprises a first connecting line and a second connecting line, one end of the first connecting line is electrically connected with the first data line, the other end of the first connecting line is electrically connected with the chip binding area, one end of the second connecting line is electrically connected with the second data line, the other end of the second connecting line is electrically connected with the chip binding area, and the length of the first connecting line is greater than that of the second connecting line;
the second longitudinal power line comprises a third sub power line and a fourth sub power line, wherein the third sub power line is positioned in the first display area, and the fourth sub power line is positioned in the second display area;
the compensation signal line further comprises a third compensation signal line electrically connected with the third sub power supply line, and the third compensation signal line and the third sub power supply line electrically connected with the third compensation signal line are overlapped in a direction perpendicular to the plane of the substrate base plate.
5. The display panel according to claim 3,
the first connecting lines comprise first sub-connecting lines and second sub-connecting lines, and the length of the first sub-connecting lines is smaller than that of the second sub-connecting lines;
the first data line comprises a first subdata line and a second subdata line, the first subdata line is electrically connected with the first sub-connecting line, and the second subdata line is electrically connected with the second sub-connecting line;
the first sub power line comprises a first sub power line and a first second sub power line, the first sub power line and the first sub data line are electrically connected to the same first pixel row, and the first second sub power line and the second sub data line are electrically connected to the same first pixel row;
the second compensation signal line comprises a second compensation line and a second compensation line, the second compensation line is electrically connected with the first power line, the second compensation line is electrically connected with the first second power line, and the length of the second compensation line is smaller than that of the second compensation line.
6. The display panel according to claim 5,
ends of the second compensation lines and the second compensation lines toward the first non-display area are aligned.
7. The display panel according to claim 1,
the first compensation signal line is a single-layer metal routing line.
8. The display panel according to claim 1, wherein the display panel further comprises a gate line extending in the first direction;
the data line and the first longitudinal power line are arranged on the same layer, and the data line and the first longitudinal power line are positioned on one side of the grid line, which is back to the substrate; the first compensation signal line is positioned on one side of the first longitudinal power line, which is back to the substrate base plate.
9. The display panel according to claim 8, wherein the display panel further comprises:
the planarization layer is positioned on one side, opposite to the substrate, of the data line;
the light-emitting element comprises an anode, a light-emitting layer and a cathode which are arranged in a stacked mode, wherein the anode is located on one side, facing away from the substrate, of the planarization layer;
the first compensation signal line and the anode are arranged on the same layer.
10. The display panel according to claim 1,
in the direction perpendicular to the plane of the substrate base plate, the first longitudinal power line completely covers the first compensation signal line.
11. A display device comprising the display panel according to any one of claims 1 to 10.
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| CN201911063328.7A CN110751922B (en) | 2019-10-31 | 2019-10-31 | Display panel and display device |
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| CN201911063328.7A CN110751922B (en) | 2019-10-31 | 2019-10-31 | Display panel and display device |
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| CN112750400B (en) * | 2020-12-31 | 2022-07-22 | 长沙惠科光电有限公司 | Voltage compensation structure of display substrate |
| CN115398639B (en) * | 2021-07-30 | 2023-07-14 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| CN114387882B (en) * | 2021-12-31 | 2024-05-03 | 上海中航光电子有限公司 | Display panel and display device |
| CN114975478A (en) * | 2022-04-24 | 2022-08-30 | 厦门天马微电子有限公司 | Display panel and display device |
| CN117501841A (en) * | 2022-05-31 | 2024-02-02 | 京东方科技集团股份有限公司 | Light-emitting substrate, preparation method thereof and light-emitting device |
| CN115240585B (en) * | 2022-06-27 | 2023-07-18 | 惠科股份有限公司 | Display driving circuit and display device |
| WO2024007313A1 (en) * | 2022-07-08 | 2024-01-11 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| CN115775528A (en) * | 2022-10-28 | 2023-03-10 | 惠科股份有限公司 | Pixel circuit and display panel |
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| KR100600332B1 (en) * | 2004-08-25 | 2006-07-14 | 삼성에스디아이 주식회사 | Light emitting display |
| KR102072216B1 (en) * | 2013-03-26 | 2020-02-03 | 삼성디스플레이 주식회사 | Organic light emitting diode display |
| CN107910352B (en) * | 2017-11-20 | 2020-03-24 | 武汉天马微电子有限公司 | Organic light-emitting display panel and display device |
| CN109166886A (en) * | 2018-08-20 | 2019-01-08 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and OLED show equipment |
| CN109036139B (en) * | 2018-08-24 | 2021-04-20 | 武汉天马微电子有限公司 | Foldable display panel and display device |
| CN208753327U (en) * | 2018-11-08 | 2019-04-16 | 京东方科技集团股份有限公司 | Display base plate and display device |
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Effective date of registration: 20211104 Address after: No.8, liufangyuan Henglu, Donghu New Technology Development Zone, Wuhan City, Hubei Province Applicant after: WUHAN TIANMA MICROELECTRONICS Co.,Ltd. Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 201201 Applicant before: SHANGHAI TIANMA AM-OLED Co.,Ltd. |
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