JP2022098890A - Multi-display - Google Patents

Abstract

To provide a multi-display in which the degradation of the image quality between adjacent ones of display panel units and degradation of the image quality caused by reduction of the accuracy of the display panel units are suppressed.SOLUTION: A first display panel unit 2A located in the center and two second display panel units 2B located across the first display panel unit 2A are provided in one direction in a plane of a display screen. The first display panel unit 2A includes: a first steady region W1 in which pixel units are lined in one direction at intervals of a; and a first transient region W2 in which the interval of the pixel units lining in one direction continuously changes from a to a+2b from both sides of the first steady region W1 to the boundary of the second display panel units 2B. The second display panel units 2B include a second steady region W3 in which the interval of the pixel units lining in one direction is a+2b.SELECTED DRAWING: Figure 20

Description

The present invention relates to a multi-display.

For example, an organic EL display device (organic EL display) using an organic electroluminescence (EL) element has high brightness and self-luminous emission, can be driven by DC low voltage, and has high responsiveness. Since it emits light from a solid organic film, it has excellent display performance and can be made thinner, lighter, and consume less power. Therefore, it is expected as a display device to replace the liquid crystal display device in the future (see, for example, Patent Document 1 below).

Specifically, the organic EL display device includes a display panel including a display area in which a plurality of pixels are arranged in a matrix in a plane. The display panel includes a plurality of scanning lines (gate lines), a plurality of signal lines (data lines), and a plurality of power supply lines (power supply lines) arranged horizontally and vertically in the plane of the display area. Each region is partitioned by the scanning lines and a plurality of signal lines, and a pixel circuit constituting the above-mentioned pixels is provided.

The display panel includes an organic EL element which is a light emitting element, a capacitor which is a holding capacity, and two thin film transistor (TFT) elements which are switching elements as a pixel circuit. In the display panel, the potential (image data) of the signal line is held in the holding capacitance connected to the signal line via the selection TFT element by the switching operation of the selection TFT element connected to the scanning line. Further, a drive current flows through the organic EL element connected to the power supply line via the drive TFT element according to the potential of the holding capacity. This makes it possible to make the organic EL element emit light (light).

Further, the display panel is provided with a peripheral area called a bezel (picture frame) so as to surround the periphery of the display area. In the peripheral area, a plurality of connecting portions corresponding to each of the plurality of scanning lines and the plurality of signal lines drawn out of the display area are provided side by side in the horizontal direction and the vertical direction of the peripheral area. ing. The plurality of scanning lines and the plurality of signal lines are electrically connected to an external drive circuit (driver) via a flexible printed wiring board (FPC) connected to the plurality of connecting portions.

By the way, as a multi-display, when a plurality of display panels are arranged in a plane and displayed as one screen, there is a problem that the peripheral area of the display panel described above becomes an obstacle.

Therefore, in the conventional multi-display, the bezel is made inconspicuous by providing a reflective member or a light guide member that covers the bezel between the display panels adjacent to each other (for example, Patent Document 2 below). , 3).

On the other hand, in multi-display, by reducing the peripheral area of the display panel or eliminating the peripheral area, it is possible to make the seams between the panels inconspicuous while keeping the pixel spacing between the display panels adjacent to each other constant. It is possible.

However, it is necessary to provide a cutting margin at the end of the display panel at the seam between the panels because the alignment of the cut surface is misaligned when the panel is cut and the cutting position changes depending on the thickness.

For example, as shown in FIG. 36, when the pixel spacing in the display panel DP is a'' and the cutting margin at the end of the display panel DP is b'', the pixel spacing between the adjacent display panel DPs is set. It becomes a'' + 2b''. In the case of this configuration, there is a problem that the image quality of the seam deteriorates due to the discontinuity of the pixel spacing between the display panel DPs.

On the other hand, as shown in FIG. 37, when all the pixel spacings in the display panel DP are a ″ + 2b ″, it is possible to suppress the deterioration of the image quality due to the seams. However, in the display panel DP, in order to improve the image quality, there is a demand for higher definition, and a reduction in the pixel size is required. Therefore, in the case of this configuration, since the pixel size becomes large, it becomes difficult to achieve high definition of the display panel DP.

Japanese Unexamined Patent Publication No. 2013-105148 Japanese Unexamined Patent Publication No. 2012-145843 Japanese Unexamined Patent Publication No. 2012-150366

The present invention has been proposed in view of such conventional circumstances, and suppresses deterioration of image quality between display panel units adjacent to each other and deterioration of image quality due to deterioration of the definition of the display panel units. The purpose is to provide a multi-display that makes it possible.

In order to achieve the above object, the present invention provides the following means.
[1] A plurality of pixels corresponding to at least the three primary colors of red, green, and blue are regarded as one pixel unit, and a plurality of display panel units including a display area in which the pixel units are periodically arranged in a plane are formed. Prepare,
A multi-display in which the display areas of the plurality of display panel units constitute one display screen by abutting adjacent objects of the plurality of display panel units against each other.
Of the plurality of display panel units, at least one first display panel unit located in the center and two second display panel units located on both sides of the first display panel unit are described above. It is provided side by side in one direction within the plane of the display screen.
When the width of the pixel unit in the one direction is a and the width of the margins provided on both sides of the pixel unit in the one direction is b.
The first display panel unit is a boundary between a first stationary region in which the distance between the pixel units arranged in one direction is a and the second display panel unit from both sides of the first stationary region. Includes a first transient region in which the spacing between the pixel units aligned in one direction changes continuously from a to a + 2b.
The second display panel unit is a multi-display characterized by including a second stationary region in which the distance between the pixel units arranged in one direction is a + 2b.
[2] Of the plurality of display panel units, at least one centrally located first display panel unit and eight second display panel units surrounding the first display panel unit are formed. , Provided side by side in the one direction and the other direction intersecting in the plane of the display screen.
When the width of the pixel unit in the other direction is a'and the width of the margins provided on both sides of the pixel unit in the other direction is b'.
The first display panel unit includes a third stationary region in which the distance between the pixel units arranged in the other direction is a', and the second display panel unit from both sides of the third stationary region. Includes a second transient region in which the spacing of the pixel units lined up in the other direction towards the boundary changes continuously from a'to a'+ 2b'.
The multi-display according to the above [1], wherein the second display panel unit includes a fourth stationary region in which the distance between the pixel units arranged in the other direction is a'+ 2b'.
[3] A plurality of pixels corresponding to at least the three primary colors of red, green, and blue are regarded as one pixel unit, and a plurality of display panel units including a display area in which the pixel units are periodically arranged in a plane are formed. Prepare,
A multi-display in which the display areas of the plurality of display panel units constitute one display screen by abutting adjacent objects of the plurality of display panel units against each other.
Of the plurality of display panel units, at least one first display panel unit located in the center, two second display panel units located on both sides of the first display panel unit, and the first display panel unit. The display panel unit 1 and the two third display panel units located on both sides of the second display panel unit are provided side by side in one direction in the plane of the display screen.
When the width of the pixel unit in the one direction is a and the width of the margins provided on both sides of the pixel unit in the one direction is b.
The first display panel unit includes a first stationary region in which the distance between the pixel units arranged in the one direction is a.
The second display panel unit is a boundary between a second stationary region in which the distance between the pixel units arranged in one direction is a and the second display panel unit from both sides of the second stationary region. Includes a first transient region in which the spacing between the pixel units aligned in one direction changes continuously from a to a + 2b.
The third display panel unit is a multi-display characterized by including a third stationary region in which the distance between the pixel units arranged in one direction is a + 2b.
[4] At least the first display panel unit located at the center of the plurality of display panel units, eight second display panel units surrounding the first display panel unit, and the second display panel unit. Sixteen third display panel units surrounding the periphery of the second display panel unit are provided side by side in one direction and the other direction intersecting in the plane of the display screen.
When the width of the pixel unit in the other direction is a'and the width of the margins provided on both sides of the pixel unit in the other direction is b'.
The first display panel unit includes a fourth stationary region in which the distance between the pixel units arranged in the other direction is a'.
The second display panel unit includes a fifth stationary region in which the distance between the pixel units arranged in the other direction is a'and the second display panel unit from both sides of the fifth stationary region. Includes a second transient region in which the spacing of the pixel units lined up in the other direction towards the boundary changes continuously from a'to a'+ 2b'.
The multi-display according to the above [3], wherein the third display panel unit includes a sixth stationary region in which the distance between the pixel units arranged in the other direction is a'+ 2b'.

As described above, according to the present invention, there is provided a multi-display capable of suppressing deterioration of image quality between display panel units adjacent to each other and deterioration of image quality due to deterioration of definition of the display panel units. It is possible to do.

It is a top view which shows the structure of the multi-display which concerns on one Embodiment of this invention. It is sectional drawing which shows the structure of a multi-display. It is a circuit diagram which shows the structure of a display panel unit. It is a circuit diagram which shows the structure of a pixel circuit. It is sectional drawing of the main part which shows the structure of a display panel unit. It is sectional drawing which shows the structure of a pixel circuit board. It is a perspective plan view which shows the structure of a pixel circuit board. It is a perspective plan view which shows another structure of a pixel circuit board. It is a perspective plan view which shows another structure of a pixel circuit board. It is a perspective plan view which shows another structure of a pixel circuit board. It is a top view which looked at the display panel unit from the back side. It is sectional drawing for demonstrating the process of manufacturing a pixel circuit board. It is sectional drawing for demonstrating the process of manufacturing a pixel circuit board. It is sectional drawing for demonstrating the process of manufacturing a pixel circuit board. It is sectional drawing for demonstrating the process of manufacturing a pixel circuit board. It is sectional drawing for demonstrating the process of manufacturing a pixel circuit board. It is sectional drawing for demonstrating the process of manufacturing a pixel circuit board. It is sectional drawing for demonstrating the process of manufacturing a pixel circuit board. It is sectional drawing for demonstrating the process of manufacturing a pixel circuit board. It is a schematic diagram for demonstrating the structure of the multi-display which concerns on 1st Embodiment of this invention. It is a top view which shows the structure of the 1st display panel unit provided in the multi-display shown in FIG. It is a top view which shows the structure of the 2nd display panel unit provided in the multi-display shown in FIG. It is a perspective view which shows the curved structure of the multi-display shown in FIG. It is a schematic diagram for demonstrating the configuration which added the 2nd display panel unit of the multi-display shown in FIG. It is a schematic diagram for demonstrating the structure of the multi-display which concerns on the 2nd Embodiment of this invention. It is a top view which shows the structure of the 1st display panel unit provided in the multi-display shown in FIG. It is a top view which shows the structure of the 2nd display panel unit provided in the multi-display shown in FIG. It is a schematic diagram for demonstrating the structure of the multi-display which concerns on 3rd Embodiment of this invention. It is a top view which shows the structure of the 1st display panel unit provided in the multi-display shown in FIG. 28. It is a top view which shows the structure of the 2nd display panel unit provided in the multi-display shown in FIG. 28. It is a top view which shows the structure of the 3rd display panel unit provided in the multi-display shown in FIG. 28. It is a schematic diagram for demonstrating the structure of the multi-display which concerns on 4th Embodiment of this invention. It is a top view which shows the structure of the 1st display panel unit provided in the multi-display shown in FIG. 32. It is a top view which shows the structure of the 2nd display panel unit provided in the multi-display shown in FIG. 32. It is a top view which shows the structure of the 3rd display panel unit provided in the multi-display shown in FIG. 32. It is a schematic diagram for demonstrating the case where the pixel spacing between display panels adjacent to each other is a'' + 2b''. It is a schematic diagram for demonstrating the case where the pixel spacing in a display panel is all a'' + 2b''.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In addition, in the drawings used in the following explanation, in order to make the features easy to understand, the featured parts may be schematically shown for convenience, and the number of each component, the dimensional ratio, etc. are the same as the actual ones. Is not always. Further, the materials, dimensions, etc. exemplified in the following description are examples, and the present invention is not necessarily limited to them, and the present invention can be appropriately modified without changing the gist thereof. ..

(Multi-display)
First, as an embodiment of the present invention, for example, the multi-display 1 shown in FIGS. 1 to 11 will be described.

Note that FIG. 1 is a plan view showing the configuration of the multi-display 1. FIG. 2 is a cross-sectional view showing the configuration of the multi-display 1. FIG. 3 is a circuit diagram showing the configuration of the display panel unit 2. FIG. 4 is a circuit diagram showing the configuration of the pixel circuit 3. FIG. 5 is a cross-sectional view of a main part showing the configuration of the display panel unit 2. FIG. 6 is a cross-sectional view showing the configuration of the pixel circuit board 4. FIG. 7 is a perspective plan view showing the configuration of the pixel circuit board 4. FIG. 8 is a perspective plan view showing another configuration of the pixel circuit board 4. FIG. 9 is a perspective plan view showing another configuration of the pixel circuit board 4. FIG. 10 is a perspective plan view showing another configuration of the pixel circuit board 4. FIG. 11 is a plan view of the display panel unit 2 as viewed from the back surface side.

As shown in FIGS. 1 and 2, the multi-display 1 of the present embodiment includes a plurality of display panel units 2 including a display area E in which a plurality of pixels P are arranged side by side in a plane, and a plurality of display panel units. It is provided with a support substrate 50 that supports 2 in an in-plane arrangement.

In the multi-display 1, a plurality of display panel units 2 are attached to one surface side of the support substrate 50 in a state where adjacent objects of the plurality of display panel units 2 are butted against each other. Display area E constitutes one display screen S.

The display panel unit 2 is an organic EL display device (organic EL display) that performs color display using an organic EL element.

Specifically, as shown in FIGS. 3, 4, and 5, the display panel unit 2 has a pixel circuit board 4 provided with a pixel circuit 3 constituting the pixel P.

The pixel circuit board 4 has a plurality of scanning lines 5 arranged in one direction (vertical direction in FIGS. 3 and 4) intersecting in the plane of the display area E, and another direction (vertical direction) intersecting in the plane of the display area E. A plurality of signal lines 6 and a plurality of power supply lines 7 arranged in a horizontal direction in FIGS. 3 and 4 are included. The pixel circuit board 4 has a structure in which a pixel circuit 3 is provided for each region partitioned by the plurality of scanning lines 5, the plurality of signal lines 6, and the plurality of power supply lines 7.

Further, the display panel unit 2 has a plurality of pixels (referred to as “sub-pixels”) P corresponding to at least the three primary colors of red (R), green (G), and blue (B) as one pixel unit (“pixel””. The pixel unit Pu has a structure in which the pixel units Pu are periodically arranged side by side in the plane.

In the present embodiment, the pixel P corresponding to red (R), the pixel P corresponding to green (G), and the pixel P corresponding to blue (B) are periodically arranged in other directions, whereby 1 One pixel unit Pu is configured. Further, in the present embodiment, the rectangular pixel units Pu in the plan view are arranged side by side in a matrix in the plane of the rectangular display area E in the plan view, so that the display panel has a rectangular shape in the plan view. Unit 2 is configured.

The pixel unit Pu is not necessarily limited to the above-described configuration, and for example, in addition to the pixels P corresponding to the red (R), green (G), and blue (B), the white (W) is used. It is also possible to configure by four pixels P including the pixel P corresponding to. Further, the configuration is not limited to the configuration in which the plurality of pixels P corresponding to the color display described above are arranged, and the configuration in which the plurality of pixels P corresponding to the monochrome display are arranged is also possible. Further, the display area E and the display panel unit 2 are not necessarily limited to the rectangular shape described above, and the plan view shape thereof can be appropriately changed.

As shown in FIGS. 4 and 6, the pixel circuit 3 includes an organic EL element 8 which is a light emitting element, a capacitor 9 which is a holding capacity C, and two TFT elements (selection TFT element 10 and a drive) which are switching elements. The TFT element 11) is provided.

The organic EL element 8 has a structure in which a pixel electrode 13, an organic functional layer 14, and a common electrode 15 are sequentially laminated on one surface (surface in FIG. 6) of a substrate 12 constituting a pixel circuit board 4. Have. That is, the organic EL element 8 has a structure in which the organic functional layer 14 is sandwiched between the pixel electrode 13 serving as the positive electrode (+) and the common electrode 15 serving as the negative electrode (−).

The substrate 12 is made of a flexible substrate such as a plastic substrate. In the present embodiment, as the substrate 12, for example, a film-shaped plastic substrate having a thickness of 10 μm or less is used. A resin material such as polyimide is used for the plastic substrate.

The substrate 12 is not necessarily limited to the configuration using the flexible substrate described above, and a configuration using a rigid substrate such as a glass substrate is also possible.

The pixel electrode 13 is provided corresponding to each of the plurality of pixels P. A metal electrode material such as aluminum (Al) is used for the pixel electrode 13. The pixel electrode 13 is formed on the interlayer insulating layer 16 that covers the surface on which the two TFT elements 10 and 11 described later are formed. For the interlayer insulating layer 16, for example, silicon oxide (SiO _x ) or the like is used. The pixel electrode 13 is electrically connected to the source electrode 11s side of the driving TFT element 11.

The organic functional layer 14 has, for example, a structure in which a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are sequentially laminated (referred to as “heterostructure”). ing. A bank layer 17 is provided on the interlayer insulating layer 16 except on the surface of the pixel electrode 13. For the bank layer 17, for example, a coating type organic insulating material or the like is used. The organic functional layer 14 is embedded and formed inside the bank layer 17.

The common electrode 15 constitutes one solid electrode common among the plurality of pixels P. For the common electrode 15, a transparent electrode material such as indium tin oxide (ITO) is used. The common electrode 15 is formed so as to cover the surface on which the organic functional layer 14 and the bank layer 17 are formed. Further, a protective layer 18 is formed on the common electrode 15 so as to cover the entire surface of the substrate 12. For the protective layer 18, for example, a coating type organic insulating material or the like is used.

The common electrode 15 is electrically connected to the GND wire 19. The GND wire 19 is provided on the surface of the gate insulating layer 20 constituting the two TFT elements 10 and 11 described later. The GND wire 19 is electrically connected to the common electrode 15 via a contact plug 21a penetrating the interlayer insulating layer 16, a contact electrode 21b formed on the interlayer insulating layer 16 and a contact plug 21c penetrating the bank layer 17. Has been done.

In the organic EL element 8, holes injected / transported from the pixel electrode 13 side via the hole injection layer and the hole transport layer, and holes injected / transported from the common electrode side via the electron injection layer and the electron transport layer. It is possible to emit light by recombining the electrons with the light emitting layer in the light emitting layer.

The organic EL element 8 has a top emission structure that extracts light from one surface side of the substrate 12 (hereinafter, one surface of the substrate 12 is referred to as a “front surface” and the other surface of the substrate 12 is referred to as a “back surface”. Distinguish as.).

Further, when color display is performed using the organic EL element 8, the organic EL element that emits white light is combined with a color filter corresponding to red (R), green (G), and blue (B). .. Alternatively, an organic EL element that emits each color light of red light, green light, and blue light may be combined.

In the holding capacitance C, one end side of the capacitor 9 is electrically connected to the source electrode 10s side of the selection TFT element 10 and the gate electrode 11g side of the driving TFT element 11, and the other end side of the capacitor 9 is the driving TFT element 11. It is provided in a state of being electrically connected to the source electrode 11s side.

The two TFT elements 10 and 11 are provided side by side on the substrate 12. Oxide semiconductors such as indium (In) -tin (Sn) -zinc (Zn) oxide (InSnZnO) are used for the two TFT elements 10 and 11. Further, the oxide semiconductor may be an oxide containing at least one metal element such as In, gallium (Ga), Zn, Sn, and Al, and may be a polycrystalline silicon, an amorphous silicon, an organic semiconductor, or the like. There may be. For the gate insulating layer 20, for example, silicon oxide (SiO _x ) or the like is used.

In the selection TFT element 10, the gate electrode 10g is electrically connected to the scanning line 5, the drain electrode 10d is electrically connected to the signal line 6, and the source electrode 10s holds the gate electrode 11g of the driving TFT element 11. It is provided in a state of being electrically connected to one end side of the capacitance C (capacitor 9).

In the driving TFT element 11, the gate electrode 10g is electrically connected to the source electrode 10s of the selection TFT element 10 and the holding capacity C (one end side of the capacitor 9), and the drain electrode 11d is electrically connected to the power supply line 7. The source electrode 11s is provided in a state of being electrically connected to the pixel electrode 13 and the other end side of the holding capacity C (capacitor 9).

In the display panel unit 2, the potential (image data) of the signal line 6 is held in the holding capacitance C via the selection TFT element 10 by the switching operation of the selection TFT element 10. Further, a drive current from the power supply line 7 flows through the organic EL element 8 via the drive TFT element 11 according to the potential of the holding capacity C. As a result, the organic EL element 8 can be made to emit light (lights up).

By the way, as shown in FIGS. 5, 6 and 7, the pixel circuit board 4 of the present embodiment is arranged with a plurality of first wirings 31 arranged on the surface side of the board 12 in the thickness direction of the board 12. It has a plurality of contact plugs 32, a plurality of second wirings 33 arranged on the back surface side of the substrate 12, and a plurality of connection portions 34 arranged on the back surface side of the substrate 12.

The plurality of first wirings 31 are electrically connected to each of the plurality of pixel circuits 3. The plurality of contact plugs 32 are electrically connected to each of the plurality of first wirings 31. The plurality of second wirings 33 are electrically connected to each of the plurality of contact plugs 32. That is, the first wiring 31 and the second wiring 33 are electrically connected via the contact plug 32.

The first wiring 31 and the second wiring 33 are linearly patterned using a conductive material such as copper, aluminum, molybdenum, or chromium. The contact plug 32 is formed by embedding it in a contact hole penetrating the substrate 12 using a conductive material such as copper, aluminum, molybdenum, or chromium.

The first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the plurality of scanning lines 5. That is, each scanning line 5 is routed from the front surface side to the back surface side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

Further, the first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the plurality of signal lines 6. That is, each signal line 6 is routed from the front surface side to the back surface side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

The plurality of connection portions 34 electrically connect each of the plurality of second wiring 33 and each of the plurality of terminals provided on one end side of the flexible printed wiring board (FPC) 35.

The connecting portion 34 uses a connecting material such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP) so as to traverse the ACF or ACP between the plurality of second wirings 33. By forming and providing conductivity at a position overlapping with each second wiring 33 while maintaining insulation between each second wiring 33, each of the second wiring 33 and each terminal of the FPC 35 can be connected to each other. The FPC 35 and the pixel circuit board 4 are bonded to each other while being electrically connected to each other.

The plurality of scanning lines 5 are connected to the FPC 35 (hereinafter, if necessary, "first flexible printed wiring") via the plurality of connection portions 34 (hereinafter, referred to as "first connection portion 34A" if necessary). It is electrically connected to the board (FPC) 35A ".

The first connecting portions 34A are provided side by side in one direction (vertical direction in FIG. 7) for each line sequence corresponding to each of the plurality of scanning lines 5. The first FPC35A is provided with a scanning line drive circuit (gate driver) 36 including, for example, a shift register and a level shifter. The plurality of scanning lines 5 are electrically connected to the gate driver 36 via the first FPC35A. The gate driver 36 sequentially supplies scanning signals to the plurality of scanning lines 5, and switches the drive of the selection TFT element 10 in response to the scanning signals.

The plurality of signal lines 6 are connected to the FPC 35 (hereinafter, if necessary, "second flexible printed wiring") via the plurality of connection portions 34 (hereinafter, referred to as "second connection portion 34B" if necessary). It is electrically connected to the board (FPC) 35B ".

The second connection portion 34B is provided side by side in another direction (horizontal direction in FIG. 7) for each line sequence corresponding to each of the plurality of signal lines 6. The second FPC35B is provided with a signal line drive circuit (data driver) 37 including, for example, a shift register, a level shifter, a video line, an analog switch, and the like. The plurality of signal lines 6 are electrically connected to the data driver 37 via the second FPC 35B. The data driver 37 supplies image data to a plurality of signal lines 6.

In the area overlapping the display area E of the pixel circuit board 4 in a plan view, a plurality of contact plugs 32 (hereinafter, “first contact” as necessary) are used for each line sequence corresponding to each of the plurality of scanning lines 5. (Distinguished as "plug 32A") are provided side by side in one direction (vertical direction in FIG. 7).

The plurality of first contact plugs 32A are located inside the plurality of first connection portions 34A in the region, and each second wiring 33 (hereinafter, if necessary, “first back surface wiring 33A””. It is electrically connected to one end side of). On the other hand, the plurality of first connection portions 34A are located on one end side (right end side in FIG. 7) in another direction (horizontal direction in FIG. 7) in the region, and the other end of each first back surface wiring 33A. It is electrically connected to the side.

Further, in the area overlapping the display area E of the pixel circuit board 4 in a plan view, a plurality of contact plugs 32 (hereinafter, "second" as necessary) are used for each line sequence corresponding to each of the plurality of signal lines 6. The contact plug 32B ”is provided side by side in another direction (horizontal direction in FIG. 7).

The plurality of second contact plugs 32B are located inside the plurality of second connection portions 34B in the region, and each of the second wiring 33 (hereinafter, "second back surface wiring 33B" as necessary). It is electrically connected to one end side of). On the other hand, the plurality of second connection portions 34B are located on one end side (upper end side in FIG. 7) in one direction (vertical direction in FIG. 7) in the region, and the other end of each second back surface wiring 33B. It is electrically connected to the side.

Further, the first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the plurality of power supply lines 7. That is, each power line 7 is routed from the front surface side to the back surface side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

The plurality of first wirings 31 provided corresponding to each of the plurality of power supply lines 7 are the plurality of contact plugs 32 provided corresponding to each of the plurality of power supply lines 7 (hereinafter, if necessary, ". Electrically connected to one common second wiring 33 (hereinafter, if necessary, distinguished as "third back surface wiring 33C") via "third contact plug 32C"). Has been done.

A plurality of third contact plugs 32C are provided side by side in one direction (vertical direction in FIG. 7) in a region overlapping the display region E of the pixel circuit board 4 in a plan view. The plurality of third contact plugs 32C are located on the other end side (left end side in FIG. 7) in the other direction (horizontal direction in FIG. 7) in the region, and are located in one direction (vertical direction in FIG. 7). It is electrically connected to the extending third back surface wiring 33C.

Further, the first wiring 31, the contact plug 32 and the second wiring 33 are provided corresponding to the GND line 19. That is, the GND line 19 is routed from the front surface side to the back surface side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

The first wiring 31 provided corresponding to the GND line 19 is distinguished as a plurality of contact plugs 32 provided corresponding to the GND line 19 (hereinafter, as necessary, as a "fourth contact plug 32D"). It is electrically connected to one common second wiring 33 (hereinafter, referred to as "fourth back surface wiring 33D" if necessary) via a common second wiring 33.

A plurality of fourth contact plugs 32D are provided side by side in one direction (vertical direction in FIG. 7) in a region overlapping the display region E of the pixel circuit board 4 in a plan view. The plurality of fourth contact plugs 32D are located on the other end side (left end side in FIG. 7) in the other direction (horizontal direction in FIG. 7) in the region, and are located in one direction (vertical direction in FIG. 7). It is electrically connected to the extending fourth back surface wiring 33D.

The pixel circuit board 4 is provided with an interlayer insulating layer 38 that covers the back surface of the board 12. The first back surface wiring 33A and the third back surface wiring 33C are electrically connected to the first contact plug 32A and the third contact plug 32C penetrating the substrate 12 and the interlayer insulating layer 38. On the other hand, the second back surface wiring 33B and the fourth back surface wiring 33D are electrically connected to the second contact plug 32B and the fourth contact plug 32D penetrating the substrate 12.

As a result, a part of the first back surface wiring 33A and a part of the second back surface wiring 33B are arranged so as to intersect each other. Further, the third back surface wiring 33C and a part of the second back surface wiring 33B are arranged so as to intersect each other.

In the display panel unit 2 having the above configuration, a plurality of connection portions 34 (first connection portion 34A and second connection portion 34B) are provided in an area that overlaps with the display area E described above in a plan view. ing. As a result, the first FPC35A and the second FPC35B are connected via the plurality of connecting portions 34 in the area overlapping the display area E of the display panel unit 2 in a plan view, and the first FPC35A and the second FPC35A and the second FPC35A are connected. The gate driver 36 and the data driver 37 provided on the FPC 35B can be arranged on the back surface side of the pixel circuit board 4.

Further, the region overlapping the display region E of the pixel circuit board 4 in a plan view substantially coincides with the outer shape of the substrate 12. As a result, it is not necessary to provide a peripheral area for arranging the gate driver 36 and the data driver 37 outside the display area E, and the peripheral area of the display panel unit 2 can be reduced.

Therefore, in the multi-display 1 of the present embodiment, when a plurality of display panel units 2 are arranged in a plane and displayed as one screen, it is possible to configure a seamless (inconspicuous) display screen S.

The display panel unit 2 illustrates the configuration of the pixel circuit board 4 as shown in FIG. 7 described above, but the configuration is not necessarily limited to such a configuration. For example, FIGS. 8 to 10 show. It is also possible to have the configuration shown below.

Specifically, in the pixel circuit board 4 shown in FIG. 8, a plurality of first contact plugs 32A are placed on one end side (horizontal direction in FIG. 8) in a region overlapping the display region E in a plan view. It is located on the left end side in FIG. 6), is arranged side by side in one direction (vertical direction in FIG. 8), and is electrically connected to one end side of each first back surface wiring 33A.

On the other hand, the plurality of first connection portions 34A are located inside the plurality of first contact plugs 32A in the region, are arranged side by side in one direction (vertical direction in FIG. 8), and each of them. It is electrically connected to the other end side of the first back surface wiring 33A.

Further, in the area overlapping the display area E in a plan view, the plurality of second contact plugs 32B are located on one end side (upper end side in FIG. 8) in one direction (vertical direction in FIG. 8), and the other. (Horizontal direction in FIG. 8), they are arranged side by side, and are electrically connected to one end side of each second back surface wiring 33B.

On the other hand, the plurality of second connection portions 34B are located inside the plurality of second contact plugs 32B in the region, are arranged side by side in other directions (horizontal direction in FIG. 8), and each of them. It is electrically connected to the other end side of the second back surface wiring 33B.

As described above, in the pixel circuit board 4 shown in FIG. 8, the first contact plug 32A and the second contact plug 32B can be arranged side by side at the end of the region overlapping the display region E in a plan view. ..

On the other hand, in the pixel circuit board 4 shown in FIG. 9, a plurality of first contact plugs 32A are located on the center side in another direction (horizontal direction in FIG. 9) in the region overlapping with the display region E in a plan view. Therefore, they are arranged side by side in one direction (vertical direction in FIG. 9) and are electrically connected to one end side of each first back surface wiring 33A.

On the other hand, the plurality of first connection portions 34A are located outside the plurality of first contact plugs 32A in the region, and are arranged side by side in one direction (vertical direction in FIG. 9), and each of them is arranged. It is electrically connected to the other end side of the first back surface wiring 33A.

Further, in the area overlapping the display area E in a plan view, the plurality of second contact plugs 32B are located on the center side in one direction (vertical direction in FIG. 9) and in the other direction (horizontal in FIG. 9). They are arranged side by side in the direction) and are electrically connected to one end side of each second back surface wiring 33B.

On the other hand, the plurality of second connection portions 34B are located outside the plurality of second contact plugs 32B in the region, and are arranged side by side in other directions (horizontal direction in FIG. 9), and each of them is arranged. It is electrically connected to the other end side of the second back surface wiring 33B.

As described above, in the pixel circuit board 4 shown in FIG. 9, the first contact plug 32A and the second contact plug 32B can be arranged side by side in the central portion in the region overlapping the display region E in a plan view. ..

On the other hand, in the pixel circuit board 4 shown in FIG. 10, a plurality of first contact plugs 32A are arranged in one diagonal direction (diagonal to the right in FIG. 10) in a region overlapping the display region E in a plan view. It is arranged and electrically connected to one end side of each first back surface wiring 33A.

On the other hand, the plurality of first connection portions 34A are located outside the plurality of first contact plugs 32A in the region, and are arranged side by side in one diagonal direction (diagonal to the right in FIG. 10). At the same time, it is electrically connected to the other end side of each first back surface wiring 33A.

Further, in the area overlapping the display area E in a plan view, a plurality of second contact plugs 32B are arranged side by side in the diagonal direction of the other (diagonally to the left in FIG. 10), and the back surface of each second contact plug 32B is arranged side by side. It is electrically connected to one end side of the wiring 33B.

On the other hand, the plurality of second connection portions 34B are located outside the plurality of second contact plugs 32B in the region, and are arranged side by side in the other diagonal direction (diagonal to the left in FIG. 10). At the same time, it is electrically connected to the other end side of each second back surface wiring 33B.

As described above, in the pixel circuit board 4 shown in FIG. 10, the first contact plug 32A and the second contact plug 32B are arranged side by side in the diagonal direction (diagonal direction) in the region overlapping the display region E in a plan view. It is possible.

Further, in the display panel unit 2, as shown in FIG. 11, on the back side thereof, a plurality of first FPC35A provided with a gate driver 36 for each line row of the plurality of scanning lines 5 are in one direction (FIG. 11). 11 is arranged side by side in the vertical direction), and a plurality of second FPC35Bs provided with a data driver 37 for each line sequence of the plurality of signal lines 6 are arranged side by side in another direction (horizontal direction in FIG. 11). It may be an arranged configuration.

Next, the manufacturing method of the display panel unit 2 will be described with reference to FIGS. 12 to 19.
12 to 19 are sectional views for explaining a process of manufacturing the pixel circuit board 4.

When manufacturing the display panel unit 2, it has a step of manufacturing a pixel circuit board 4.

In the step of manufacturing the pixel circuit board 4, first, as shown in FIG. 12, a substrate 12 formed in a film shape on the surface of the first glass substrate 101 is prepared. Then, on one surface (surface) of the substrate 12, the first wiring 31 including the scanning line 5, the signal line 6, the power supply line 7, and the GND line 19 described above, the contact plug 21a, the contact electrode 21b, and the contact are formed. The plug 21c, the selection TFT element 10 including the organic EL element 8 (pixel electrode 13, organic functional layer 14 and common electrode 15) constituting the pixel circuit 3, the capacitor 9, and the gate insulating layer 20, and the driving TFT element 11. , The interlayer insulating layer 16, the bank layer 17, and the protective layer 18 are formed.

In addition, conventionally known film forming process, photolithography process and the like can be used for these forming steps, and the forming method thereof is not particularly limited.

Next, as shown in FIG. 13, the second glass substrate 103 is attached to the uppermost layer of the substrate 12 via the adhesive layer 102.

Next, as shown in FIG. 14, the laser beam L is irradiated from the first glass substrate 101 side toward the substrate 12. At this time, the laser beam L passes through the first glass substrate 101 and is absorbed by the substrate 12, so that a part of the plastic film near the interface with the first glass substrate 101 evaporates due to heat. As a result, as shown in FIG. 15, the first glass substrate 101 can be peeled off from the other surface (back surface) of the substrate 12.

Next, as shown in FIG. 16, a contact hole 104 penetrating the substrate 12 and the gate insulating layer 20 is formed at a position where the second contact plug 32B and the fourth contact plug 32D of the substrate 12 are formed.

Next, as shown in FIG. 17, after the second contact plug 32B and the fourth contact plug 32D are embedded and formed in the contact hole 104, the second back surface wiring 33B and the fourth back surface wiring are formed on the back surface of the substrate 12. The 33D is patterned.

Next, as shown in FIG. 18, after the interlayer insulating layer 38 is formed on the back surface of the substrate 12, the substrate 12 and the interlayer insulation are formed at the positions where the first contact plug 32A and the third contact plug 32C of the substrate 12 are formed. A contact hole 105 is formed through the layer 38.

Next, as shown in FIG. 19, after the first contact plug 32A and the third contact plug 32C are embedded and formed in the contact hole 105, the first back surface wiring 33A and the third back surface wiring are formed on the back surface of the substrate 12. 33C is patterned.

Next, after forming ACPs to be the first connection portion 34A and the second connection portion 34B, the first FPC35A and the second FPC35B are formed via the first connection portion 34A and the second connection portion 34B. To connect. Finally, the second glass substrate 103 is removed together with the adhesive layer 102. This makes it possible to manufacture the display panel unit 2.

In the method of manufacturing the display panel unit 2, a plurality of connection portions 34 (first connection portion 34A and second connection portion 34B) are provided in a region overlapping the display region E described above in a plan view. It is possible to arrange the gate driver 36 and the data driver 37 provided in the FPC 35A of 1 and the data driver 37 of the second FPC 35B on the back surface side of the pixel circuit board 4. As a result, it is not necessary to provide a peripheral area for arranging the gate driver 36 and the data driver 37 outside the display area E, and it is possible to manufacture the display panel unit 2 in which the peripheral area is reduced.

Further, by using a film-shaped plastic substrate having a thickness of 10 μm or less as the substrate 12, the size (opening diameter) of the contact holes 104 and 105 described above can be miniaturized. This makes it possible to reduce the size of the pixel P and improve the definition of the display panel unit 2.

In the multi-display 1 of the present embodiment, the plurality of display panel units 2 are supported by one surface of the support substrate 50 in a state where adjacent ones of the plurality of display panel units 2 produced by the above-mentioned steps are butted against each other. It can be manufactured by sticking it to the side.

As shown in FIG. 2, the support substrate 50 is bonded to the surface side of the plurality of display panel units 2 via the first adhesive layer 51.

The support substrate 50 is made of a transparent flexible substrate such as a plastic substrate, and has a shape corresponding to the display screen S. A resin material such as polyimide is used for the plastic substrate.

The support substrate 50 is not necessarily limited to the configuration using the flexible substrate described above, and when a rigid substrate is used for the substrate 12, for example, a configuration using a transparent rigid substrate such as a glass substrate is used. It is also possible to do.

A transparent adhesive material such as an epoxy-based resin adhesive is used for the first adhesive layer 51.

Further, an antireflection layer 52 is arranged on the other surface side of the support substrate 50. The antireflection layer 52 is located on the surface side of each display panel unit 2 to prevent reflection of external light, and is composed of a film-shaped circular polarizing plate.

The antireflection layer 52 is attached to the surface of the support substrate 50 opposite to each display panel unit 2 via a second adhesive layer 53. As the second adhesive layer 53, the same one as that of the first adhesive layer 51 is used.

(First Embodiment)
Next, as the first embodiment of the present invention, the multi-display 1A shown in FIGS. 20 to 24 will be described.

Note that FIG. 20 is a schematic diagram for explaining the configuration of the multi-display 1A. FIG. 21 is a plan view showing the configuration of the first display panel unit 2A included in the multi-display 1A. FIG. 22 is a plan view showing the configuration of the second display panel unit 2B included in the multi-display 1A. FIG. 23 is a perspective view showing a curved configuration of the multi-display 1A. FIG. 24 is a schematic diagram for explaining a configuration in which a second display panel unit 2B of the multi-display 1A is added. Further, in the following description, the same parts as those of the multi-display 1 will be omitted and the same reference numerals will be given in the drawings.

As shown in FIGS. 20, 21 and 22, the multi-display 1A of the present embodiment is a first display panel unit located at the center of the three display panel units 2 constituting the multi-display 1. 2A and two second display panel units 2B located on both sides of the first display panel unit 2A are provided side by side in one direction (horizontal direction in FIG. 20) in the plane of the display screen S. Has a configured configuration.

That is, in this multi-display 1A, one first display panel unit 2A located in the center and two second display panel units 2B located on both sides of the first display panel unit 2A are displayed. It has a configuration in which the screen S is arranged in the width direction.

Here, the width of the pixel unit Pu in one direction is a, and the width of the margins provided on both sides of the pixel unit Pu in one direction is b.

The first display panel unit 2A is a boundary between a first stationary region W1 in which the distance between the pixel units Pu arranged in one direction is a and a second display panel unit 2B from both sides of the first stationary region W1. A first transient region W2 in which the distance between the pixel units Pu arranged in one direction continuously changes from a to a + 2b is included.

On the other hand, the second display panel unit 2B includes a second stationary region W3 in which the distance between the pixel units Pu arranged in one direction is a + 2b.

In this case, between the first display panel unit 2A and the second display panel unit 2B (first transient region W2), the distance between the pixel units Pu arranged in one direction is continuously from a to a + 2b. It's changing. As a result, the seam between the first display panel unit 2A and the second display panel unit 2B arranged in one direction can be made inconspicuous, and deterioration of image quality at this seam can be suppressed. ..

Further, the first steady region W1 of the first display panel unit 2A located at the center of the display screen S is the second display panel unit 2B located on both sides of the first display panel unit 2A. The interval between the pixel units Pu arranged in one direction is shorter than that of the stationary region W3 of 2. As a result, when viewing an image centered on the center of the display screen S, an image having a relatively high definition is displayed on the center side of the display screen S, which is the center of the viewing angle, and the display screen is outside the viewing angle. Even if an image having a relatively low definition is displayed outside S, it is possible to suppress deterioration of image quality due to a decrease in definition over the width direction of the display screen S.

As described above, in the multi-display 1A of the present embodiment, the deterioration of the image quality between the display panel units 2A and 2B adjacent to each other and the deterioration of the image quality due to the deterioration of the definition of the display panel units 2A and 2B are suppressed. It is possible to do.

In this embodiment, the display screen S of the multi-display 1A described above is not limited to a flat surface. For example, as shown in FIG. 23, both sides of the display screen S in the width direction are rounded (arched) inward. It may have a curved structure.

Further, in the present embodiment, in addition to the configuration of the multi-display 1A described above, as shown in FIG. 24, for example, two more on both sides of the first display panel unit 2A and the second display panel unit 2B. A second display panel unit 2B may be added to the configuration.

(Second embodiment)
Next, as a second embodiment of the present invention, the multi-display 1B shown in FIGS. 25 to 27 will be described.

Note that FIG. 25 is a schematic diagram for explaining the configuration of the multi-display 1B. FIG. 26 is a plan view showing the configuration of the first display panel unit 2A included in the multi-display 1B. FIG. 27 is a plan view showing the configuration of the second display panel unit 2B included in the multi-display 1B. Further, in the following description, the same parts as those of the multi-displays 1 and 1A will be omitted and the same reference numerals will be given in the drawings.

As shown in FIGS. 25, 26, and 27, the multi-display 1B of the present embodiment is a first display panel located at the center of a plurality of (nine in this embodiment) display panel units 2. One direction (horizontal direction in FIG. 25) and the other direction in which the unit 2A and the eight second display panel units 2B surrounding the first display panel unit 2A intersect in the plane of the display screen S. It has a configuration provided side by side (vertical direction in FIG. 25).

That is, in this multi-display 1B, one first display panel unit 2A located in the center and two second display panel units 2B located on both sides of the first display panel unit 2A are displayed. The screen S has a configuration in which the screen S is arranged in the width direction, the height direction, and the diagonal direction, respectively.

Here, the width of the pixel unit Pu in one direction is a, and the width of the margins provided on both sides of the pixel unit Pu in one direction is b.

The first display panel unit 2A is a boundary between a first stationary region W1 in which the distance between the pixel units Pu arranged in one direction is a and a second display panel unit 2B from both sides of the first stationary region W1. A first transient region W2 in which the distance between the pixel units Pu arranged in one direction continuously changes from a to a + 2b is included.

On the other hand, the second display panel unit 2B includes a second stationary region W3 in which the distance between the pixel units Pu arranged in one direction is a + 2b.

In this case, the distance between the pixel units Pu arranged in one direction is continuously changed from a to a + 2b between the first display panel unit 2A and the second display panel unit 2B. As a result, the seam between the first display panel unit 2A and the second display panel unit 2B arranged in one direction can be made inconspicuous, and deterioration of image quality at this seam can be suppressed. ..

Further, the first steady region W1 of the first display panel unit 2A located at the center of the display screen S is the second display panel unit 2B located on both sides of the first display panel unit 2A. The interval between the pixel units Pu arranged in one direction is shorter than that of the stationary region W3 of 2. As a result, when viewing an image centered on the center of the display screen S, an image having a relatively high definition is displayed on the center side of the display screen S, which is the center of the viewing angle, and the display screen is outside the viewing angle. Even if an image having a relatively low definition is displayed outside S, it is possible to suppress deterioration of image quality due to a decrease in definition over the width direction of the display screen S.

On the other hand, the width of the pixel unit Pu in the other direction is a', and the width of the margins provided on both sides of the pixel unit Pu in the other direction is b'.

The first display panel unit 2A includes a third stationary region H1 in which the distance between the pixel units Pu arranged in other directions is a', and a second display panel unit 2B from both sides of the third stationary region H1. It includes a second transient region H2 in which the distance between the pixel units Pu arranged in other directions continuously changes from a'to a'+ 2b' toward the boundary.

On the other hand, the second display panel unit 2B includes a fourth stationary region H3 in which the distance between the pixel units Pu arranged in the other direction is a'+ 2b'.

In this case, between the first display panel unit 2A and the second display panel unit 2B (second transient region H2), the distance between the pixel units Pu arranged in the other direction is continuous from a'to a + 2b'. Is changing. As a result, the seam between the first display panel unit 2A and the second display panel unit 2B arranged in the other direction can be made inconspicuous, and deterioration of image quality at this seam can be suppressed. ..

Further, the third steady-state region H1 of the first display panel unit 2A located at the center of the display screen S is the second display panel unit 2B located on both sides of the first display panel unit 2A. The distance between the pixel units Pu arranged in other directions is shorter than that of the steady region H3 of No. 4 by 2b. As a result, when viewing an image centered on the center of the display screen S, an image having a relatively high definition is displayed on the center side of the display screen S, which is the center of the viewing angle, and the display screen is outside the viewing angle. Even if an image having a relatively low definition is displayed outside the S, it is possible to suppress deterioration of the image quality due to a decrease in the definition in the height direction and the diagonal direction of the display screen S. ..

As described above, in the multi-display 1B of the present embodiment, the deterioration of the image quality between the display panel units 2A and 2B adjacent to each other and the deterioration of the image quality due to the deterioration of the definition of the display panel units 2A and 2B are suppressed. It is possible to do.

In this embodiment, the display screen S of the multi-display 1B described above is not limited to a flat surface, and for example, both sides of the display screen S in the width direction are curved inward in a round (arch) shape. There may be.

Further, in the present embodiment, in addition to the configuration of the multi-display 1B described above, for example, 16 second display panel units 2B surrounding the periphery of the second display panel unit 2B may be added.

(Third embodiment)
Next, as a third embodiment of the present invention, the multi-display 1C shown in FIGS. 28 to 31 will be described.

Note that FIG. 28 is a schematic diagram for explaining the configuration of the multi-display 1C. FIG. 29 is a plan view showing the configuration of the first display panel unit 2C included in the multi-display 1C. FIG. 30 is a plan view showing the configuration of the second display panel unit 2D included in the multi-display 1C. FIG. 31 is a plan view showing the configuration of the third display panel unit 2E included in the multi-display 1C. Further, in the following description, the same parts as those of the multi-display 1 will be omitted and the same reference numerals will be given in the drawings.

As shown in FIGS. 28 to 31, the multi-display 1C of the present embodiment includes a first display panel unit 2C located at the center of a plurality of (five in the present embodiment) display panel units 2. , Two second display panel units 2D located on both sides of the first display panel unit 2C, and two located on both sides of the first display panel unit 2C and the second display panel unit 2D. The third display panel unit 2E has a configuration provided side by side in one direction (horizontal direction in FIG. 28) in the plane of the display screen S.

That is, the multi-display 1C includes one first display panel unit 2C located in the center, two second display panel units 2D located on both sides of the first display panel unit 2C, and a first display panel unit 2D. The display panel unit 2C and the two third display panel units 2E located on both sides of the second display panel unit 2D are arranged side by side in the width direction of the display screen S.

Here, the width of the pixel unit Pu in one direction is a, and the width of the margins provided on both sides of the pixel unit Pu in one direction is b.

The first display panel unit 2C includes a first stationary region W4 in which the distance between the pixel units Pu arranged in one direction is a.

On the other hand, the second display panel unit 2D includes a second stationary region W5 in which the distance between the pixel units Pu arranged in one direction is a, and a third display panel unit 2E from both sides of the second stationary region W5. It includes a first transient region W6 in which the distance between the pixel units Pu arranged in one direction continuously changes from a to a + 2b toward the boundary of.

On the other hand, the third display panel unit 2E includes a third stationary region W7 in which the distance between the pixel units Pu arranged in one direction is a + 2b.

In this case, between the second display panel unit 2D and the third display panel unit 2E (first transient region W6), the distance between the pixel units Pu arranged in one direction is continuously from a to a + 2b. It's changing. As a result, the seam between the second display panel unit 2D and the third display panel unit 2E arranged in one direction can be made inconspicuous, and deterioration of image quality at this seam can be suppressed. ..

Further, the first stationary region W4 of the first display panel unit 2C and the second stationary region W5 of the second display panel unit 2D located at the center of the display screen S are the first display panel unit 2C and the first stationary region W5. The distance between the pixel units Pu arranged in one direction is shorter than that of the third stationary region W7 of the third display panel unit 2E located on both sides of the second display panel unit 2D. As a result, when viewing an image centered on the center of the display screen S, an image having a relatively high definition is displayed on the center side of the display screen S, which is the center of the viewing angle, and the display screen is outside the viewing angle. Even if an image having a relatively low definition is displayed outside S, it is possible to suppress deterioration of image quality due to a decrease in definition over the width direction of the display screen S.

As described above, in the multi-display 1C of the present embodiment, the image quality deteriorates between the display panel units 2C, 2D, and 2E adjacent to each other, and the image quality deteriorates due to the deterioration of the definition of the display panel units 2C, 2D, 2E. It is possible to suppress deterioration.

In this embodiment, the display screen S of the multi-display 1C described above is not limited to a flat surface, and for example, both sides of the display screen S in the width direction are curved inward in a round (arch) shape. There may be.

Further, in the present embodiment, in addition to the configuration of the multi-display 1C described above, for example, further on both sides of the first display panel unit 2C, the second display panel unit 2D, and the third display panel unit 2E. It may be configured by adding two third display panel units 2E.

(Fourth Embodiment)
Next, as a fourth embodiment of the present invention, the multi-display 1D shown in FIGS. 32 to 35 will be described.

Note that FIG. 32 is a schematic diagram for explaining the configuration of the multi-display 1D. FIG. 33 is a plan view showing the configuration of the first display panel unit 2C included in the multi-display 1D. FIG. 34 is a plan view showing the configuration of the second display panel unit 2D included in the multi-display 1D. FIG. 35 is a plan view showing the configuration of the third display panel unit 2E included in the multi-display 1D. Further, in the following description, the same parts as those of the multi-displays 1 and 1C will be omitted and the same reference numerals will be given in the drawings.

As shown in FIGS. 32 to 35, the multi-display 1D of the present embodiment includes a first display panel unit 2C located at the center of a plurality of (25 in the present embodiment) display panel units 2. , Eight second display panel units 2D surrounding the first display panel unit 2C, and 16 third display panel units surrounding the first display panel unit 2C and the second display panel unit 2D. The 2E has a configuration provided side by side in one direction (horizontal direction in FIG. 32) and another direction (vertical direction in FIG. 32) that intersect in the plane of the display screen S.

That is, the multi-display 1D includes one first display panel unit 2C located in the center, two second display panel units 2D located on both sides of the first display panel unit 2C, and a first display panel unit 2D. The display panel unit 2C and the two third display panel units 2E located on both sides of the second display panel unit 2D are arranged side by side in the width direction, the height direction, and the diagonal direction of the display screen S, respectively. It has a configuration.

Here, the width of the pixel unit Pu in one direction is a, and the width of the margins provided on both sides of the pixel unit Pu in one direction is b.

The first display panel unit 2C includes a first stationary region W4 in which the distance between the pixel units Pu arranged in one direction is a.

On the other hand, the second display panel unit 2D includes a second stationary region W5 in which the distance between the pixel units Pu arranged in one direction is a, and a third display panel unit 2E from both sides of the second stationary region W5. It includes a first transient region W6 in which the distance between the pixel units Pu arranged in one direction continuously changes from a to a + 2b toward the boundary of.

On the other hand, the third display panel unit 2E includes a third stationary region W7 in which the distance between the pixel units Pu arranged in one direction is a + 2b.

In this case, between the second display panel unit 2D and the third display panel unit 2E (first transient region W6), the distance between the pixel units Pu arranged in one direction is continuously from a to a + 2b. It's changing. As a result, the seam between the second display panel unit 2D and the third display panel unit 2E arranged in one direction can be made inconspicuous, and deterioration of image quality at this seam can be suppressed. ..

Further, the first stationary region W4 of the first display panel unit 2C and the second stationary region W5 of the second display panel unit 2D located at the center of the display screen S are the first display panel unit 2C and the first stationary region W5. The distance between the pixel units Pu arranged in one direction is shorter than that of the third stationary region W7 of the third display panel unit 2E located on both sides of the second display panel unit 2D. As a result, when viewing an image centered on the center of the display screen S, an image having a relatively high definition is displayed on the center side of the display screen S, which is the center of the viewing angle, and the display screen is outside the viewing angle. Even if an image having a relatively low definition is displayed outside S, it is possible to suppress deterioration of image quality due to a decrease in definition over the width direction of the display screen S.

On the other hand, the width of the pixel unit Pu in the other direction is a', and the width of the margins provided on both sides of the pixel unit Pu in the other direction is b'.

The first display panel unit 2C includes a fourth stationary region H4 in which the distance between the pixel units Pu arranged in the other direction is a'.

On the other hand, in the second display panel unit 2D, the fifth stationary region H5 in which the distance between the pixel units Pu arranged in the other direction is a'and the third display panel unit 2E from both sides of the fifth stationary region H5. It includes a second transient region H6 in which the distance between the pixel units Pu arranged in the other direction continuously changes from a'to a'+ 2b' toward the boundary with and.

On the other hand, the third display panel unit 2E includes a sixth stationary region H7 in which the distance between the pixel units Pu arranged in the other direction is a'+ 2b'.

In this case, between the second display panel unit 2D and the third display panel unit 2E (second transient region H6), the distance between the pixel units Pu arranged in the other direction is continuous from a'to a + 2b'. Is changing. As a result, the seam between the second display panel unit 2D and the third display panel unit 2E arranged in the other direction can be made inconspicuous, and deterioration of image quality at this seam can be suppressed. ..

Further, the fourth steady-state region H4 of the first display panel unit 2C and the fifth steady-state region H5 of the second display panel unit 2D located at the center of the display screen S are the first display panel unit 2C and the first display panel unit 2C. The distance between the pixel units Pu arranged in other directions is shorter than that of the sixth stationary region H7 of the third display panel unit 2E located on both sides of the second display panel unit 2D. As a result, when viewing an image centered on the center of the display screen S, an image having a relatively high definition is displayed on the center side of the display screen S, which is the center of the viewing angle, and the display screen is outside the viewing angle. Even if an image having a relatively low definition is displayed outside the S, it is possible to suppress deterioration of the image quality due to a decrease in the definition in the height direction and the diagonal direction of the display screen S. ..

As described above, in the multi-display 1D of the present embodiment, the image quality deteriorates between the display panel units 2C, 2D, and 2E adjacent to each other, and the image quality deteriorates due to the deterioration of the definition of the display panel units 2C, 2D, 2E. It is possible to suppress deterioration.

In this embodiment, the display screen S of the multi-display 1D described above is not limited to a flat surface, and for example, both sides of the display screen S in the width direction are curved inward in a round (arch) shape. There may be.

Further, in the present embodiment, in addition to the configuration of the multi-display 1D described above, for example, 24 third display panel units 2E surrounding the periphery of the third display panel unit 2E may be added.

The present invention is not necessarily limited to that of the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above embodiment, the case where the present invention is applied to the above-mentioned organic EL display is illustrated, but the light emitting element is not necessarily limited to the one using an organic EL element, for example, a micro LED or the like. An LED element or a light emitting element such as a quantum dot may be used. The present invention can also be applied to liquid crystal displays and the like.

1A, 1B, 1C, 1D ... Multi-display 2 ... Display panel unit 2A ... First display panel unit 2B ... Second display panel unit 2C ... First display panel unit 2D ... Second display panel unit 2E ... Second Display panel unit of 3 ... Pixel circuit 4 ... Pixel circuit board 5 ... Scan line 6 ... Signal line 7 ... Power supply line 8 ... Organic EL element 9 ... Condenser 10 ... Selective TFT element 11 ... Drive TFT element 12 ... Board 13 ... pixel electrode 14 ... organic functional layer 15 ... common electrode 16 ... interlayer insulating layer 17 ... bank layer 18 ... protective layer 19 ... GND wire 20 ... gate insulating layer 31 ... first wiring 32 ... contact plug 32A ... first contact Plug 32B ... Second contact plug 32C ... Third contact plug 32D ... Fourth contact plug 33 ... Second wiring 33A ... First backside wiring 33B ... Second backside wiring 33C ... Third backside wiring 33D ... Fourth backside wiring 34 ... Connection part 34A ... First connection part 34B ... Second connection part 35 ... Flexible printed wiring board (FPC) 35A ... First FPC 35B ... Second FPC 36 ... Scanning line drive Circuit (gate driver) 37 ... Signal line drive circuit (data driver) 38 ... Interlayer insulation layer 50 ... Support substrate 51 ... First adhesive layer 52 ... Antireflection layer (circular polarizing plate) 53 ... Second adhesive layer C ... Retention capacity P ... Pixel Pu ... Pixel unit E ... Display area S ... Display screen W1 ... First constant area W2 ... First transient area W3 ... Second constant area H1 ... Third constant area H2 ... Second Transient region H3 ... 4th constant region W4 ... 1st constant region W5 ... 2nd constant region W6 ... 1st transient region W7 ... 3rd constant region H4 ... 4th constant region H5 ... 5th steady region Region H6 ... Second transient region H7 ... Sixth stationary region

Claims (4)

A plurality of pixels corresponding to at least the three primary colors of red, green, and blue are regarded as one pixel unit, and the pixel units are provided with a plurality of display panel units including a display area periodically arranged side by side in the plane.
A multi-display in which the display areas of the plurality of display panel units constitute one display screen by abutting adjacent objects of the plurality of display panel units against each other.
Of the plurality of display panel units, at least one first display panel unit located in the center and two second display panel units located on both sides of the first display panel unit are described above. It is provided side by side in one direction within the plane of the display screen.
When the width of the pixel unit in the one direction is a and the width of the margins provided on both sides of the pixel unit in the one direction is b.
The first display panel unit is a boundary between a first stationary region in which the distance between the pixel units arranged in one direction is a and the second display panel unit from both sides of the first stationary region. Includes a first transient region in which the spacing between the pixel units aligned in one direction changes continuously from a to a + 2b.
The second display panel unit is a multi-display characterized by including a second stationary region in which the distance between the pixel units arranged in one direction is a + 2b. Of the plurality of display panel units, at least one centrally located first display panel unit and eight second display panel units surrounding the first display panel unit are the displays. It is provided side by side in the one direction and the other direction that intersect in the plane of the screen.
When the width of the pixel unit in the other direction is a'and the width of the margins provided on both sides of the pixel unit in the other direction is b'.
The first display panel unit includes a third stationary region in which the distance between the pixel units arranged in the other direction is a', and the second display panel unit from both sides of the third stationary region. Includes a second transient region in which the spacing of the pixel units lined up in the other direction towards the boundary changes continuously from a'to a'+ 2b'.
The multi-display according to claim 1, wherein the second display panel unit includes a fourth stationary region in which the distance between the pixel units arranged in the other direction is a'+ 2b'. A plurality of pixels corresponding to at least the three primary colors of red, green, and blue are regarded as one pixel unit, and the pixel units are provided with a plurality of display panel units including a display area periodically arranged side by side in the plane.
A multi-display in which the display areas of the plurality of display panel units constitute one display screen by abutting adjacent objects of the plurality of display panel units against each other.
Of the plurality of display panel units, at least one first display panel unit located in the center, two second display panel units located on both sides of the first display panel unit, and the first display panel unit. The display panel unit 1 and the two third display panel units located on both sides of the second display panel unit are provided side by side in one direction in the plane of the display screen.
When the width of the pixel unit in the one direction is a and the width of the margins provided on both sides of the pixel unit in the one direction is b.
The first display panel unit includes a first stationary region in which the distance between the pixel units arranged in the one direction is a.
The second display panel unit is a boundary between a second stationary region in which the distance between the pixel units arranged in one direction is a and the second display panel unit from both sides of the second stationary region. Includes a first transient region in which the spacing between the pixel units aligned in one direction changes continuously from a to a + 2b.
The third display panel unit is a multi-display characterized by including a third stationary region in which the distance between the pixel units arranged in one direction is a + 2b. Of the plurality of display panel units, at least the first display panel unit located at the center, eight second display panel units surrounding the first display panel unit, and the second display. The 16 third display panel units surrounding the panel unit are provided side by side in one direction and the other direction intersecting in the plane of the display screen.
When the width of the pixel unit in the other direction is a'and the width of the margins provided on both sides of the pixel unit in the other direction is b'.
The first display panel unit includes a fourth stationary region in which the distance between the pixel units arranged in the other direction is a'.
The second display panel unit includes a fifth stationary region in which the distance between the pixel units arranged in the other direction is a'and the second display panel unit from both sides of the fifth stationary region. Includes a second transient region in which the spacing of the pixel units lined up in the other direction towards the boundary changes continuously from a'to a'+ 2b'.
The multi-display according to claim 3, wherein the third display panel unit includes a sixth stationary region in which the distance between the pixel units arranged in the other direction is a'+ 2b'.

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