CN110750952B - Semiconductor layout and layout method of semiconductor layout - Google Patents
Semiconductor layout and layout method of semiconductor layout Download PDFInfo
- Publication number
- CN110750952B CN110750952B CN201910980989.XA CN201910980989A CN110750952B CN 110750952 B CN110750952 B CN 110750952B CN 201910980989 A CN201910980989 A CN 201910980989A CN 110750952 B CN110750952 B CN 110750952B
- Authority
- CN
- China
- Prior art keywords
- filling
- pattern
- active layer
- layer
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000013461 design Methods 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Abstract
The application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor layout and a layout method of the semiconductor layout. The semiconductor layout includes: a predetermined region and a filled region; the predetermined region comprises an active layer and/or a gate layer; the filling area comprises at least one filling pattern, the filling pattern comprises a filling active layer and a filling grid layer, and the pattern of the filling pattern is generated according to the pattern density of the active layer and the grid layer of the preset area. The layout method of the semiconductor layout comprises the following steps: acquiring pattern densities of an active layer and a gate layer of a predetermined area; generating a filling pattern according to the pattern density of the active layer and the gate layer of the preset area; and filling the filling pattern in the filling area in the preset area to generate the semiconductor layout. The method and the device avoid the problem of coordination matching of the relation between the active layer and the gate layer in the process of filling the patterns by integrally filling the filling patterns in the filling areas.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor layout and a layout method of the semiconductor layout.
Background
With the continuous development of integrated circuit manufacturing technology, the integration level of semiconductor devices is also continuously improved. In the manufacturing process of a semiconductor, chemical mechanical polishing (Chemical Mechanical Polishing, CMP) is a process for realizing surface planarization of a semiconductor device, and in order to meet the requirements of the CMP process, it is generally required to insert a filling pattern in a blank region (referred to as a "filling region" in this application) of a semiconductor layout.
The related art generally adopts a scheme of optimally inserting a single level of filling pattern, for example, when an active layer and a gate layer are inserted in a semiconductor layout, only the active layer pattern or the gate layer pattern is inserted in a single insertion, and only whether the filling density of the inserted active layer or gate layer meets the requirement of the respective filling density is considered, but the relationship between the layers is not considered and is difficult to coordinate, so that a filling structure of a filling area as shown in fig. 6 is formed, that is, the filling area of the semiconductor layout comprises the filling active layer 310 and the filling gate layer 320, the filling active layer 310 and the filling gate layer 320 belong to different pattern layers in the semiconductor layout, and a overlapped layer 330 is formed between the filling active layer 310 and the filling active layer 320.
However, when the above scheme is adopted to process the pattern insertion in a plurality of layers, the relationship between the filled patterns is difficult to coordinate and match, and once the patterns are overlapped with each other, parasitic effects such as parasitic transistors, parasitic capacitance and resistance are easy to generate, so that other digital or analog devices in the circuit are affected.
Disclosure of Invention
The application provides a semiconductor layout and a layout method of the semiconductor layout, wherein the problem of coordination and matching of the relation between an active layer and a gate layer in the process of filling the pattern in the related art can be solved by calculating the pattern density of the filled active layer and the pattern density of the gate layer and filling the filled active layer and the filled gate layer into the filling area as a whole.
As a first aspect of the present invention, there is provided a semiconductor layout comprising:
a predetermined region and a filled region;
the predetermined region comprises an active layer and/or a gate layer;
the filling area comprises at least one filling pattern, the filling pattern comprises a filling active layer and a filling grid layer which are spaced, and the pattern of the filling pattern is generated according to the pattern density of the active layer and the grid layer of the preset area.
Further, the filling patterns are multiple, and two adjacent filling patterns are spaced.
Further, the pattern of the filling pattern is obtained by looking up a table according to the pattern densities of the filling active layer and the filling grid layer;
the pattern density of the filling active layer and the filling grid layer is calculated based on the layout design rule according to the pattern density of the active layer and the grid layer of the preset area, the area of the preset area and the area of the filling area;
wherein the pattern of the filling pattern includes shapes of the filling active layer and the filling gate layer, and/or a space between the filling active layer and the filling gate layer.
Further, the pattern density of the filling active layer and the filling gate layer is calculated by the following formula:
A x ＝(S 1 *ΔA)/S 2
P x ＝(S 1 *ΔP)/S 2
wherein A is X For the density of the filled active layer,P X s is the density of the filling grid layer 1 For the area of the predetermined area S 2 And delta A is the difference between the pattern density of the active layer in the preset area and the pattern density of the active layer specified in the layout design rule, and delta P is the difference between the pattern density of the gate layer in the preset area and the pattern density of the gate layer specified in the layout design rule.
As a second aspect of the present invention, there is provided a layout method of a semiconductor layout, comprising:
acquiring pattern densities of an active layer and a gate layer of a predetermined area;
generating a filling pattern according to pattern densities of the active layer and the gate layer of the preset area, wherein the filling pattern comprises a filling active layer and a filling gate layer which are spaced;
and filling the filling pattern in the filling area in the preset area to generate the semiconductor layout.
Further, the filling patterns are multiple, and two adjacent filling patterns are spaced. .
Further, the generating a filling pattern according to the pattern density of the active layer and the gate layer of the predetermined area includes:
calculating the pattern density of the filling active layer and the filling gate layer based on the layout design rule according to the pattern density of the active layer and the gate layer of the preset area, the area of the preset area and the area of the filling area;
the pattern of the filling pattern is obtained by looking up a table according to the pattern density of the filling active layer and the filling grid layer, wherein the pattern of the filling pattern comprises the shapes of the filling active layer and the filling grid layer and/or the interval between the filling active layer and the filling grid layer;
and generating the filling pattern according to the pattern of the filling pattern.
Further, according to the pattern density of the active layer and the gate layer of the predetermined area, the area of the predetermined area and the area of the filling area, the pattern densities of the filling active layer and the filling gate layer are calculated according to the following formula based on the layout design rule:
A x ＝(S 1 *ΔA)/S 2
P x ＝(S 1 *ΔP)/S 2
wherein A is X For the density of the filling active layer, P X S is the density of the filling grid layer 1 For the area of the predetermined area S 2 And delta A is the difference between the pattern density of the active layer in the preset area and the pattern density of the active layer specified in the layout design rule, and delta P is the difference between the pattern density of the gate layer in the preset area and the pattern density of the gate layer specified in the layout design rule.
The technical scheme of the application at least comprises the following advantages:
firstly, the pattern density of the filling active layer and the pattern density of the gate layer are calculated, the filling active layer and the filling gate layer are used as a whole filling pattern to be filled in the filling area, the pattern density of the active layer, the pattern density of the gate layer and the relationship between the active layer and the gate layer in a preset area are matched through different patterns of the filling pattern, and the problem of coordination matching of the relationship between the active layer and the gate layer in the pattern filling process in the prior art can be avoided.
Secondly, the problem that the layers in the two adjacent filling patterns are overlapped with each other can be avoided by arranging the two adjacent filling patterns at intervals, so that parasitic effects of devices can be further avoided, and the semiconductor layout is more reliable.
Third, by spacing the filling active layer and the filling gate layer in one filling pattern, parasitic effects between the filling active layer and the filling gate layer can be avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor layout according to a first aspect of the present invention.
Fig. 2 is a schematic diagram of a filling area structure of a semiconductor layout according to a first aspect of the present invention.
Fig. 3 is a schematic structural diagram of a filling pattern of a semiconductor layout according to a first aspect of the present invention.
Fig. 4 is a flow chart of a semiconductor layout method according to a second aspect of the present invention.
Fig. 5 is a flow chart of a method for generating a filler figure according to a second aspect of the present invention.
Fig. 6 is a schematic diagram of a semiconductor layout filling area structure of the related art of the present invention.
100. Predetermined area, 200, fill area, 300, fill pattern, 310, fill active layer, 320, fill gate layer, 330, overlap layer, 400, blank area, 500, redundant area.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
As a first aspect of the present invention, as shown in fig. 1, there is provided a semiconductor layout including:
a predetermined region 100 and a filled region 200; the predetermined region 100 includes an active layer, and/or a gate layer; the filling region 200 includes at least one filling pattern 300, the filling pattern 300 includes a filling active layer 310 and a filling gate layer 320 spaced apart, and the pattern of the filling pattern 300 is generated according to the pattern densities of the active layer and the gate layer of the predetermined region 100.
It can be appreciated that the filling pattern 300 of the filling active layer 310 and the filling gate layer 320 as a whole is filled in the filling area 200, and the pattern density of the active layer, the pattern density of the gate layer and the relationship between the active layer and the gate layer in the predetermined area 100 are matched by different patterns of the filling pattern 300, so that the problem of the coordination matching of the relationship between the active layer and the gate layer in the process of filling the pattern 300 in the prior art can be avoided.
As shown in fig. 2 and 3, in order to avoid parasitic effects between the filling active layer 310 and the filling gate layer 320, the filling active layer 310 and the filling gate layer 320 are spaced apart.
It should be noted that if there are a plurality of filling patterns 300, two adjacent filling patterns 300 are spaced apart from each other. By arranging the adjacent two filling patterns 300 at intervals, the problem of mutual overlapping between the layers in the adjacent two filling patterns 300 can be avoided, and thus, the parasitic effect of the device can be further avoided.
The pattern of the filling pattern 300 is obtained by looking up a table according to the pattern densities of the filling active layer 310 and the filling gate layer 320; the pattern densities of the filling active layer 310 and the filling gate layer 320 are calculated based on the layout design rule according to the pattern densities of the active layer and the gate layer of the predetermined region 100, the area of the predetermined region 100, and the area of the filling region 200; wherein the pattern of the filling pattern 300 includes the shape of the filling active layer 310, the shape of the filling gate layer 320, and the interval between the filling active layer 310 and the filling gate layer 320.
It should be noted that, firstly, the table for querying the pattern of the filling pattern 300 is preset, and different pattern patterns can be matched according to the calculated pattern density of the filling active layer 310, the pattern density of the filling gate layer 320, and the relationship between the pattern densities of the filling active layer 310 and the filling gate layer 320. Secondly, the area of the filling area 200 is calculated based on the layout design rule according to the area of the predetermined area 100; the semiconductor layout comprises a preset area 100 with preset circuit modules and a blank area 400 without the preset circuit modules, wherein the blank area 400 comprises a filling area 200 allowing the filling of the pattern 300 and a redundant area 500 not allowing the filling of the pattern 300, and the redundant area 500 is used for avoiding parasitic effects among devices; different semiconductor layouts have different requirements for the redundant region 500, so the area of the filler region 200 also needs to be constrained by the area of the redundant region 500 to avoid parasitic effects between devices. Thirdly, for the pattern of the filling pattern 300, a space is formed between the filling active layer 310 and the filling gate layer 320 in the filling pattern 300, so that overlapping between the filling active layer 310 and the filling gate layer 320 can be avoided, and parasitic effect between the filling active layer 310 and the filling gate layer 320 can be avoided.
The pattern densities of the filling active layer 310 and the filling gate layer 320 are calculated according to the following formulas based on the layout design rule according to the pattern densities of the active layer and the gate layer of the predetermined region 100, the area of the predetermined region 100, and the area of the filling region 200:
A x ＝(S 1 *ΔA)/S 2
P x ＝(S 1 *ΔP)/S 2
wherein A is X For the density, P, of the filled active layer 310 X S is the density of the filling gate layer 320 1 S is the area of the predetermined area 100 2 For the area of the filling area 200, Δa is a difference between the pattern density of the active layer of the predetermined area 100 and the pattern density of the active layer specified in the layout design rule, and Δp is a difference between the pattern density of the gate layer of the predetermined area 100 and the pattern density of the gate layer specified in the layout design rule.
As a second aspect of the present invention, as shown in fig. 4, there is provided a layout method of a semiconductor layout, the layout method of the semiconductor layout including:
s1: acquiring pattern densities of an active layer and a gate layer of the predetermined region 100;
s2: generating a filling pattern 300 according to the pattern density of the active layer and the gate layer of the predetermined region 100, wherein the filling pattern 300 comprises a filling active layer 310 and a filling gate layer 320;
s3: filling the filling pattern 300 in the filling area 200 in the predetermined area 100 to generate the semiconductor layout.
It can be appreciated that the filling pattern 300 of the filling active layer 310 and the filling gate layer 320 as a whole is filled in the filling area 200, and the pattern density of the active layer, the pattern density of the gate layer and the relationship between the active layer and the gate layer in the predetermined area 100 are matched by different patterns of the filling pattern 300, so that the problem of the coordination matching of the relationship between the active layer and the gate layer in the process of filling the pattern 300 in the prior art can be avoided.
In order to avoid parasitic effects between the filling active layer 310 and the filling gate layer 320, the filling active layer 310 and the filling gate layer 320 are spaced apart.
It should be noted that if there are a plurality of filling patterns 300, two adjacent filling patterns 300 are spaced apart from each other. By arranging the adjacent two filling patterns 300 at intervals, the problem of mutual overlapping between the layers in the adjacent two filling patterns 300 can be avoided, and thus, the parasitic effect of the device can be further avoided.
As shown in fig. 5, the step S2: generating a filling pattern 300 according to the pattern density of the active layer and the gate layer of the predetermined region 100, including:
s210: calculating the pattern density of the filling active layer 310 and the filling gate layer 320 based on the layout design rule according to the pattern density of the active layer and the gate layer of the predetermined area 100, the area of the predetermined area 100 and the area of the filling area 200;
s220: obtaining a pattern of the filling pattern 300 according to pattern density lookup tables of the filling active layer 310 and the filling gate layer 320, wherein the pattern of the filling pattern 300 comprises shapes of the filling active layer 310 and the filling gate layer 320 and/or a space between the filling active layer 310 and the filling gate layer 320;
230: and generating the filling pattern 300 according to the pattern of the filling pattern 300.
It should be noted that the table for querying the pattern of the filling pattern 300 in S220 is preset, and different pattern patterns can be matched according to the calculated pattern density of the filling active layer 310, the pattern density of the filling gate layer 320, and the relationship between the pattern densities of the filling active layer 310 and the filling gate layer 320.
S210: the pattern densities of the filling active layer 310 and the filling gate layer 320 are calculated according to the following formulas based on the layout design rule according to the pattern densities of the active layer and the gate layer of the predetermined region 100, the area of the predetermined region 100, and the area of the filling region 200:
A x ＝(S 1 *ΔA)/S 2
P x ＝(S 1 *ΔP)/S 2
wherein A is X For the density, P, of the filled active layer 310 X S is the density of the filling gate layer 320 1 S is the area of the predetermined area 100 2 For the area of the filling area 200, Δa is a difference between the pattern density of the active layer of the predetermined area 100 and the pattern density of the active layer specified in the layout design rule, and Δp is a difference between the pattern density of the gate layer of the predetermined area 100 and the pattern density of the gate layer specified in the layout design rule.
The layout method of the semiconductor layout further comprises the following steps:
s240: according to the difference DeltaA between the pattern density of the active layer of the predetermined area 100 and the pattern density of the active layer specified in the layout design rule, and the area S of the filled active layer 310 in the filled pattern 300 generated by S230 3 The number of fills of the filling pattern 300 in the filling area 200 is calculated. Or according to the difference DeltaP between the pattern density of the gate layer of the predetermined region 100 and the pattern density of the gate layer specified in the layout design rule, and the area S of the filling active layer 310 in the filling pattern 300 generated by S230 4 The number of fills of the filling pattern 300 in the filling area 200 is calculated.
As can be seen from the technical solutions provided in the first and second aspects of the present invention, by calculating the pattern density of the filling active layer 310 and the pattern density of the gate layer, and filling the filling active layer 310 and the filling gate layer 320 into the filling area 200 according to the respective pattern densities as a whole filling pattern 300, the relationships between the active layer and the gate layer in the semiconductor layout can be matched in a coordinated manner, so that parasitic effects between the filling active layer 310 and the filling gate layer 320 are avoided, and the designed semiconductor layout is more reliable.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (8)
1. A semiconductor layout, comprising:
a predetermined region and a filled region;
the predetermined region comprises an active layer and/or a gate layer;
the filling area comprises at least one filling pattern, the filling pattern comprises a filling active layer and a filling grid layer which are spaced, and the pattern of the filling pattern is generated according to the pattern density of the active layer and the grid layer of the preset area;
the filling active layer and the filling gate layer are filled in the filling area as a whole filling pattern.
2. The semiconductor layout according to claim 1, wherein the filling patterns are plural, and two adjacent filling patterns are spaced apart.
3. The semiconductor layout according to claim 2, wherein the pattern of the filling pattern is obtained by looking up a table according to pattern densities of the filling active layer and the filling gate layer;
the pattern density of the filling active layer and the filling grid layer is calculated based on the layout design rule according to the pattern density of the active layer and the grid layer of the preset area, the area of the preset area and the area of the filling area;
wherein the pattern of the filling pattern includes shapes of the filling active layer and the filling gate layer, and/or a space between the filling active layer and the filling gate layer.
4. A semiconductor layout according to claim 3, wherein the pattern density of the filled active layer and the filled gate layer is calculated by the following formula:
A x ＝(S 1 *ΔA)/S 2
P x ＝(S 1 *ΔP)/S 2
wherein A is X For the density of the filling active layer, P X S is the density of the filling grid layer 1 For the area of the predetermined area S 2 And delta A is the difference between the pattern density of the active layer in the preset area and the pattern density of the active layer specified in the layout design rule, and delta P is the difference between the pattern density of the gate layer in the preset area and the pattern density of the gate layer specified in the layout design rule.
5. A layout method of a semiconductor layout, comprising:
acquiring pattern densities of an active layer and a gate layer of a predetermined area;
generating a filling pattern according to pattern densities of the active layer and the gate layer of the preset area, wherein the filling pattern comprises a filling active layer and a filling gate layer which are spaced;
and filling the filling pattern in the filling area in the preset area to generate the semiconductor layout.
6. The method of claim 5, wherein the filling patterns are plural, and two adjacent filling patterns are spaced apart.
7. The method of claim 6, wherein generating the fill pattern from the pattern density of the active layer and the gate layer of the predetermined region comprises:
calculating the pattern density of the filling active layer and the filling gate layer based on the layout design rule according to the pattern density of the active layer and the gate layer of the preset area, the area of the preset area and the area of the filling area;
the pattern of the filling pattern is obtained by looking up a table according to the pattern density of the filling active layer and the filling grid layer, wherein the pattern of the filling pattern comprises the shapes of the filling active layer and the filling grid layer and/or the interval between the filling active layer and the filling grid layer;
and generating the filling pattern according to the pattern of the filling pattern.
8. The method according to claim 7, wherein the pattern densities of the filled active layer and the filled gate layer are calculated based on the layout design rule according to the following formula based on the pattern densities of the active layer and the gate layer of the predetermined region, the area of the predetermined region, and the area of the filled region:
A x ＝(S 1 *ΔA)/S 2
P x ＝(S 1 *ΔP)/S 2
wherein A is X For the density of the filling active layer, P X S is the density of the filling grid layer 1 For the area of the predetermined area S 2 And delta A is the difference between the pattern density of the active layer in the preset area and the pattern density of the active layer specified in the layout design rule, and delta P is the difference between the pattern density of the gate layer in the preset area and the pattern density of the gate layer specified in the layout design rule.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910980989.XA CN110750952B (en) | 2019-10-16 | 2019-10-16 | Semiconductor layout and layout method of semiconductor layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910980989.XA CN110750952B (en) | 2019-10-16 | 2019-10-16 | Semiconductor layout and layout method of semiconductor layout |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110750952A CN110750952A (en) | 2020-02-04 |
| CN110750952B true CN110750952B (en) | 2024-02-02 |
Family
ID=69278372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910980989.XA Active CN110750952B (en) | 2019-10-16 | 2019-10-16 | Semiconductor layout and layout method of semiconductor layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110750952B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113312873B (en) * | 2021-05-24 | 2023-03-14 | 海光信息技术股份有限公司 | Circuit layout design method and device, mask plate and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1918721A (en) * | 2004-01-14 | 2007-02-21 | 波利Ic有限及两合公司 | Organic transistor comprising a self-adjusting gate electrode, and method for the production thereof |
| CN102468134A (en) * | 2010-11-16 | 2012-05-23 | 上海华虹Nec电子有限公司 | Method for adjusting chip graph density using redundancy graph insertion, |
| CN102542119A (en) * | 2012-01-12 | 2012-07-04 | 中国科学院微电子研究所 | Redundant metal filling method and system utilizing same |
-
2019
- 2019-10-16 CN CN201910980989.XA patent/CN110750952B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1918721A (en) * | 2004-01-14 | 2007-02-21 | 波利Ic有限及两合公司 | Organic transistor comprising a self-adjusting gate electrode, and method for the production thereof |
| CN102468134A (en) * | 2010-11-16 | 2012-05-23 | 上海华虹Nec电子有限公司 | Method for adjusting chip graph density using redundancy graph insertion, |
| CN102542119A (en) * | 2012-01-12 | 2012-07-04 | 中国科学院微电子研究所 | Redundant metal filling method and system utilizing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110750952A (en) | 2020-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106711120B (en) | Semiconductor device with buried power rail and method of manufacturing the same | |
| CN102272904B (en) | Method of forming trench capacitors | |
| CN103367244B (en) | Back side metal-oxide-metal/metal-insulator-metal element | |
| CN110750952B (en) | Semiconductor layout and layout method of semiconductor layout | |
| US9686866B2 (en) | Package structure and manufacturing method thereof | |
| CN100459112C (en) | Electronic component having an integrated passive electronic component and associated production method | |
| CN109002566B (en) | Filling method and system for redundant metal | |
| KR101671665B1 (en) | Conductive line patterning | |
| JP5547934B2 (en) | Semiconductor device, semiconductor device manufacturing method, and semiconductor device layout method | |
| CN106304634A (en) | Board structure of circuit and manufacture method thereof | |
| CN113625527B (en) | Method for setting alignment mark of warpage wafer | |
| US11309382B2 (en) | Electronic product comprising a component having triskelion-pillars, and corresponding fabrication method | |
| CN102197456A (en) | Improved metal-on-metal capacitor with diagonal feedline | |
| US10499512B2 (en) | Multi-layer circuit board and manufacturing method thereof | |
| US20070018274A1 (en) | Semiconductor circuit arrangement and method | |
| JP4997646B2 (en) | Integrated circuit having embedded resistor that can be electrically coupled to decoupling capacitor and method of manufacturing the same | |
| CN111653627B (en) | Capacitor structure with vertical diffusion plate | |
| CN102456080A (en) | Dummy fill insertion method for integrated circuit layout | |
| JP5431037B2 (en) | Multilayer wiring, multilayer wiring dummy wiring arrangement method, semiconductor device and manufacturing method thereof | |
| US7916449B2 (en) | Creation of capacitors equipped with means to reduce the stresses in the metal material of their lower structures | |
| US11355579B2 (en) | Device integrated with three-dimensional MIM capacitor and method for making the same | |
| CN103426728A (en) | Capacitor structure and manufacturing method thereof | |
| CN104081520A (en) | Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias | |
| TWI248192B (en) | Semiconductor integrated circuit and its manufacturing method | |
| KR20100116389A (en) | Method for forming a via hole of the semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |