CN110739391B - Surface acoustic wave filter device and method of manufacturing the same - Google Patents
Surface acoustic wave filter device and method of manufacturing the same Download PDFInfo
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- CN110739391B CN110739391B CN201911019686.8A CN201911019686A CN110739391B CN 110739391 B CN110739391 B CN 110739391B CN 201911019686 A CN201911019686 A CN 201911019686A CN 110739391 B CN110739391 B CN 110739391B
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
- H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
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- H—ELECTRICITY
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Abstract
The invention provides a surface acoustic wave filter device and a manufacturing method thereof, wherein a small-sized piezoelectric wafer is firstly divided into a plurality of piezoelectric crystal grains and is temporarily bonded onto a large-sized carrier wafer, so that the manufacturing process of the surface acoustic wave filter device can be completed on a large-sized wafer processing machine table corresponding to the size of the carrier wafer, the manufacturing process of the surface acoustic wave filter device is compatible with the processing process of the large-sized wafer, and therefore, the problem that equipment is purchased again when the large-sized wafer replaces the surface acoustic wave filter device in a factory is avoided, and the cost is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a surface acoustic wave filter device and a manufacturing method thereof.
Background
A Surface Acoustic Wave (SAW) filter is one of the mainstream piezoelectric Acoustic Wave filters at present, and can meet the requirements of small-size filter devices used in communication terminals, and the process for manufacturing the mainstream SAW filter at present is a 4-inch (inch) wafer process, because there is no mature growth technology of 8-inch piezoelectric materials at present, while the existing 6-inch piezoelectric material growth technology has the problem of poor in-chip processing uniformity.
However, to further reduce costs, MEMS (Micro-Electro-Mechanical systems) wafer foundry is gradually moving toward 8-inch wafers. Obviously, there is always a gap between the SAW filter device and the MEMS wafer foundry, and the SAW filter is not compatible with the MEMS wafer foundry, so if the MEMS wafer foundry intends to foundry the SAW filter device, the related equipment needs to be purchased again, which is greatly disadvantageous to the depreciation of the equipment and the reduction of the cost.
Disclosure of Invention
The invention aims to provide a surface acoustic wave filter device and a manufacturing method thereof, which can make the manufacturing process of the surface acoustic wave filter device compatible with the processing process of a large-size wafer and reduce the cost.
In order to achieve the above object, the present invention provides a method for manufacturing a surface acoustic wave filter device, comprising the steps of:
providing a piezoelectric wafer and a carrier wafer, wherein the size of the piezoelectric wafer is smaller than that of the carrier wafer;
dividing the piezoelectric wafer into a plurality of piezoelectric crystal grains, temporarily bonding each piezoelectric crystal grain to the carrier wafer, and taking a gap between every two adjacent piezoelectric crystal grains as a cutting path;
forming interdigital electrodes and first pads on top surfaces of the respective piezoelectric dies;
providing a packaging substrate which is not smaller than the carrier wafer in size and is provided with a plurality of second bonding pads, assembling the carrier wafer with the piezoelectric crystal grains on the packaging substrate, and aligning each first bonding pad and the corresponding second bonding pad and carrying out bump bonding;
and peeling the carrier wafer, and cutting the packaging substrate along each cutting channel to obtain a plurality of surface acoustic wave filter devices.
Optionally, each piezoelectric die is temporarily bonded to the carrier wafer by at least one of applying a bonding glue, attaching a bonding film, and depositing a laser release layer on the carrier wafer.
Optionally, the carrier wafer is peeled according to the temporary bonding mode, and the peeling mode comprises thermal sliding peeling, mechanical peeling and laser peeling.
Optionally, after temporarily bonding each piezoelectric die to the carrier wafer and before forming the interdigital electrodes and the first pads on the top surface of each piezoelectric die, further forming an insulating layer on the carrier wafer, wherein the insulating layer fills the dicing channels and exposes the top surface of each piezoelectric die; the interdigital electrode and the first bonding pad are exposed out of the top surface of the insulating layer in the cutting channel.
Optionally, before and/or after forming the interdigital electrodes and the first pads on the top surfaces of the respective piezoelectric dies, a temperature compensation layer is further formed on the top surfaces of the piezoelectric dies, and the temperature compensation layer is at least filled in the gaps of the interdigital electrodes and exposes the top surfaces of the respective first pads.
Optionally, the material of the temperature compensation layer comprises undoped or doped silicon oxide.
Optionally, the step of forming the temperature compensation layer, the interdigital electrode, and the first pad includes:
covering a first temperature compensation layer on the surface of each of the piezoelectric crystal grains and the insulating layer before forming the interdigital electrodes and the first pads on the top surface of each of the piezoelectric crystal grains;
patterning the first temperature compensation layer to form interdigital grooves and pad grooves on the top surface of each of the piezoelectric dies;
depositing a metal layer to fill the interdigital grooves and the pad grooves, and flattening the metal layer to the top surface of the first temperature compensation layer to form the interdigital electrodes and the first pad;
covering a second temperature compensation layer on the top surfaces of the first temperature compensation layer, the interdigital electrode and the first bonding pad, patterning the second temperature compensation layer to expose the top surface of the first bonding pad, wherein the first temperature compensation layer after patterning and the second temperature compensation layer after patterning form the temperature compensation layer.
Optionally, the material of the piezoelectric wafer includes at least one of lithium niobate, lithium tantalate, aluminum nitride, barium titanate, lead zirconate titanate, zinc oxide, and piezoelectric ceramic.
Optionally, before the carrier wafer with the piezoelectric die is assembled on the package substrate, the first pad or the second pad is ball-bonded, so that bump bonding is performed after the first pad and the second pad are aligned.
Based on the same inventive concept, the invention also provides a surface acoustic wave filter device, which is manufactured by the manufacturing method of the surface acoustic wave filter device; the surface acoustic wave filter device comprises a packaging substrate and a piezoelectric crystal grain which are packaged together, wherein the piezoelectric crystal grain is positioned above the packaging substrate; the packaging substrate is provided with a second bonding pad, one surface of the piezoelectric crystal grain, facing the packaging substrate, is provided with an interdigital electrode and a first bonding pad, the first bonding pad and the second bonding pad are aligned and bonded together, and a space for sound wave resonance is provided between the piezoelectric crystal grain and the packaging substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the method comprises the steps of firstly dividing a small-sized piezoelectric wafer into a plurality of piezoelectric crystal grains, and temporarily bonding the piezoelectric crystal grains to a large-sized carrier wafer, so that the manufacturing process of the surface acoustic wave filter device can be completed on a large-sized wafer processing machine table corresponding to the size of the carrier wafer, namely the manufacturing process of the surface acoustic wave filter device is compatible with the processing process of the large-sized wafer, and therefore the problem that equipment is purchased again when the large-sized wafer replaces the surface acoustic wave filter device in a factory is avoided, and cost is reduced.
2. And assembling the carrier wafer with the piezoelectric crystal grains on the packaging substrate, aligning each first bonding pad with the corresponding second bonding pad on the packaging substrate and bonding the first bonding pad and the second bonding pad through bumps, so that a wafer-level packaging process with high integration level can be realized, and the packaging cost is further reduced.
3. The method is not only suitable for manufacturing common surface acoustic wave filter devices, but also suitable for manufacturing temperature compensation type surface acoustic wave filter (TC-SAW) devices.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a surface acoustic wave filter device according to an embodiment of the present invention;
fig. 2 is a schematic top view of a piezoelectric wafer provided in step S1 of the method for manufacturing a surface acoustic wave filter device according to an embodiment of the present invention;
fig. 3 is a schematic top view of a piezoelectric crystal grain temporarily bonded to a carrier wafer in step S2 of the method for manufacturing a surface acoustic wave filter device according to the embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a surface acoustic wave filter device according to an embodiment of the present invention after a piezoelectric crystal grain is temporarily bonded to a carrier wafer in step S2;
fig. 5A to 5D are schematic cross-sectional views illustrating a method of manufacturing a surface acoustic wave filter device according to an embodiment of the present invention;
fig. 6A to 6E are schematic cross-sectional views illustrating a method of manufacturing a surface acoustic wave filter device according to another embodiment of the present invention.
Detailed Description
To make the objects, advantages and features of the present invention clearer, the technical solutions proposed by the present invention will be further described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention. Further, the term "and/or" herein means either or both.
Referring to fig. 1, an embodiment of the invention provides a method for manufacturing a surface acoustic wave filter device, including the following steps:
s1, providing a piezoelectric wafer and a carrier wafer, wherein the size of the piezoelectric wafer is smaller than that of the carrier wafer;
s2, dividing the piezoelectric wafer into a plurality of piezoelectric crystal grains, temporarily bonding each piezoelectric crystal grain to the carrier wafer, and taking the gap between the adjacent piezoelectric crystal grains as a cutting path;
s3, forming an insulating layer, wherein the insulating layer fills the cutting path and exposes the top surface of each piezoelectric crystal grain;
s4, forming an interdigital electrode and a first pad on the top surface of each piezoelectric crystal grain, wherein the interdigital electrode and the first pad are exposed out of the surface of the insulating layer in the cutting channel;
s5, providing a packaging substrate which is not smaller than the carrier wafer in size and is provided with a plurality of second bonding pads, assembling the carrier wafer with the piezoelectric crystal grains on the packaging substrate, and aligning and electrically connecting each first bonding pad with the corresponding second bonding pad;
and S6, peeling the carrier wafer, and cutting the packaging substrate and the insulating layer along each cutting path to obtain a plurality of surface acoustic wave filter devices with corresponding piezoelectric crystal grains and packaging substrates.
Referring to fig. 2 to 4, in step S1, a 4 inch or 6 inch piezoelectric wafer 10' and an 8 inch or 12 inch carrier wafer 20 may be provided, i.e., the size of the piezoelectric wafer 10 is smaller than that of the silicon wafer 20. Wherein, the material of the piezoelectric wafer 10 'includes at least one of lithium niobate, lithium tantalate, aluminum nitride, barium titanate, lead zirconate titanate, and zinc oxide, and the piezoelectric wafer 10' is also often referred to as a piezoelectric chip. The material of the carrier wafer 20 includes at least one of a semiconductor (e.g., silicon, germanium, gallium arsenide, silicon on insulator, etc.), glass, quartz, silicon carbide, alumina, epoxy, polyurethane. The carrier wafer 20 is a large-sized wafer relative to the piezoelectric wafer 10, the size of the carrier wafer 20 meets the wafer processing size requirement of a large-sized wafer processing machine, and the size of the piezoelectric wafer 10' is smaller than the carrier wafer 20 and does not meet the wafer processing size requirement of the large-sized wafer processing machine.
Referring to fig. 2 to 4, in step S2, first, a wafer dicing process may be used to divide the piezoelectric wafer 10' into a plurality of piezoelectric crystal grains 10, where the size and shape of the piezoelectric crystal grains 10 are substantially the same, and the dividing process specifically includes: firstly, a blue film (not shown) is pasted on the bottom surface of the piezoelectric wafer 10, then the piezoelectric wafer 10 is cut from the top surface of the piezoelectric wafer 10 to the top surface of the blue film, and then the blue film is removed to obtain a plurality of piezoelectric crystal grains 10a, wherein the blue film can better fix the piezoelectric wafer 10 and fix the cut piezoelectric crystal grains 10a, so that the cut piezoelectric crystal grains 10a are prevented from flying out of a machine, and the protection and collection of the piezoelectric crystal grains 10a are facilitated. Then, each piezoelectric die 10 may be temporarily bonded to the carrier wafer 20 by at least one of coating bonding glue, attaching a bonding film, and depositing a laser release layer (not shown) on the carrier wafer 20 on a wafer bonding machine corresponding to the carrier wafer 20. For example, each piezoelectric die 10 is temporarily bonded to the carrier wafer 20 through a temporary bonding layer (i.e., an adhesive bonding film or a bonding glue layer) 30, so as to realize a chip to wafer (chip to wafer) packaging manner. The individual piezoelectric crystal grains 10 may be arranged in an array at equal intervals, and the gaps between adjacent piezoelectric crystal grains 10 serve as cutting streets 10a, and the cutting streets 10a are used for subsequently realizing dicing between the piezoelectric crystal grains (i.e., chip to chip). The wafer bonding structure formed after each piezoelectric die 10 is temporarily bonded to the carrier wafer 20 may enter a corresponding large-sized wafer processing machine for performing corresponding film deposition, photolithography, etching, and the like, as in the case of a large-sized (e.g., 8 inch) wafer.
Referring to fig. 5A, in step S3, a corresponding film forming process such as vapor deposition or spin coating is performed on a large-sized wafer processing machine (e.g., a vapor deposition apparatus, an oxidation furnace, or a film coating machine) corresponding to the carrier wafer 20 to cover the insulating layer 11 on the piezoelectric crystal grains 10 and the carrier wafer 20, wherein the insulating layer 11 at least fills the scribe lines 10 a. Then, the top surface of the insulating layer 11 is ground by a Chemical Mechanical Polishing (CMP) process to expose the top surface of each piezoelectric crystal grain 10a, and in other embodiments of the present invention, the insulating layer 11 may be etched back by an etch-back process to expose the top surface of each piezoelectric crystal grain 10. The material of the insulating layer 11 includes at least one of a plastic package material, silicon oxide, silicon oxynitride, silicate glass (e.g., borosilicate glass BSG, phosphosilicate glass PSG, borophosphosilicate glass BPSG, undoped silicate glass USG, etc.), a low-K dielectric (dielectric constant K is less than 4), and polyimide. On one hand, the insulating layer 11 can enhance the firmness of the piezoelectric crystal grain 10 and prevent the piezoelectric crystal grain 10 from moving in the subsequent process when being fixed only by the temporary bonding layer 30, so that the reliability of the subsequent process is improved; on the other hand, the insulating layer 11 can also protect the side wall of the piezoelectric crystal grain 10, and prevent the piezoelectric crystal grain 10 from being damaged by the side wall of the piezoelectric crystal grain 10 in the subsequent process, which affects the yield and performance of the manufactured surface acoustic wave filter device. Of course, in other embodiments of the present invention, if the subsequent processes do not have the above-mentioned problems, the formation of the insulating layer 11 may be omitted.
Referring to fig. 5A, in step S4, a metal layer (not shown) may be covered on the insulating layer 11 and each piezoelectric crystal grain 10 by vacuum evaporation, sputtering deposition, or other processes on a large-sized wafer processing machine corresponding to the size of the carrier wafer 20, wherein the metal layer includes at least one of tungsten, silver, zirconium, molybdenum, platinum (i.e., platinum), ruthenium, iridium, titanium, tungsten, copper, chromium, hafnium, and aluminum. Then, the metal layer (not shown) is patterned by a process of photolithography in combination with dry etching to form the interdigital electrode 12b and the first pad 12a, and the interdigital electrode 12b and the first pad 12a each expose a top surface of the insulating layer 11 in the scribe line 10 a. Wherein the first pads 12a are used for subsequently performing bump bonding with the package substrate. The interdigital electrode 12b is an electrode having a periodic pattern in its face, such as a finger or comb. The interdigital electrodes 12b are usually present in pairs, whereby an input electrical signal excites a surface acoustic wave by the piezoelectric effect of one interdigital electrode 12b and propagates to the other interdigital electrode 12b, the surface acoustic wave is converted into an electrical signal at the other interdigital electrode 12b for output due to the inverse piezoelectric effect, and a desired band-pass filter frequency response curve can be obtained by controlling the period and shape of the interdigital electrode 12b and selecting the parameters of the piezoelectric medium. In other embodiments of the present invention, the interdigital electrodes 12b and the first pads 12a may also be formed by a Lift-off process, in which a substrate (i.e., the insulating layer 11 and the individual piezoelectric dies 10) is first coated with glue and then subjected to photolithography, and then a metal thin film is prepared, where the photoresist is present, the metal thin film is formed on the photoresist, and where the photoresist is absent, the metal thin film is directly formed on the substrate. When the photoresist on the substrate is removed by using a solvent, unnecessary metal is removed in the solvent along with the dissolution of the photoresist, and the metal portion directly formed on the substrate remains to form a pattern, that is, the interdigital electrode 12b and the first pad 12 a.
With continued reference to fig. 5A, in order to subsequently realize bump bonding between the side of the carrier wafer 20 having the first pads 12a and the interdigital electrodes 12b and the side of the package substrate 40, balls may be first planted on the first pads 12a to form solder balls 13. The solder balls 13 may be tin solder balls, lead solder balls, tin-lead solder balls, silver solder balls, tin-silver-copper solder balls, or copper pillars.
Referring to fig. 5B, in step S5, first, a package substrate 40 having a size not smaller than the carrier wafer 20 and a plurality of second pads 41 is provided, where the package substrate 40 may be a High Temperature co-fired Ceramic (HTCC) substrate having the same size as the carrier wafer 20, and the molding process of the HTCC substrate includes: according to the design requirement of a heating circuit, heating resistance slurry for protecting at least one high-melting-point metal such as tungsten, molybdenum, manganese and the like is printed on 92-96% of alumina casting ceramic green bodies, and is subjected to multilayer overlapping under the action of 4-8% of sintering aids, and is co-fired into a whole at a high temperature of 1500-1600 ℃. Next, the carrier wafer 20 with the piezoelectric crystal grains 10 may be assembled on the package substrate 40 on a large-sized wafer processing machine (i.e., a wafer bonding machine) corresponding to the size of the carrier wafer 20, and each of the first pads 12a and the corresponding second pad 41 are aligned and bump-bonded through the solder balls 13. Step S5 is substantially a wafer to wafer (wafer to wafer) packaging process, in which the carrier wafer 20 with the piezoelectric die 10 is assembled on the package substrate 40, and the first pads 12a and the corresponding second pads 41 on the package substrate 40 are aligned and bump-bonded, so as to realize a wafer level packaging process with high integration and further reduce the packaging cost.
It should be noted that, in other embodiments of the present invention, before the carrier wafer 20 with the piezoelectric die 10 is assembled on the package substrate 40, the balls may be planted on the second pads 41 instead of the first pads 12 a; alternatively, balls are planted on both the first pad 12a and the second pad 41 to realize bump bonding between the first pad 12a and the second pad 41.
In step S6, referring to fig. 5B and 5C, the carrier wafer 20 may be peeled off from each piezoelectric die 10 by selecting a suitable wafer peeling method according to the temporary bonding manner in step S2, the peeling manners including thermal slide peeling, mechanical peeling, and laser peeling, and in some peeling manners, the temporary bonding layer 30 between the carrier wafer 20 and each piezoelectric die 10 is still remained on the surface of the piezoelectric die 10 after the carrier wafer 20 is removed for subsequent cutting of the scribe lines between the piezoelectric dies 10, so as to protect the piezoelectric dies 10. Then, referring to fig. 5D, the package substrate 40 and the insulating layer 11 may be cut along the cutting lines 10a from the piezoelectric die 10 side to obtain a plurality of surface acoustic wave filter devices 50 having the corresponding interdigital electrodes 12b, the piezoelectric die 10 and the package substrate 40.
In the above method for manufacturing the surface acoustic wave filter device, steps S3 to S6 are performed on the large-sized wafer processing machine corresponding to the carrier wafer 20 (i.e., the machine that can directly process the carrier wafer, including the photolithography machine, the etching machine, the CMP machine, and the deposition machine). Therefore, the manufacturing method of the surface acoustic wave filter device provided by the invention has the advantages that the small-size piezoelectric wafer is firstly divided into the plurality of piezoelectric crystal grains and is temporarily bonded to the large-size carrier wafer, the manufacturing process of the surface acoustic wave filter device can be completed on the large-size wafer processing machine table corresponding to the size of the carrier wafer, the manufacturing process of the surface acoustic wave filter device is compatible with the processing process of the large-size wafer, the problem that equipment is purchased again when the large-size wafer replaces the surface acoustic wave filter device in a factory is solved, and the cost is reduced. In addition, according to the method for manufacturing the surface filter device of the embodiment, since the cut piezoelectric crystal grains 10 can be arranged on the carrier wafer 20 with the maximum integration level, the utilization rates of the carrier wafer 20 and the package substrate 40 can be improved, the operation of trimming the carrier wafer 20 and the package substrate 40 is avoided, and the yield of the finally manufactured surface filter device can be further improved.
The manufacturing method of the surface acoustic wave filter device is not only suitable for processing the common surface acoustic wave filter device, but also suitable for processing the temperature compensation type surface acoustic wave filter TC-SAW device. Referring to fig. 1 to 4 and fig. 6A to 6E, another embodiment of the present invention further provides a method for manufacturing a temperature compensation type surface acoustic wave filter TC-SAW device, including the following steps:
s1, providing a piezoelectric wafer 10 ' and a carrier wafer 20, wherein the size of the piezoelectric wafer 10 ' is smaller than that of the carrier wafer 20, please refer to fig. 2 and 3, and the specific material of the piezoelectric wafer 10 ' and the carrier wafer 20 can refer to the above description, and will not be described in detail herein.
S2, the piezoelectric wafer 10' is diced into a plurality of piezoelectric dies 10, each piezoelectric die 10 is temporarily bonded to the carrier wafer 20, and the gap between adjacent piezoelectric dies 10 is used as a dicing street 10a, please refer to fig. 2 to 4, and the specific process is described with reference to step S2 above, which is not described in detail herein.
S3, an insulating layer 11 is formed, the insulating layer 11 fills the scribe line 10a and exposes the top surface of each piezoelectric die 10, please refer to fig. 6A, the specific process of forming the insulating layer 11 is described with reference to step S3, and will not be described in detail herein.
S4, forming an interdigital electrode 12b and a first pad 12a on the top surface of each piezoelectric die 10, wherein the interdigital electrode 12b and the first pad 12a both expose the surface of the insulating layer 11 in the scribe line 10a, please refer to fig. 6A, and the specific forming process of the interdigital electrode 12b and the first pad 12a is described with reference to step S4 above, and will not be described in detail herein.
After step S4, first, referring to fig. 6A, depositing a temperature compensation layer 14 on top surfaces of the interdigital electrode 12a, the first bonding pad 12a, the piezoelectric crystal grain 10 and the insulating layer 11 by vapor deposition or the like, wherein a material of the temperature compensation layer 14 includes undoped or doped silicon oxide; then, the surface of the temperature compensation layer 14 may be planarized by a trimming (trim) machine such as a CMP machine; then, referring to fig. 6B, by using a photolithography and etching process, the temperature compensation layer 14 is patterned, and the remaining temperature compensation layer 14 buries the interdigital electrode 12a therein and exposes the top surface of the insulating layer 11 in each of the first pad 12a and the scribe line 10 a; then, referring to fig. 6C, a ball may be mounted on the first pad 12a to form a solder ball 13.
S5, providing a package substrate 40 having a plurality of second pads 41 and meeting the size requirement of the large-sized wafer processing machine, assembling the carrier wafer 20 having the piezoelectric die 10 on the package substrate 40, and aligning each of the first pads 12a and the corresponding second pads 41 and bump-bonding them through solder balls 13, as shown in fig. 6C. The specific process may refer to step S5 above, and will not be described in detail here.
S6, peeling the carrier wafer 20, and cutting the package substrate 40 and the insulating layer 11 along the cutting streets 10a to obtain a plurality of temperature compensated surface acoustic wave filters having the corresponding interdigital electrodes 12b, the piezoelectric crystal grains 10 and the package substrate 40, as shown in fig. 6D and 6E, the specific process can refer to step S6 above, and will not be described in detail herein.
It should be noted that, the temperature compensation layer in the above embodiment is formed after the interdigital electrode 12a, the interdigital electrode 12a can be buried inside and expose the top surface of the insulating layer 11 in each of the first bonding pad 12a and the scribe line 10a, and the temperature compensation layer plays a role in reducing the frequency-temperature coefficient, improving the performance of the device, that is, compensating the volume change of the piezoelectric crystal grain 10a caused by the temperature change, and reducing the frequency change of the finally manufactured TC-SAW filter caused by the temperature change. However, the solution of forming the temperature compensation layer in the present invention is not limited to the above embodiment. Specifically, in another embodiment of the present invention, a temperature compensation layer may be formed on the top surface of each of the piezoelectric dies 10 after step S3 and before step S4 (i.e., after the insulating layer 11 is formed and before the interdigital electrodes 12b and the first pads 12a are formed on the top surface of each of the piezoelectric dies 10. the step of forming the temperature compensation layer, the interdigital electrodes 12b and the first pads 12a includes, first, covering the temperature compensation layer on the surface of each of the piezoelectric dies 10 and the insulating layer 11 after step S3, and further planarizing the surface of the temperature compensation layer 14 by a finishing (trim) machine such as a CMP machine, and then patterning the temperature compensation layer to form interdigital grooves (not shown) and pad grooves (not shown) on the top surface of each of the piezoelectric dies 10, and the residual temperature compensation layer also exposes the top surface of the insulation layer 11 of the cutting street 10 a; then, step S4 is performed to deposit a metal layer to fill the finger grooves and pad grooves, planarize the metal layer to the top surface of the temperature compensation layer, and remove the excess metal layer in the scribe line 10a area to form the finger electrodes 12b and the first pad 12a, where the temperature compensation layer fills the gap between the finger electrodes 12b and exposes the top surfaces of the finger electrodes 12b, the first pad 12a, and the insulating layer 11 in the scribe line 10 a. The temperature compensation layer in this case is formed before the interdigital electrode 12a, and although the interdigital electrode 12a cannot be buried therein, it can also function as temperature compensation.
In still another embodiment of the present invention, a temperature compensation layer may be formed after step S3 and before step S4, and after step S4 and before step S5. The specific process comprises the following steps: first, after step S3, a first temperature compensation layer (not shown) is covered on the surface of each of the piezoelectric crystal grains 10 and the insulating layer 11, the material of the first temperature compensation layer includes undoped or doped silicon oxide, and the surface of the first temperature compensation layer is further planarized by a trimming (trim) machine such as a CMP machine; then, patterning the first temperature compensation layer to form an interdigital groove (not shown) and a pad groove (not shown) on the top surface of each of the piezoelectric dies 10, and exposing the top surface of the insulation layer 11 of the scribe line 10a by the remaining first temperature compensation layer; then, step S4 is performed, a metal layer is deposited to fill the finger groove and the pad groove, and the metal layer is planarized to the top surface of the first temperature compensation layer, and the excess metal layer in the scribe line 10a area is removed to form the finger electrode 12b and the first pad 12 a; then, covering a second temperature compensation layer (not shown) on the top surfaces of the interdigital electrode 12a, the first pad 12a, the piezoelectric die 10, the first temperature compensation layer and the insulating layer 11, wherein the material of the second temperature compensation layer comprises undoped or doped silicon oxide; then, the surface of the second temperature compensation layer can be flattened by a trimming (trim) machine such as a CMP machine; then, the second temperature compensation layer is patterned by a process of photolithography and etching, and the remaining second temperature compensation layer buries the interdigital electrode 12a and exposes the top surface of the insulating layer 11 in each of the first pad 12a and the scribe line 10a, so that the remaining first temperature compensation layer and the remaining second temperature compensation layer constitute the temperature compensation layer.
Based on the same inventive concept, the invention also provides a surface acoustic wave filter device which is manufactured by adopting the manufacturing method of the surface acoustic wave filter device in any embodiment. Referring to fig. 5D and 6E, the surface acoustic wave filter device includes a package substrate 40 and a piezoelectric die 10, wherein the piezoelectric die 10 is located above the package substrate 40. The package substrate 40 is provided with a second bonding pad 41, one surface of the piezoelectric crystal grain 10 facing the package substrate 40 is provided with an interdigital electrode 12b and a first bonding pad 12a, the first bonding pad 12a and the second bonding pad 41 are aligned and bump-bonded through a solder ball 13, and a space for acoustic wave resonance is provided between the piezoelectric crystal grain 10 and the package substrate 40.
Optionally, a surface of the interdigital electrode 12b facing the package substrate 40 is further covered with a temperature compensation layer 14, and the temperature compensation layer 14 buries the interdigital electrode 12b therein and exposes each of the first pads 12 a. Optionally, the material of the temperature compensation layer comprises undoped or doped silicon oxide.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (10)
1. A method for manufacturing a surface acoustic wave filter device, comprising the steps of:
providing a piezoelectric wafer and a carrier wafer, wherein the size of the piezoelectric wafer is smaller than that of the carrier wafer;
dividing the piezoelectric wafer into a plurality of piezoelectric crystal grains, temporarily bonding each piezoelectric crystal grain to the carrier wafer, and taking a gap between every two adjacent piezoelectric crystal grains as a cutting path;
forming interdigital electrodes and first pads on top surfaces of the respective piezoelectric dies;
providing a packaging substrate which is not smaller than the carrier wafer in size and is provided with a plurality of second bonding pads, assembling the carrier wafer with the piezoelectric crystal grains on the packaging substrate, and aligning each first bonding pad and the corresponding second bonding pad and carrying out bump bonding;
and peeling the carrier wafer, and cutting the packaging substrate along each cutting channel to obtain a plurality of surface acoustic wave filter devices.
2. A method of manufacturing a surface acoustic wave filter device as claimed in claim 1, characterized in that the individual piezoelectric grains are temporarily bonded to the carrier wafer by at least one of applying a bonding glue, attaching a bonding film and depositing a laser release layer on the carrier wafer.
3. The method of manufacturing a surface acoustic wave filter device according to claim 2, wherein the carrier wafer is peeled in accordance with the manner of the temporary bonding, and the manner of peeling includes thermal slide peeling, mechanical peeling, and laser peeling.
4. The method of manufacturing a surface acoustic wave filter device according to claim 1, wherein an insulating layer is further formed on the carrier wafer after temporarily bonding each piezoelectric die to the carrier wafer and before forming the interdigital electrodes and the first pads on the top surface of each piezoelectric die, the insulating layer filling the dicing channels and exposing the top surface of each piezoelectric die.
5. The method of manufacturing a surface acoustic wave filter device as set forth in claim 1, wherein a temperature compensation layer is further formed on the top surface of said piezoelectric crystal grain before and/or after forming said interdigital electrodes and said first bonding pads on the top surface of each of said piezoelectric crystal grains, said temperature compensation layer filling at least between the slits of said interdigital electrodes and exposing the top surface of each of said first bonding pads.
6. A method of manufacturing a surface acoustic wave filter device as set forth in claim 5, wherein the material of the temperature compensation layer comprises undoped or doped silicon oxide.
7. The method of manufacturing a surface acoustic wave filter device according to claim 5, wherein the step of forming the temperature compensation layer, the interdigital electrode, and the first pad includes:
covering a first temperature compensation layer on the surface of each of the piezoelectric dies and the insulating layer in the scribe line before forming the interdigital electrodes and the first pads on the top surface of each of the piezoelectric dies;
patterning the first temperature compensation layer to form interdigital grooves and pad grooves on the top surface of each of the piezoelectric dies;
depositing a metal layer to fill the interdigital groove and the pad groove, and flattening the metal layer to the top surface of the first temperature compensation layer to form the interdigital electrode and the first pad;
covering a second temperature compensation layer on the top surfaces of the first temperature compensation layer, the interdigital electrode and the first bonding pad, patterning the second temperature compensation layer to expose the top surface of the first bonding pad, wherein the first temperature compensation layer after patterning and the second temperature compensation layer after patterning form the temperature compensation layer.
8. The method of manufacturing a surface acoustic wave filter device according to claim 1, wherein the material of the piezoelectric wafer includes at least one of lithium niobate, lithium tantalate, aluminum nitride, barium titanate, lead zirconate titanate, and zinc oxide.
9. The method of manufacturing a surface acoustic wave filter device according to claim 1, wherein before the carrier wafer having the piezoelectric crystal grains is mounted on the package substrate, balls are attached to the first bonding pads or the second bonding pads to perform bump bonding after the first bonding pads and the second bonding pads are aligned.
10. A surface acoustic wave filter device manufactured by the method for manufacturing a surface acoustic wave filter device according to any one of claims 1 to 9; the surface acoustic wave filter device comprises a packaging substrate and a piezoelectric crystal grain which are packaged together, wherein the piezoelectric crystal grain is positioned above the packaging substrate; the packaging substrate is provided with a second bonding pad, one surface of the piezoelectric crystal grain, facing the packaging substrate, is provided with an interdigital electrode and a first bonding pad, the first bonding pad and the second bonding pad are aligned and bonded together, and a space for sound wave resonance is provided between the piezoelectric crystal grain and the packaging substrate.
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| CN114351202B (en) * | 2021-03-18 | 2023-08-25 | 青岛惠芯微电子有限公司 | Electroplating method of wafer |
| CN113872563A (en) * | 2021-08-26 | 2021-12-31 | 绍兴中芯集成电路制造股份有限公司 | Filter, filter packaging structure and filter manufacturing method |
| CN116761494A (en) * | 2023-08-22 | 2023-09-15 | 青禾晶元(晋城)半导体材料有限公司 | Composite piezoelectric substrate and preparation method thereof |
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