CN110739391A - Surface acoustic wave filter device and method of manufacturing the same - Google Patents

Surface acoustic wave filter device and method of manufacturing the same Download PDF

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Publication number
CN110739391A
CN110739391A CN201911019686.8A CN201911019686A CN110739391A CN 110739391 A CN110739391 A CN 110739391A CN 201911019686 A CN201911019686 A CN 201911019686A CN 110739391 A CN110739391 A CN 110739391A
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piezoelectric
wafer
acoustic wave
wave filter
pad
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CN110739391B (en
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项少华
王冲
王大甲
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SMIC Manufacturing Shaoxing Co Ltd
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SMIC Manufacturing Shaoxing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/01Manufacture or treatment
    • H10N30/07Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

The invention provides surface acoustic wave filter devices and a manufacturing method thereof, wherein a small-sized piezoelectric wafer is firstly divided into a plurality of piezoelectric crystal grains and is temporarily bonded onto a large-sized carrier wafer, so that the manufacturing process of the surface acoustic wave filter device can be completed on a large-sized wafer processing machine table corresponding to the size of the carrier wafer, the manufacturing process of the surface acoustic wave filter device is compatible with the processing process of the large-sized wafer, and therefore, the problem of equipment repurchase when the large-sized wafer replaces the surface acoustic wave filter device in a factory is avoided, and the cost is reduced.

Description

Surface acoustic wave filter device and method of manufacturing the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to surface acoustic wave filter devices and a manufacturing method thereof.
Background
The SAW (Surface Acoustic Wave) filter device is which is the mainstream piezoelectric Acoustic Wave filter device at present, and can meet the requirements of small-size filter devices used in communication terminals, and the preparation process of the SAW filter device at present is a 4-inch (inch) wafer process, because no mature growth technology of 8-inch piezoelectric materials exists at present, and the existing growth technology of 6-inch piezoelectric materials has the problem of poor in-chip processing property .
However, in order to further steps to reduce the cost, the current MEMS (Micro-Electro-Mechanical System) wafer foundry is gradually changing to 8-inch wafers, obviously, there are gaps between the SAW filter device and the MEMS wafer foundry, and the fabrication of the SAW filter is incompatible with the MEMS wafer foundry, so that if the MEMS foundry intends to foundry the SAW filter device, the related equipment needs to be re-purchased, which is greatly disadvantageous to the depreciation of the equipment and the reduction of the cost.
Disclosure of Invention
The invention aims to provide surface acoustic wave filter devices and a manufacturing method thereof, which can make the manufacturing process of the surface acoustic wave filter devices compatible with the processing process of large-size wafers and reduce the cost.
In order to achieve the above object, the present invention provides a manufacturing method of kinds of surface acoustic wave filter devices, comprising the steps of:
providing a piezoelectric wafer and a carrier wafer, wherein the size of the piezoelectric wafer is smaller than that of the carrier wafer;
dividing the piezoelectric wafer into a plurality of piezoelectric crystal grains, temporarily bonding each piezoelectric crystal grain to the carrier wafer, and taking a gap between every two adjacent piezoelectric crystal grains as a cutting path;
forming interdigital electrodes and th pads on the top surface of each of said piezoelectric dies;
providing a packaging substrate which is not smaller than the carrier wafer in size and is provided with a plurality of second bonding pads, assembling the carrier wafer with the piezoelectric crystal grains on the packaging substrate, and aligning each th bonding pad with the corresponding second bonding pad and carrying out bump bonding;
and peeling the carrier wafer, and cutting the packaging substrate along each cutting channel to obtain a plurality of surface acoustic wave filter devices.
Optionally, temporarily bonding individual piezoelectric dies to the carrier wafer by at least of applying a bonding glue, attaching a bonding film, and depositing a laser release layer on the carrier wafer.
Optionally, the carrier wafer is peeled according to the temporary bonding manner, and the peeling manner includes thermal slide peeling, mechanical peeling and laser peeling.
Optionally, after temporarily bonding each piezoelectric die to the carrier wafer and before forming the interdigital electrodes and the th pads on the top surface of each piezoelectric die, an insulating layer is further formed on the carrier wafer, the insulating layer filling the scribe lines and exposing the top surface of each piezoelectric die, and the interdigital electrodes and the th pads both expose the top surface of the insulating layer in the scribe lines.
Optionally, before and/or after forming the interdigital electrodes and the th pads on the top surfaces of the respective piezoelectric dies, a temperature compensation layer is further formed on the top surfaces of the piezoelectric dies, the temperature compensation layer filling at least the gaps of the interdigital electrodes and exposing the top surfaces of the respective th pads.
Optionally, the material of the temperature compensation layer comprises undoped or doped silicon oxide.
Optionally, the step of forming the temperature compensation layer, the interdigital electrode, and the th pad comprises:
covering a th temperature compensation layer on the surface of each of the piezoelectric dies and the insulating layer before forming the interdigital electrodes and the th bonding pads on the top surface of each of the piezoelectric dies;
patterning the th temperature compensation layer to form interdigital grooves and land grooves on the top surface of each of the piezoelectric dies;
depositing a metal layer to fill the interdigital grooves and the pad grooves, and planarizing the metal layer to the top surface of the th temperature compensation layer to form the interdigital electrodes and the th pad;
covering a second temperature compensation layer on top surfaces of the th temperature compensation layer, the interdigital electrode and the th pad, and patterning the second temperature compensation layer to expose a top surface of the th pad, the patterned th temperature compensation layer and the patterned second temperature compensation layer constituting the temperature compensation layer.
Optionally, the material of the piezoelectric wafer includes at least of lithium niobate, lithium tantalate, aluminum nitride, barium titanate, lead zirconate titanate, zinc oxide, and piezoelectric ceramic.
Optionally, before the carrier wafer with the piezoelectric die is assembled on the package substrate, the th pad or the second pad is ball-bonded, so that bump bonding is performed after the th pad and the second pad are aligned.
Based on the same conception, the invention also provides surface acoustic wave filter devices which are manufactured by the manufacturing method of the surface acoustic wave filter devices, wherein each surface acoustic wave filter device comprises a packaging substrate packaged from and a piezoelectric crystal grain, the piezoelectric crystal grain is positioned above the packaging substrate, the packaging substrate is provided with a second bonding pad, an interdigital electrode and a -th bonding pad are arranged on the surface of the piezoelectric crystal grain facing the packaging substrate, the -th bonding pad and the second bonding pad are aligned and bonded from , and a space for acoustic wave resonance is provided between the piezoelectric crystal grain and the packaging substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the method comprises the steps of firstly dividing a small-sized piezoelectric wafer into a plurality of piezoelectric crystal grains, and temporarily bonding the piezoelectric crystal grains to a large-sized carrier wafer, so that the manufacturing process of the surface acoustic wave filter device can be completed on a large-sized wafer processing machine table corresponding to the size of the carrier wafer, namely the manufacturing process of the surface acoustic wave filter device is compatible with the processing process of the large-sized wafer, and therefore the problem that equipment is purchased again when the large-sized wafer replaces the surface acoustic wave filter device in a factory is avoided, and cost is reduced.
2. And assembling the carrier wafer with the piezoelectric crystal grains on the packaging substrate, aligning each th bonding pad with the corresponding second bonding pad on the packaging substrate and performing bump bonding, so that a wafer-level packaging process with high integration level can be realized, and the packaging cost is further reduced by .
3. The method is not only suitable for manufacturing common surface acoustic wave filter devices, but also suitable for manufacturing temperature compensation type surface acoustic wave filter (TC-SAW) devices.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a surface acoustic wave filter device according to an embodiment of the present invention;
fig. 2 is a schematic top view of a piezoelectric wafer provided in step S1 of the method for manufacturing a surface acoustic wave filter device according to an embodiment of the present invention;
fig. 3 is a schematic top view of a piezoelectric crystal grain temporarily bonded to a carrier wafer in step S2 of the method for manufacturing a surface acoustic wave filter device according to the embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a surface acoustic wave filter device according to an embodiment of the present invention after a piezoelectric crystal grain is temporarily bonded to a carrier wafer in step S2;
fig. 5A to 5D are schematic cross-sectional views illustrating a method of manufacturing a surface acoustic wave filter device according to an embodiment of the present invention;
fig. 6A to 6E are schematic cross-sectional views illustrating a method of manufacturing a surface acoustic wave filter device according to another embodiment of the present invention.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a solution provided by the present invention will be described in further with reference to the accompanying drawings, wherein the drawings are in a simplified form and are in a non-exact scale for convenience and clarity in describing the embodiments of the present invention.
Referring to fig. 1, an embodiment of the present invention provides a method for manufacturing surface acoustic wave filters, including the steps of:
s1, providing a piezoelectric wafer and a carrier wafer, wherein the size of the piezoelectric wafer is smaller than that of the carrier wafer;
s2, dividing the piezoelectric wafer into a plurality of piezoelectric crystal grains, temporarily bonding each piezoelectric crystal grain to the carrier wafer, and taking the gap between the adjacent piezoelectric crystal grains as a cutting path;
s3, forming an insulating layer, wherein the insulating layer fills the cutting channel and exposes the top surface of each piezoelectric crystal grain;
s4, forming an interdigital electrode and a bonding pad on the top surface of each piezoelectric crystal grain, wherein the interdigital electrode and the bonding pad expose the surface of the insulating layer in the cutting channel;
s5, providing a packaging substrate which is not smaller than the carrier wafer in size and is provided with a plurality of second bonding pads, assembling the carrier wafer provided with the piezoelectric crystal grains on the packaging substrate, and aligning and electrically connecting each th bonding pad with the corresponding second bonding pad;
and S6, peeling the carrier wafer, and cutting the packaging substrate and the insulating layer along each cutting path to obtain a plurality of surface acoustic wave filter devices with corresponding piezoelectric crystal grains and packaging substrates.
Referring to fig. 2 to 4, in step S1, a piezoelectric wafer 10 'of 4 inches or 6 inches and a carrier wafer 20 of 8 inches or 12 inches may be provided, that is, the size of the piezoelectric wafer 10 is smaller than that of the provided silicon wafer 20, wherein the material of the piezoelectric wafer 10' includes at least of lithium niobate, lithium tantalate, aluminum nitride, barium titanate, lead zirconate titanate and zinc oxide, the piezoelectric wafer 10 'is also often referred to as a piezoelectric wafer, the material of the carrier wafer 20 includes at least of semiconductors (such as silicon, germanium, gallium arsenide, silicon on insulator, etc.), glass, quartz, silicon carbide, aluminum oxide, epoxy resin and polyurethane, the carrier wafer 20 is a large-sized wafer with respect to the piezoelectric wafer 10, the size of the carrier wafer 20 meets the wafer processing size requirement of a large-sized wafer processing machine, and the size of the piezoelectric wafer 10' is smaller than the carrier wafer 20 and does not meet the wafer processing size requirement of the large-sized wafer processing machine.
Referring to fig. 2 to 4, in step S2, the piezoelectric wafer 10' may be first divided into a plurality of piezoelectric dies 10 by a wafer dicing process, the size and shape of the piezoelectric dies 10 are substantially the same, the dividing process specifically includes attaching a blue film (not shown) on a bottom surface of the piezoelectric wafer 10, then cutting the piezoelectric wafer 10 from a top surface of the piezoelectric wafer 10 to a top surface of the blue film, and then removing the blue film to obtain a plurality of piezoelectric dies 10a, wherein the blue film may better fix the piezoelectric wafer 10 and fix the cut piezoelectric dies 10a, so as to prevent the cut piezoelectric dies 10a from flying out of a machine, thereby facilitating protection and collection of the piezoelectric dies 10a, and then, temporarily bonding each piezoelectric die 10 to the carrier wafer 20 by at least methods including coating a bonding glue, attaching a film, depositing a laser release layer (not shown) on the carrier wafer 20, and then forming a temporary bonding film for bonding the wafer 10a wafer after the wafer bonding film is etched into a wafer bonding wafer array (e.g., dicing wafer bonding wafer array) for forming a wafer bonding wafer array for temporary wafer bonding wafer 10a wafer 20, and wafer bonding wafer array (e.g., dicing wafer bonding wafer arrays) for forming a wafer array for example, wafer bonding wafer array for wafer 2, wafer bonding wafer 32, wafer bonding wafer 2, wafer bonding wafer 32, wafer bonding wafer 2, and wafer bonding wafer 2.
Referring to fig. 5A, in step S3, a film forming process such as vapor deposition or spin coating is performed on a large-sized wafer processing machine (e.g., a vapor deposition device, an oxidation furnace, or a film coating machine) corresponding to the carrier wafer 20 to cover the insulating layer 11 on the piezoelectric dies 10 and the carrier wafer 20, the insulating layer 11 at least fills up the scribe lines 10a, and then the top surface of the insulating layer 11 is polished by a Chemical Mechanical Polishing (CMP) process to expose the top surface of each piezoelectric die 10 a. in other embodiments of the present invention, the insulating layer 11 may be etched back by an etch-back process to expose the top surface of each piezoelectric die 10. the material of the insulating layer 11 includes a plastic molding material, silicon oxide, silicon oxynitride, silicate glass (e.g., borosilicate glass bsg., phosphosilicate glass PSG, borophosphosilicate glass (BPSG), Undoped Silicate Glass (USG), a low K dielectric medium (dielectric constant K less than 4), or polyimide) at least of the insulating layer , the insulating layer 11 can enhance the reliability of the piezoelectric dies 10, prevent the sidewall damage of the piezoelectric dies from being caused by a bpg, and the sidewall damage of the piezoelectric dies produced by the subsequent bonding process, and can be omitted in the subsequent processes, so as well as to prevent the sidewall damage of course, the piezoelectric dies 10, and the piezoelectric devices produced in the subsequent embodiments, if the piezoelectric dies 10, the piezoelectric bonding process, the piezoelectric dies 10, the piezoelectric devices produced by the present invention, and the present invention, and.
With reference to fig. 5A, in step S4, a metal layer (not shown) is first deposited on the insulating layer 11 and each piezoelectric die 10 by vacuum evaporation, sputter deposition, or the like on a large-sized wafer processing machine corresponding to the size of the carrier wafer 20, the metal layer being made of at least of tungsten, silver, zirconium, molybdenum, platinum (i.e., platinum), ruthenium, iridium, titanium, tungsten, copper, chromium, hafnium, and aluminum, and then the metal layer (not shown) is patterned by a process of photolithography in combination with dry etching to form the interdigital electrode 12b and the pad 12a, the interdigital electrode 12b and the pad 12a both exposing the top surface of the insulating layer 11 in the scribe line 10a, wherein the pad 12a is used to subsequently achieve bonding with the package substrate, the interdigital electrode 12b is an electrode having a periodic pattern in a plane such as a finger or comb-like, the pad 12b is typically paired, whereby an input electrical signal is transferred through through the pad 12b on the substrate, the pad 12b is transferred through a photoresist pad 12b, and the pad 12b is transferred to the pad 12b by a photoresist pad 12b, and then the pad 12b, the pad 12b is removed by a photoresist pad forming process of a photoresist pad 12b, and the pad 12b, wherein the photoresist pad 12b is removed by a photoresist pad after the photoresist pattern is removed by a photoresist pattern, the photoresist pattern, and the photoresist pattern, the photoresist pattern is removed by a photoresist pattern, the photoresist pattern of which is removed by a process of the photoresist pattern of which is removed, i.e.e.g., photoresist pattern of the photoresist pattern.
With continued reference to fig. 5A, in order to subsequently realize bump bonding between the 20 surface of the carrier wafer 20 having the -th bonding pad 12a and the interdigital electrode 12b and the surface of the package substrate 40, a ball may be first planted on the -th bonding pad 12a to form a solder ball 13, where the solder ball 13 may be a tin solder ball, a lead solder ball, a tin-lead solder ball, a silver solder ball, a tin-silver-copper solder ball, or a copper pillar.
Referring to fig. 5B, in step S5, a package substrate 40 having a plurality of second pads 41 and a size not smaller than the carrier wafer 20 is first provided, the package substrate 40 may be a high temperature co-fired Ceramic (HTCC) substrate having a size equal to that of the carrier wafer 20, and the HTCC substrate molding process includes printing a heat-generating resistive paste protecting at least high melting point metals such as tungsten, molybdenum, manganese, etc. on 92% -96% alumina cast Ceramic green bodies according to the requirements of heat-generating circuit design, laminating the layers under the action of 4% -8% sintering aid, co-firing at 1500-1600 ℃, and then, mounting the carrier wafer 20 having the piezoelectric crystal grains 10 on the package substrate 40 on a large-sized wafer processing machine (i.e., wafer bonding machine) corresponding to the size of the carrier wafer 20, and aligning each of the pads 12a and the corresponding second pads 41 to the pads of the package substrate 40, and mounting the package substrate having the bumps about 76 a bump bonding stage of the piezoelectric crystal grains 10 on the package substrate 40 by the step S3913.
It should be noted that, in other embodiments of the present invention, before the carrier wafer 20 with the piezoelectric die 10 is assembled on the package substrate 40, balls may be planted on the second pads 41 instead of the th pads 12a, or balls may be planted on both the th pads 12a and the second pads 41, so as to achieve bump bonding between the th pads 12a and the second pads 41.
In step S6, referring to fig. 5B and 5C, an appropriate wafer lift-off method may be selected to lift off the carrier wafer 20 from the piezoelectric dies 10 according to the temporary bonding manner in step S2, wherein the lift-off manner includes thermal slide lift-off, mechanical lift-off and laser lift-off, and in , the temporary bonding layer 30 between the carrier wafer 20 and each piezoelectric die 10 protects the piezoelectric dies 10 when the carrier wafer 20 is removed and still remains on the surfaces of the piezoelectric dies 10 for subsequent cutting of the dicing channels between the piezoelectric dies 10, and then, referring to fig. 5D, the package substrate 40 and the insulating layer 11 may be cut along each dicing channel 10a from the piezoelectric die 10 side to obtain a plurality of surface acoustic wave filter devices 50 having the corresponding interdigital electrodes 12B, the piezoelectric dies 10 and the package substrate 40.
In the above method for manufacturing a surface acoustic wave filter, steps S3 to S6 are performed on a large-sized wafer processing machine corresponding to the carrier wafer 20 (i.e., a machine capable of directly processing the carrier wafer, including a photolithography machine, an etching machine, a CMP machine, a deposition machine, etc.). Therefore, the manufacturing method of the surface acoustic wave filter device provided by the invention has the advantages that the small-size piezoelectric wafer is firstly divided into the plurality of piezoelectric crystal grains and is temporarily bonded to the large-size carrier wafer, the manufacturing process of the surface acoustic wave filter device can be completed on the large-size wafer processing machine table corresponding to the size of the carrier wafer, the manufacturing process of the surface acoustic wave filter device is compatible with the processing process of the large-size wafer, the problem that equipment is purchased again when the large-size wafer replaces the surface acoustic wave filter device in a factory is solved, and the cost is reduced. In addition, according to the method for manufacturing the surface filter device of the embodiment, since the cut piezoelectric crystal grains 10 can be arranged on the carrier wafer 20 with the maximum integration level, the utilization rates of the carrier wafer 20 and the package substrate 40 can be improved, the operation of trimming the carrier wafer 20 and the package substrate 40 is avoided, and the yield of the finally manufactured surface filter device can be further improved.
Referring to fig. 1 to 4 and fig. 6A to 6E, another embodiment of the present invention further provides a manufacturing method of temperature compensation type surface acoustic wave filter TC-SAW devices, including the following steps:
s1, providing a piezoelectric wafer 10 ' and a carrier wafer 20, wherein the size of the piezoelectric wafer 10 ' is smaller than that of the carrier wafer 20, please refer to fig. 2 and 3, and the specific material of the piezoelectric wafer 10 ' and the carrier wafer 20 can refer to the above description, and will not be described in detail herein.
S2, the piezoelectric wafer 10' is diced into a plurality of piezoelectric dies 10, each piezoelectric die 10 is temporarily bonded to the carrier wafer 20, and the gap between adjacent piezoelectric dies 10 is used as a dicing street 10a, please refer to fig. 2 to 4, and the specific process is described with reference to step S2 above, which is not described in detail herein.
S3, an insulating layer 11 is formed, the insulating layer 11 fills the scribe line 10a and exposes the top surface of each piezoelectric die 10, please refer to fig. 6A, the specific process of forming the insulating layer 11 is described with reference to step S3, and will not be described in detail herein.
S4, forming an interdigital electrode 12b and a pad 12a on the top surface of each piezoelectric die 10, wherein the interdigital electrode 12b and the pad 12a both expose the surface of the insulating layer 11 in the scribe line 10a, please refer to fig. 6A, and the specific forming process of the interdigital electrode 12b and the pad 12a refers to the above step S4, which is not described in detail herein.
After step S4, referring to fig. 6A, a temperature compensation layer 14 is deposited on the top surfaces of the interdigital electrode 12a, the th pad 12a, the piezoelectric die 10 and the insulating layer 11 by a vapor deposition process, etc., the material of the temperature compensation layer 14 includes undoped or doped silicon oxide, then the surface of the temperature compensation layer 14 may be planarized by a CMP machine, etc., then, referring to fig. 6B, the temperature compensation layer 14 is patterned by a photolithography and etching process, the remaining temperature compensation layer 14 buries the interdigital electrode 12a and exposes the top surface of the insulating layer 11 in each of the th pad 12a and the scribe line 10a, and then, referring to fig. 6C, a solder ball 13 may be formed on the th pad 12 a.
S5, providing a package substrate 40 having a plurality of second pads 41 and meeting the size requirement of the large-sized wafer processing machine, assembling the carrier wafer 20 having the piezoelectric die 10 on the package substrate 40, and aligning each -th pad 12a with the corresponding second pad 41 and bump-bonding the second pad through the solder ball 13, as shown in fig. 6C.
S6, peeling the carrier wafer 20, and cutting the package substrate 40 and the insulating layer 11 along the cutting streets 10a to obtain a plurality of temperature compensated surface acoustic wave filters having the corresponding interdigital electrodes 12b, the piezoelectric crystal grains 10 and the package substrate 40, as shown in fig. 6D and 6E, the specific process can refer to step S6 above, and will not be described in detail herein.
It should be noted that the temperature compensation layer in the above embodiment is formed after the interdigital electrode 12a, the interdigital electrode 12a can be buried inside and expose the top surface of the insulating layer 11 in each of the th pad 12a and the scribe line 10a, and serves as a temperature compensation, which is advantageous for reducing the frequency-temperature coefficient and improving the device performance, i.e., compensating for the volume change of the piezoelectric die 10a caused by the temperature change and reducing the frequency change of the finally manufactured TC-SAW filter caused by the temperature change, although the temperature compensation layer in the above embodiment is formed after the interdigital electrode 12a is formed and after the interdigital electrode 12a is formed, the top surface of the interdigital electrode 12a is exposed, the top surface of the insulating layer 12a is exposed, and the top surface of the scribe line 10a is formed, and serves as a temperature compensation layer for the dicing SAW 10a, the temperature compensation layer is formed on the top surface of the piezoelectric die 10 b, the temperature compensation layer is formed after the step S3 and before the step S4 is performed (i.e., after the insulating layer 11 is formed, and before the interdigital electrode 12b and the interdigital electrode 12a is formed on the top surface of each of the dicing SAW die 10a, the interdigital electrode 12a, the top surface of the interdigital electrode 12a is formed, the interdigital electrode 12b, the dicing SAW 12a, the interdigital electrode 12a, the dicing SAW 12a, the interdigital electrode 12a is formed, the top surface of the interdigital electrode 12a is formed, the interdigital electrode 12b, the interdigital electrode 12a, the interdigital electrode 12b, the dicing SAW 12b, the interdigital electrode 12b, the dicing SAW 12a, the dicing SAW 12b, the dicing SAW 12a, the interdigital electrode 12a, the dicing SAW 12a, the temperature compensation layer is removed, the dicing SAW 12a, the top surface of the interdigital layer is removed, the.
In a further embodiment of the present invention, a temperature compensation layer may be formed after step S3 and before step S4 and after step S4 and before step S5. the specific process includes first, after step S3, covering a temperature compensation layer (not shown) on the surface of each of the piezoelectric dies 10 and the insulating layer 11, the material of the temperature compensation layer including undoped or doped silicon oxide, and step of planarizing the surface of the temperature compensation layer by a CMP tool or the like, then patterning the th temperature compensation layer to form interdigitated grooves (not shown) and land grooves (not shown) on the top surface of each of the piezoelectric dies 10, and the remaining temperature compensation layer also exposing the top surface of the insulating layer 11 of the dicing street 10a, then, performing step S8, depositing a metal layer to fill the interdigitated grooves and the planarized metal layer, and planarizing the top surface of the second buried pad 12, and further etching the remaining interdigital pad 12a layer of the buried pad 12, and etching the remaining pad 12 layer of the buried pad 12, thereby forming a buried pad 12a, and the buried pad 12a, and the pad 12 are etched by a etching process, wherein the temperature compensation layer of the buried pad 12 is further, the temperature compensation layer of the buried pad is formed by a and the pad forming a, the pad of the pad is etched pad under the temperature compensation layer of the buried pad under the temperature compensation layer of the temperature compensation layer, and the temperature compensation layer of the buried pad of the buried pad of the pad type 3610 a pad, and pad of the pad, and the pad of the pad type, wherein the pad of the pad type, and the pad type, wherein the pad type, the pad type.
Referring to fig. 5D and 6E, the surface acoustic wave filter device includes a package substrate 40 packaged at and a piezoelectric crystal grain 10, the piezoelectric crystal grain 10 is located above the package substrate 40, wherein a second bonding pad 41 is disposed on the package substrate 40, an interdigital electrode 12b and a bonding pad 12a are disposed on a surface of the piezoelectric crystal grain 10 facing the package substrate 40, the bonding pad 12a and the second bonding pad 41 are aligned and bump-bonded through a solder ball 13, and a space for acoustic wave resonance is provided between the piezoelectric crystal grain 10 and the package substrate 40.
Optionally, the side of the interdigital electrode 12b facing the package substrate 40 is further covered with a temperature compensation layer 14, and the temperature compensation layer 14 buries the interdigital electrode 12b therein and exposes each bonding pad 12 a.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.

Claims (10)

1, methods for manufacturing surface acoustic wave filter devices, comprising the steps of:
providing a piezoelectric wafer and a carrier wafer, wherein the size of the piezoelectric wafer is smaller than that of the carrier wafer;
dividing the piezoelectric wafer into a plurality of piezoelectric crystal grains, temporarily bonding each piezoelectric crystal grain to the carrier wafer, and taking a gap between every two adjacent piezoelectric crystal grains as a cutting path;
forming interdigital electrodes and th pads on the top surface of each of said piezoelectric dies;
providing a packaging substrate which is not smaller than the carrier wafer in size and is provided with a plurality of second bonding pads, assembling the carrier wafer with the piezoelectric crystal grains on the packaging substrate, and aligning each th bonding pad with the corresponding second bonding pad and carrying out bump bonding;
and peeling the carrier wafer, and cutting the packaging substrate along each cutting channel to obtain a plurality of surface acoustic wave filter devices.
2. A method of manufacturing a surface acoustic wave filter device as set forth in claim 1, wherein each piezoelectric die is temporarily bonded to the carrier wafer by at least of the steps of applying a bonding glue, attaching a bonding film, and depositing a laser release layer on the carrier wafer.
3. The method of manufacturing a surface acoustic wave filter device according to claim 2, wherein the carrier wafer is peeled in accordance with the manner of the temporary bonding, and the manner of peeling includes thermal slide peeling, mechanical peeling, and laser peeling.
4. The method of manufacturing a surface acoustic wave filter device as set forth in claim 1, wherein an insulating layer is further formed on said carrier wafer after temporarily bonding each piezoelectric die to said carrier wafer and before forming said interdigital electrodes and said th pads on the top surface of each of said piezoelectric dies, said insulating layer filling said scribe line and exposing the top surface of each of said piezoelectric dies.
5. The method of manufacturing a surface acoustic wave filter device as set forth in claim 1, wherein a temperature compensation layer is further formed on the top surfaces of said piezoelectric crystal grains before and/or after forming said interdigital electrodes and said -th pads on the top surfaces of said respective piezoelectric crystal grains, said temperature compensation layer filling at least between the slits of said interdigital electrodes and exposing the top surfaces of said respective -th pads.
6. A method of manufacturing a surface acoustic wave filter device as set forth in claim 5, wherein the material of the temperature compensation layer comprises undoped or doped silicon oxide.
7. The method of manufacturing a surface acoustic wave filter device as set forth in claim 5, wherein the step of forming said temperature compensation layer, said interdigital electrode and said th pad comprises:
covering a th temperature compensation layer on the surface of each of the piezoelectric dies and the insulating layer before forming the interdigital electrodes and the th bonding pads on the top surface of each of the piezoelectric dies;
patterning the th temperature compensation layer to form interdigital grooves and land grooves on the top surface of each of the piezoelectric dies;
depositing a metal layer to fill the interdigital grooves and the pad grooves, and planarizing the metal layer to the top surface of the th temperature compensation layer to form the interdigital electrodes and the th pad;
covering a second temperature compensation layer on top surfaces of the th temperature compensation layer, the interdigital electrode and the th pad, and patterning the second temperature compensation layer to expose a top surface of the th pad, the patterned th temperature compensation layer and the patterned second temperature compensation layer constituting the temperature compensation layer.
8. A method of manufacturing a surface acoustic wave filter device according to claim 1, wherein the material of the piezoelectric wafer includes at least of lithium niobate, lithium tantalate, aluminum nitride, barium titanate, lead zirconate titanate, and zinc oxide.
9. The method of manufacturing a surface acoustic wave filter device as set forth in claim 1, wherein before the carrier wafer having the piezoelectric die is mounted on the package substrate, balls are first mounted on the th land or the second land to perform bump bonding after the th land and the second land are aligned.
10, surface acoustic wave filter device, characterized in that, it is manufactured by the method of any claim 1-9, the surface acoustic wave filter device includes a package substrate packaged at and a piezoelectric crystal grain above the package substrate, wherein, the package substrate is provided with a second bonding pad, the surface of the piezoelectric crystal grain facing the package substrate is provided with an interdigital electrode and a bonding pad, the bonding pad and the second bonding pad are aligned and bonded at , and a space for acoustic wave resonance is provided between the piezoelectric crystal grain and the package substrate.
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