CN110739351A

CN110739351A - Semiconductor power element and method for manufacturing the same

Info

Publication number: CN110739351A
Application number: CN201810789783.4A
Authority: CN
Inventors: 唐松年; 陈和泰; 许修文
Original assignee: SHUAIQUN MICROELECTRONIC CO Ltd
Current assignee: SHUAIQUN MICROELECTRONIC CO Ltd; Super Group Semiconductor Co Ltd
Priority date: 2018-07-18
Filing date: 2018-07-18
Publication date: 2020-01-31

Abstract

The invention discloses semiconductor power elements and a manufacturing method thereof, the manufacturing method of the semiconductor power elements comprises the steps of forming a semiconductor layer on a substrate, forming at least a body region and a source region in the body region in the semiconductor layer, defining a channel region between the edge of the source region and the edge of the body region, forming a gate stack structure on the semiconductor layer and overlapping the channel region in the vertical direction, forming at least a spacing part to cover the side wall surface of the gate stack structure, covering the part of the source region by the spacing part, exposing the other part of the source region to the upper surface, carrying out a self-aligned silicification process by taking the spacing part and the gate stack structure as a shield to form a silicide layer contacting the source region, and forming an interconnection circuit structure on the semiconductor layer.

Description

Semiconductor power element and method for manufacturing the same

Technical Field

The present invention relates to semiconductor power devices and methods for fabricating the same, and more particularly, to vertical double diffused metal oxide semiconductor field effect transistors and methods for fabricating the same.

Background

For the conventional semiconductor power devices (e.g., horizontal Double-diffused MOSFET (LDMOSFET) and Vertical Double-diffused MOSFET (VDMOSFET)), breakdown voltage (breakdown voltage) and on-resistance (on-resistance) are important parameters, wherein the on-resistance affects the conduction loss of the semiconductor power device.

For the case of vertical double diffused transistors, generally reduces the on-resistance by increasing the carrier concentration in the drift region of the semiconductor power device.

Disclosure of Invention

The technical problem to be solved by the present invention is how to further reduce the on-resistance of the semiconductor power device without affecting the breakdown voltage of the semiconductor power device.

To solve the above problems, a embodiment of the present invention provides methods for manufacturing a semiconductor power device, wherein the aforementioned method comprises forming a semiconductor layer on an substrate, wherein the semiconductor layer has at least 2 body regions and source regions in the body regions, the source regions are connected to the top surface of of the semiconductor layer, and 5 channel regions are defined between the edges of the source regions and the body regions, forming 6 gate stack structure on the semiconductor layer and overlapping the channel regions in the direction perpendicular to , forming at least spacers to cover the sidewall surfaces of the gate stack structure, wherein the spacers cover portions of the source regions and another portion of the source regions is exposed to the top surface, performing a self-aligned silicidation process using the spacers and the gate stack structure as masks to form contact source regions, and forming an interconnect structure on the semiconductor layer, wherein the interconnect structure comprises at least a source region electrically connected to the interlayer silicide conductive layer and extends from the bottom of the source region to the interlayer silicide layer.

Further , the step of forming the gate stack structure further includes sequentially forming a gate insulating material layer, an initial gate layer and an initial shield layer on the upper surface of the semiconductor layer to form an initial gate stack structure, and patterning the initial gate stack structure to form the gate stack structure, the gate stack structure partially exposing the source region.

Further , the gate stack structure includes a gate insulator, a gate and a shield layer covering the gate.

Further , the step of forming the interconnect structure includes forming a layer of interlayer dielectric material that completely covers the silicide layer, the spacers and the gate stack, patterning the layer of interlayer dielectric material to form an interlayer dielectric having at least a source contact opening through which the silicide layer is exposed, and forming a source conductive layer within the source contact opening to electrically connect the source region through the contact silicide layer.

Further , the interlayer dielectric layer further has a gate contact opening, the gate contact opening and the source contact opening are both formed during the step of patterning the interlayer dielectric material layer, and the step of forming the interconnect structure further includes removing a portion of the shield layer through the gate contact opening to expose the gate after the step of patterning the interlayer dielectric material layer, and forming a gate conductive layer in the gate contact opening to electrically connect the gate conductive layer to the gate, wherein the gate conductive layer and the source conductive layer are spaced apart from each other.

Further , the semiconductor layer is defined to have a device region and a termination region, the gate stack has a th portion in the device region and a second portion in the termination region, and the gate contact opening corresponds to the second portion.

Further , the step of forming the spacer includes forming a layer of dielectric material overlying the top surface of the semiconductor layer and the gate stack structure, and performing an etching step to remove a portion of the layer of dielectric material overlying the gate stack structure and overlying the top surface to form the spacer.

Further , the thickness of the spacer decreases from bottom to top in a direction parallel to the width of the gate stack structure.

Further , the salicidation process includes forming a conductive layer entirely covering the top surface of the semiconductor layer, the spacers, and the gate stack, performing a heat treatment on the conductive layer to promote reaction of a portion of the conductive layer with the semiconductor layer to form a silicide layer, and removing the unreacted conductive layer.

Another technical solution adopted by the present invention is to provide kinds of semiconductor power devices, which include a substrate, a semiconductor layer disposed on the substrate, and at least having a 0 body region and a source region located in the body region, the source region being connected to the upper surface of the semiconductor layer, and a channel region being defined between the edge of the source region and the edge of the body region, a spacer disposed on the semiconductor layer and overlapping the channel region in the vertical direction, the spacer covering the sidewall of the gate stack, wherein the spacer covers the portion of the source region, contacts the source region, and the interconnect structure includes a interlayer dielectric layer and an source conductive layer, the interlayer dielectric layer having at least a source contact opening, and the source conductive layer being disposed on the interlayer dielectric layer and contacting the silicide layer through the source contact opening to electrically connect the source region, and the source conductive layer extending from the lower side of the source conductive layer to the lower side of the gate stack structure.

Further , the semiconductor layer is defined to have a device region and a terminal region, the gate stack structure has a th portion located in the device region and a second portion located in the terminal region, and the interlayer dielectric layer further has a gate contact opening corresponding to the second portion.

Further , the shielding layer of the second portion has a extension opening in communication with the gate contact opening, and the interconnect structure further includes a gate conductive layer disposed in the termination region and electrically connected to the gate through the gate contact opening and the extension opening.

The semiconductor power device and the method for manufacturing the same according to the present invention have the advantages that the shortest distance between the silicide layer and the channel region can be reduced by the technical means of forming the spacer covering the sidewall of the gate stack structure before forming the interconnect structure and performing the salicide process, since the resistance of the silicide is usually lower than the resistance of the source region itself, the distance between the silicide and the channel region is reduced, and the on-resistance of the semiconductor power device can be further reduced by .

To further enable the understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the present invention and accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the present invention.

Drawings

Fig. 1 shows a flow chart of a semiconductor power device of an embodiment of the invention.

Fig. 2A is a schematic partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 2B is a partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 2C is a schematic partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 2D is a partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 2E is a partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 2F is a partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 2G is a schematic partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 2H is a partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 3A is a schematic partial cross-sectional view of a semiconductor power device according to an embodiment of the invention.

Fig. 3B is a partial top view of a semiconductor power device according to an embodiment of the invention.

Fig. 3C is a partial cross-sectional view of the semiconductor power device of fig. 3B along line IIIC-IIIC.

Fig. 3D is a partial cross-sectional view of the semiconductor power device of fig. 3B along line IIID-IIID.

Fig. 4A is a partial top view of a semiconductor power device according to an embodiment of the invention.

Fig. 4B is a partial cross-sectional view of the semiconductor power device of fig. 4A along line IVB-IVB.

Fig. 4C is a partial cross-sectional view of the semiconductor power device of fig. 4A along line IVC-IVC.

Detailed Description

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor power device according to an embodiment of the invention.

At step S100, a semiconductor layer is formed on the substrate, and at step S110, a gate stack structure is formed on the semiconductor layer, and at least spacers are formed to cover the sidewall surfaces of the gate stack structure at step S120. at step S130, a salicide process is performed with the spacers and the gate stack structure as a mask, and then a silicide layer is formed to contact the source region, and at step S140, a interconnect structure is formed on the semiconductor layer.

As described above, in the present embodiment, before the step of forming the interconnect structure, the spacer portion covering the sidewall of the gate stack structure is formed, and a salicidation process is performed. Specific steps in the manufacturing method of the semiconductor power element will be described in detail below.

Referring to fig. 1 and fig. 2A, fig. 2A is a partial cross-sectional view of a semiconductor power device in step S100 according to an embodiment of the invention .

A semiconductor layer 11 is disposed on the substrate 10, wherein the semiconductor layer 11 has an upper surface 11a remote from the substrate 10.

The substrate 10 has a high concentration of th type conductivity impurity to serve as a drain region (drain) of the semiconductor power device the th type conductivity impurity may be an N-type or P-type conductivity impurity the substrate 10 may be silicon, silicon carbide, or other semiconductor material.

Assuming that the substrate 10 is a silicon carbide substrate, the N-type conductivity impurity is a pentavalent ion, such as a phosphorus ion or an arsenic ion, and the P-type conductivity impurity is a trivalent ion, such as a boron ion, an aluminum ion, or a gallium ion.

The material of the semiconductor layer 11 may be the same as the substrate 10 and have the same conductivity type as the substrate 10. However, the doping concentration of the semiconductor layer 11 is lower than that of the substrate 10. In the case of an NMOS transistor, the substrate 10 has a high concentration of N-type dopant (N)⁺) And the semiconductor layer 11 has a low concentration of N-type doping (N)^-). For example, in the case of a PMOS transistor, the substrate 10 and the semiconductor layer 11 have a high concentration of P-type dopant (P)⁺doping) and low concentration of P-type doping (P)^-doping)。

Silicon carbide has a wider band gap and has preferred thermal conductivity compared to silicon. In addition, semiconductor power devices made of silicon carbide have a high switching speed, low power loss, and high breakdown voltage. Therefore, in the present embodiment, the material of both the substrate 10 and the semiconductor layer 11 is silicon carbide.

It should be noted that the semiconductor layer 11 may be defined as an element region and a termination region, and fig. 2A is a partial cross-sectional schematic diagram of the element region of the semiconductor power element.

In addition, in the embodiment of fig. 2A, the semiconductor layer 11 can be divided into a drift region 110(drift region), a body region 111(body region) and a source region 112(source region) by doping different regions with different concentrations and different types of conductive impurities. The body region 111 and the source region 112 are closer to the upper surface 11a of the semiconductor layer 11, i.e., formed in the upper half of the semiconductor layer 11.

In , semiconductor layer 11 is subjected to a body doping process to form body region 111, wherein the body doping process is used to dope semiconductor layer 11 with impurities of the second type of conductivity, it should be noted that body region 111 is distributed in the device region and the termination region.

Thereafter, the semiconductor layer 11 is subjected to source doping process to form the source region 112. the source doping process is to dope the th type conductivity impurity with high concentration in the body region 111, and the doping concentration of the source region 112 is greater than that of the body region 111.

The source region 112 is formed in the body region 111 and located in the device region, the source region 112 is separated from the drift region 110 by the body region 111 to define at least channel regions 113, and the channel region 113 is located between an edge of of the source region 112 and an edge of of the body region 111 and is adjacent to the upper surface 11a of the semiconductor layer 11 in step .

In fig. 2A, two body regions 111 are separated from each other by the drift region 110 and define two channel regions 113 with two source regions 112, respectively.

Next, step S110 of fig. 1 is performed. Referring to fig. 2B to fig. 2D, a detailed process of forming a gate stack structure on the semiconductor layer 11 according to an embodiment of the invention is shown.

As shown in fig. 2B, the gate insulating material layer 120 ' and the initial gate layer 121 ' are formed on the upper surface 11a of the semiconductor layer 11, and the initial gate layer 121 ' covers the entire upper surface 11a of the semiconductor layer 11.

The material of the gate insulating material layer 120' may be a nitride or an oxide, such as: silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material.

The initial gate layer 121 'is formed on the gate insulating material layer 120' to be isolated from the semiconductor layer 11 by the gate insulating material layer 120 ', the material of the initial gate layer 121' is a conductive material, such as heavily doped polysilicon or other metal or alloy, in the embodiment, the thickness of the initial gate layer 121 'is greater than the thickness of the gate insulating material layer 120'.

Referring to fig. 2C, in the method of the present embodiment, an initial shielding layer 122 ' is further formed on the initial gate layer 121 ', accordingly, the gate insulating material layer 120 ', the initial gate layer 121 ', and the initial shielding layer 122 ' form the initial gate stack 12 ', the material of the initial shielding layer 122 ' may be a nitride or an oxide, which is not limited by the invention.

Referring to fig. 2D, the initial gate stack structure 12' is patterned to form the gate stack structure 12. it should be noted that the gate stack structure 12 has an th portion 12A located in the device region and a second portion 12b located in the termination region, and thus, fig. 2D only shows a cross-sectional view of the th portion 12A of the gate stack structure 12 for illustration.

Specifically, the gate stack structure may be formed by dry etching or wet etching the aforementioned gate insulating material layer 120 ', the initial gate layer 121 ', and the initial shielding layer 122 '.

Accordingly, the gate stack 12 includes a gate insulating layer 120, a gate electrode 121, and a shielding layer 122 overlying the gate electrode 121. after etching to remove a portion of the gate insulating material layer 120 ', the gate insulating layer 120 is formed. similarly, the gate electrode 121 is formed by etching the initial gate layer 121 ', and the shielding layer 122 is formed by etching the initial shielding layer 122 '.

The gate stack 12 overlaps the body region 111 with the source region 112 in the vertical direction . in fig. 2D, the source regions 112 are respectively connected to two opposite sides of the gate stack 12, and the gate stack overlaps the channel regions 113. in step , the gate stack 12 overlaps the channel regions 113 in the vertical direction to control the turn-on and turn-off of the semiconductor power device.

Taking an NMOS transistor as an example, when a positive bias is applied to the gate 121, electrons accumulate in the channel region 113, so that a current is generated in the channel region 113, and the NMOS transistor is turned on. Accordingly, when the gate electrode 121 is negatively biased, the NMOS transistor is turned off.

In addition, the gate stack structure 12 does not completely cover the source region 112, but the source region 112 is partially exposed on the upper surface 11a of the semiconductor layer 11, so as to fabricate an interconnect structure for electrically connecting the source region 112 and the gate 121 to an external control circuit.

Next, step s120 of fig. 1 is performed, referring to fig. 2E to 2F, showing a detailed flow of forming the spacers, as shown in fig. 2E, a dielectric material layer 13' is first formed covering the upper surface 11a of the semiconductor layer 11 and the outer surface (including the sidewall surface and the top surface) of the gate stack structure 12.

The layer of dielectric material 13' may be a nitride layer or an oxide layer, for example: a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer, etc., and the present invention is not limited thereto. In addition, the thickness of the dielectric material layer 13' is approximately between 50 nm and 500 nm.

Next, as shown in fig. 2F, an etching step is performed to remove portions of the dielectric material layer 13 'covering the gate stack structure 12 and the top surface 11a to form the spacers 13S, specifically, portions of the dielectric material layer 13' covering the top surface of the gate stack structure 12 and the top surface 11a of the semiconductor layer 11 are removed, leaving only the dielectric material layer covering the sidewall surfaces of the gate stack structure 12 to form the spacers 13S.

In the present embodiment, the spacer 13S is formed in self-alignment by performing a dry etching (dry etching) step. Since the dry etching has a much higher downward etching rate than the lateral etching rate, it is ensured that the dielectric material layer on the sidewall surface of the gate stack structure 12 is remained when removing the portion of the dielectric material layer on the top surface of the gate stack structure 12 and the upper surface 11a of the semiconductor layer 11.

Accordingly, the spacer 13S has a maximum thickness D of in a direction parallel to the width of the gate stack 12, and the maximum thickness D is substantially the same as the thickness of the dielectric material layer 13'. The maximum thickness D of the spacer 13S is between 50 nm and 500 nm in embodiment. As shown in FIG. 2F, the spacer 13S further has a maximum height H of , i.e., the vertical distance between the top of the spacer 13S and the top surface 11a of the semiconductor layer 11. in this embodiment, the maximum height H of the spacer 13S is substantially the same as the height of the gate stack 12.

In addition, the thickness of the spacer 13S in the direction parallel to the width of the gate stack structure 12 decreases from bottom to top, that is, the thickness of the spacer 13S close to the semiconductor layer 11 is greater than the thickness of the spacer 13S far from the semiconductor layer 11, the spacer 13S covers the portion of the source region 112, and the other portion of the source region 112 is exposed on the upper surface 11a of the semiconductor layer 11.

Please refer to step S130 of fig. 1, and fig. 2G-2H, which show a detailed flow of performing the salicidation process with the spacers 13S and the gate stack 12 as masks.

As shown in fig. 2G, a conductive layer 14' is formed to cover the entire upper surface 11a of the semiconductor layer 11, the spacer 13S and the gate stack 12. The material of the conductive layer 14' may be tungsten, titanium, cobalt, tantalum, nickel, palladium, or any combination thereof.

Next, as shown in FIG. 2H, a heat treatment is performed on the conductive layer to promote a portion of the conductive layer 14 ' to react with the semiconductor layer 11 to form a silicide layer 14. a portion of the conductive layer 14 ' covers the gate stack 12 and the spacers 13S and reacts, therefore, the unreacted conductive layer 14 ' is removed in a subsequent step.

It should be noted that in the embodiment, the gate electrode 121 is heavily doped polysilicon, if the conductive layer 14' directly contacts the gate electrode 121 and performs a silicidation reaction with the gate electrode 121 during the thermal process, the high temperature of the thermal process may cause the gate electrode 121 to melt and deform.

Therefore, in the present embodiment, the conductive layer 14' covering the gate stack 12 is isolated from the gate 121 by the shielding layer 122. Thus, the shielding layer 122 can protect the gate electrode 121 during the thermal process to prevent the conductive layer 14' and the gate electrode 121 from silicidation.

Next, please refer to step S140 of fig. 1, fig. 3A to 3D and fig. 4A to 4C, which illustrate a detailed process for forming an interconnect structure on the semiconductor layer 11.

Referring to fig. 3A, an interlayer dielectric material layer 15 'is formed to entirely cover the silicide layer 14, the spacer 13S and the gate stack 12. the material of the interlayer dielectric material layer 15' may be selected from borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), oxide, nitride or a combination thereof.

Next, please refer to and fig. 3B-3D, fig. 3B is a partial top view of the semiconductor power device according to the embodiment of the present invention in step S140, fig. 3C is a partial cross-sectional view of the semiconductor power device of fig. 3B along line IIIC-IIIC, and fig. 3D is a partial cross-sectional view of the semiconductor power device of fig. 3B along line IIID-IIID.

It is noted that, as mentioned above, the semiconductor layer 11 is defined as an element region AR and a termination region TR, and the gate stack structure 12 has an portion 12A located in the element region AR and a second portion 12B located in the termination region TR, as shown in fig. 3B.

In fig. 3B, the interlayer dielectric material layer 15 'is patterned to form an interlayer dielectric layer 15 having at least source contact openings 15S and at least gate contact openings 15G in the embodiment, the gate contact openings 15G and the source contact openings 15S are defined during the step of patterning the interlayer dielectric material layer 15'.

In addition, in the present embodiment, the gate contact opening 15G corresponds to the second portion 12B of the gate stack structure 12, and thus the gate contact opening 15G is located in the termination region TR. In other embodiments, the gate contact opening 15G may also be located in the device region AR.

As shown in fig. 3B and 3C, the source contact opening 15S is located in the device region AR, so that the silicide layer 14 is exposed through the source contact opening 15S. It should be noted that the positions of the source contact opening 15S and the gate contact opening 15G are not limited in the present invention as long as the source region 112 and the gate 121 can be electrically connected to the external control circuit.

In addition, as shown in FIGS. 3B and 3D, after the step of patterning the interlayer dielectric material layer 15', the method of manufacturing the semiconductor device further includes removing a portion of the shielding layer 122 through the gate contact opening 15G to expose the gate 121. that is, the shielding layer 122 has a extending opening 122H in communication with the gate contact opening 15G.

Referring to fig. 4A to 4C, fig. 4A is a partial top view of a semiconductor power device according to an embodiment of the present invention, fig. 4B is a partial cross-sectional view of the semiconductor power device of fig. 4A taken along line IVB-IVB, and fig. 4C is a partial cross-sectional view of the semiconductor power device of fig. 4A taken along line IVC-IVC.

As shown in fig. 4A, a source conductive layer 16 and a gate conductive layer 17 are formed on the semiconductor layer 11 to be electrically connected to the source region 112 and the gate electrode 121, respectively. The source conductive layer 16 and the gate conductive layer 17 may be completed in the same process. In addition, the gate conductive layer 17 and the source conductive layer 16 are provided apart from each other.

As shown in fig. 4A and 4B, the source conductive layer 16 is formed in the device region AR and fills the source contact opening 15S to electrically connect to the source region 112, and , the source conductive layer 16 is electrically connected to the source region 112 through the silicide layer 14, and as shown in fig. 4C, the gate conductive layer 17 is located in the gate contact opening 15G and the extension opening 122H to electrically connect to the gate 121.

It is noted that in the present embodiment, the interlayer dielectric layer 15 covers the silicide layer 14. further , the silicide layer 14 extends from under the source conductive layer 16 to under the interlayer dielectric layer 15 in the direction of the gate stack 12 until contacting the spacer 13S.

Since the resistance value of the silicide layer 14 will generally be lower than the resistance value of the source region 112 itself, the farther the horizontal distance between the silicide layer 14 and the channel region 113, the greater the on-resistance of the semiconductor power element M1. Therefore, in the present embodiment, the shortest distance between the silicide layer 14 and the channel region 113 is correlated with the maximum thickness D of the spacer 13S.

It should be noted that, in the prior art, when fabricating the interconnection of the semiconductor power device, the dielectric layer is usually formed first, then the dielectric layer is etched to define a plurality of contact windows corresponding to the source region and the gate electrode, and then silicide layers (silicide) are formed on the source region and the gate electrode respectively by the salicide process.

In contrast, the present invention forms the interconnect structure after the silicide layer 14 is formed by spacer definition directly before the salicidation process is performed, so that the shortest distance between the silicide layer 14 and the channel region 113 can be reduced to 100-200 nm, thereby further reducing the on-resistance of the semiconductor power device M1 and reducing the conduction loss.

Based on the above, as shown in fig. 4A to 4C, the embodiment of the invention further provides a semiconductor power device M1, which includes a substrate 10, a semiconductor layer 11, a gate stack structure 12, a spacer 13S, a silicide layer 14, and an interconnect structure.

The semiconductor layer 11 is disposed on the substrate 10, and the semiconductor layer 11 at least has body regions 111 and source regions 112 located in the body regions 111. the source regions 112 are connected to the upper surface 11a of the semiconductor layer 11, and a channel region 113 is defined between the edge of the source regions 112 and the edge of the body regions 111. the semiconductor layer 11 is defined as device regions AR and termination region TR.

The gate stack 12 is disposed on the semiconductor layer 11, and the gate stack 12 vertically overlaps the channel region 113 at . as mentioned above, the gate stack 12 includes the gate insulating layer 120, the gate 121, and the shielding layer 122 covering the gate 121. in addition, the gate stack has a th portion a in the device region AR and a second portion 12B in the termination region TR.

The spacer 13S is disposed on the semiconductor layer 11 and covers the sidewall surface of the gate stack 12. the spacer 13S has a maximum thickness of nm in a direction parallel to the width of the gate stack 12, and the maximum thickness is between 50 nm and 500 nm.

The silicide layer 14 contacts the source regions 112 and the shortest distance between the silicide layer 14 and the channel region 113 is between 100 and 200 nanometers.

The interconnect structure includes an interlayer dielectric layer 15, a source conductive layer 16 and a gate conductive layer 17. The interlayer dielectric layer 15 has a source contact opening 15S and a gate contact opening 15G, wherein the gate contact opening 15G corresponds to the second portion 12B of the gate stack structure 12.

The source conductive layer 16 is disposed on the interlayer dielectric layer 15 and contacts the silicide layer 14 through the source contact opening 15S to electrically connect to the source region 112. In the present embodiment, the silicide layer 14 extends from below the source conductive layer 16 to below the interlayer dielectric layer 15 in the direction of the gate stack 12. That is, the interlayer dielectric layer 15 and the source conductive layer 16 are vertically overlapped with the silicide layer 14, and the silicide layer 14 is not formed under the spacer 13S.

The gate conductive layer 17 is also disposed on the interlayer dielectric layer 15 and electrically connected to the gate electrode 121 through the gate contact opening 15G and the extension opening 122H of the shielding layer 122. In this embodiment, the gate conductive layer 17 is located in the termination region TR and is spaced apart from the source conductive layer 16.

In summary, the semiconductor power device and the method for manufacturing the same according to the present invention have the advantages that the shortest distance between the silicide layer 14 and the channel region 113 can be reduced by the technical means of forming the spacer 13S covering the sidewall of the gate stack structure 12 before forming the interconnect structure and performing the salicide process, since the resistance of the silicide layer 14 is usually lower than the resistance of the source region 112, the distance between the silicide layer 14 and the channel region 113 is reduced, and the on-resistance of the semiconductor power device M1 can be further reduced by .

In addition, in the semiconductor power device according to the embodiment of the invention, the gate electrode 121 may be blocked from the conductive layer 14' formed in the salicide process by the shielding layer 122, so as to prevent the gate electrode 121 from being melted or deformed due to the high temperature of the thermal process and the silicidation reaction.

The disclosure is only a preferred embodiment of the invention, and is not intended to limit the scope of the claims, so that all technical equivalents and modifications using the contents of the specification and drawings are included in the scope of the claims.

Claims

A method for manufacturing a semiconductor power device of , comprising:

forming a semiconductor layer on a substrate, wherein the semiconductor layer has at least a body region and a source region located in the body region, the source region is connected to the upper surface of of the semiconductor layer, and a channel region is defined between the source region and the body region;

forming a gate stack structure on the semiconductor layer and overlapping the channel region in the vertical direction;

forming at least spacers to cover sidewall surfaces of the gate stack structure, wherein the spacers cover portions of the source regions and another portions of the source regions are exposed at the upper surface;

performing salicide process with the spacer and the gate stack structure as a mask to form a silicide layer contacting the source region, and

forming an interconnect structure on the semiconductor layer, wherein the interconnect structure comprises interlayer dielectric layer and source conductive layer electrically connected to the source region;

wherein the silicide layer extends from below the source conductive layer to below the interlayer dielectric layer in a direction of the gate stack structure.
2. The method of claim 1, wherein the step of forming the gate stack further comprises the steps of:

sequentially forming a gate insulating material layer, an initial gate layer and an initial shield layer on the upper surface of the semiconductor layer to form an initial gate stack structure, and

patterning the initial gate stack structure to form the gate stack structure, wherein the gate stack structure locally exposes the source region.
3. The method of claim 1, wherein the gate stack structure comprises gate insulation layer, gate, and shield layer covering the gate.
4. The method of claim 3, wherein the step of forming the interconnect structure comprises:

forming an interlayer dielectric material layer to completely cover the silicide layer, the spacer and the gate stack structure;

patterning the layer of interlayer dielectric material to form the interlayer dielectric layer having at least source contact openings through which the silicide layer is exposed, and

a source conductive layer is formed within the source contact opening to electrically connect the source region by contacting the silicide layer.
5. The method of claim 4, wherein the interlayer dielectric layer further has gate contact openings, the gate contact openings and the source contact openings are formed during the step of patterning the interlayer dielectric material layer, and the step of forming the interconnect structure further includes:

removing a portion of the shield layer through the gate contact opening to expose the gate after the step of patterning the layer of interlayer dielectric material, and

forming a gate conductive layer in the gate contact opening to electrically connect the gate conductive layer to the gate, wherein the gate conductive layer and the source conductive layer are spaced apart from each other.
6. The method of claim 5, wherein the semiconductor layer is defined element region and termination region, the gate stack structure has a th portion located in the element region and a second portion located in the termination region, and the gate contact opening corresponds to the second portion.
7. The method of manufacturing a semiconductor power element according to claim 1, wherein the step of forming the spacer includes:

forming a layer of dielectric material covering the upper surface of the semiconductor layer and the gate stack structure, and

an etch step is performed to remove a portion of the layer of dielectric material overlying the gate stack structure and on the upper surface to form the spacers.
8. The method of claim 1, wherein a thickness of the spacer in a direction parallel to a width direction of of the gate stack structure decreases from bottom to top.
9. The method of claim 1, wherein the salicidation process comprises:

forming a conductive layer to completely cover the upper surface of the semiconductor layer, the spacer and the gate stack structure;

performing a heat treatment on the conductive layer to promote a reaction between a portion of the conductive layer and the semiconductor layer to form the silicide layer, and

and removing the unreacted conductive layer.
10, kinds of semiconductor power element, characterized in that, the semiconductor power element includes:

a substrate;

semiconductor layer disposed on the substrate, wherein the semiconductor layer has at least body region and source region located in the body region, the source region is connected to upper surface of the semiconductor layer, and channel region is defined between edge of the source region and edge of the body region;

a gate stack structure disposed on the upper surface of the semiconductor layer, wherein the gate stack structure overlaps the channel region in a vertical direction;

spacers disposed on the semiconductor layer and covering sidewall surfaces of the gate stack structure, wherein the spacers cover portions of the source regions;

a silicide layer contacting the source region, and

interconnect structure including a interlayer dielectric layer having at least source contact openings and a source conductive layer disposed on the interlayer dielectric layer and contacting the silicide layer through the source contact openings to electrically connect to the source regions;

wherein the silicide layer extends from below the source conductive layer to below the interlayer dielectric layer in a direction of the gate stack structure.
11. The semiconductor power device of claim 10, wherein the gate stack structure comprises gate insulation layers, gate electrodes, and shield layers overlying the gate electrodes.
12. The semiconductor power device of claim 11 wherein the semiconductor layer defines a cell region and a termination region, the gate stack structure has a th portion within the cell region and a second portion within the termination region, and the interlayer dielectric layer further has a gate contact opening corresponding to the second portion.
13. The semiconductor power device of claim 12, wherein said shield layer of said second portion has an extension opening in communication with said gate contact opening, and said interconnect structure further comprises a gate conductive layer disposed in said termination region and electrically connected to said gate through said gate contact opening and said extension opening.
14. The semiconductor power device of claim 10, wherein the thickness of the spacer portion decreases from bottom to top in a direction parallel to the width direction of the gate stack structure.