CN110739023A - Method for detecting storage state of solid-state storage device - Google Patents
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Abstract
The invention provides methods for detecting storage states of a solid state memory device, the method comprises applying a plurality of sensing voltages to each memory cell, comparing the threshold voltage of each memory cell with the plurality of sensing voltages to define a storage state, the plurality of storage states being classified according to whether the memory cell falls in a strong correct region, a weak correct region, a strong error region or a weak error region, calculating the number of memory cells in each storage state, calculating the number of memory cells in the strong correct region, which is the strong correct ratio of the number of memory cells in the sum of the strong correct region and the weak correct region, calculating the number of memory cells in the strong error region, which is the strong error ratio of the number of memory cells in the sum of the strong error region and the weak error region, and generating a logarithmic probability ratio based on the strong correct ratio and the strong error ratio.
Description
Technical Field
The present invention relates to solid-state memory devices, and more particularly, to methods for detecting storage states of solid-state memory devices.
Background
Now, memory applications are becoming more popular, and internal damage of the memory is caused by factors such as the erase and write times during the use process, so that the error rate is increased, and the reliability of the non-volatile memory (non-volatile memory) is drastically reduced, so that the reliability of the non-volatile memory can be improved by a reliability design technique, particularly an error correction technique, and the product can be made more durable and stable.
Conventionally, BCH is adopted as mainstream error correction coding, the calculation speed of the coding is relatively high, and the correction capability is stronger as the redundant bits are more, but as the manufacturing technology of the non-volatile memory is higher and higher, the BCH coding technology cannot provide enough correction capability, so that the LDPC error correction technology widely applied in the communication field is turned to, and the LDPC error correction technology becomes a new trend in the storage field by virtue of the strong correction capability.
Disclosure of Invention
An object of the present invention is to provide methods for detecting storage states of a solid-state storage device, which have steps of improving error correction capability of stored data of a non-volatile memory.
The embodiment of the invention provides methods for detecting storage states of a solid state storage device, wherein the solid state storage device comprises a plurality of memory cells, the method comprises the steps of applying a plurality of sensing voltages with different voltage values to each memory cell, comparing the threshold voltage of each memory cell with the plurality of sensing voltages, defining a plurality of storage states according to the sensing voltages, calculating the number of the plurality of memory cells in each region of a strong correct region, a weak correct region, a strong error region and a weak error region according to the read memory cells, calculating the number of the plurality of memory cells in the strong correct region, the weak correct region, the strong error region and the weak error region, calculating the number of the plurality of memory cells in the strong correct region, the strong correct ratio of the number of the plurality of memory cells in the sum of the strong correct region and the weak correct region, calculating the number of the plurality of memory cells in the strong error region, the strong error ratio of the plurality of memory cells in the sum of the strong error region and the weak error region, and generating a probability error ratio based on the strong error ratio and the probability ratio.
Preferably, a difference between the lower bit sensing voltage and the middle bit sensing voltage is the same as a difference between the upper bit sensing voltage and the middle bit sensing voltage.
Preferably, the method for detecting the storage state of the solid-state storage device further comprises the following steps, which are applied to the memory cell originally having the bit value of logic 1: applying the middle sensing voltage to each memory cell; comparing whether the threshold voltage of each memory unit is smaller than the median sensing voltage, if so, judging that the memory unit is logic 1, and if not, judging that the memory unit is logic 0; applying the low sensing voltage to each of the memory cells; comparing whether the critical voltage of each memory unit is smaller than the low-level sensing voltage, if so, judging that the memory unit is logic 1, and if not, judging that the memory unit is logic 0; applying the high sensing voltage to each of the memory cells; comparing whether the threshold voltage of each memory unit is smaller than the high-level sensing voltage, if so, judging that the memory unit is logic 1, and if not, judging that the memory unit is logic 0; defining the memory cell with the critical voltage smaller than the low sensing voltage to belong to the strong correct region; defining the memory cell with the threshold voltage larger than the low bit sensing voltage and smaller than the middle bit sensing voltage to belong to the weak correct region; defining the memory cell with the threshold voltage larger than the middle sensing voltage and smaller than the high sensing voltage to belong to the weak error region; and defining the memory cell with the critical voltage larger than the high sensing voltage to belong to the strong error region.
Preferably, the method for detecting the storage state of the solid-state storage device further comprises the following steps, which are applied to the memory unit originally having the bit value of logic 0: applying the middle sensing voltage to each memory cell; comparing whether the threshold voltage of each memory unit is greater than the median sensing voltage, if so, judging that the memory unit is logic 0, and if not, judging that the memory unit is logic 1; applying the high sensing voltage to each of the memory cells; comparing whether the critical voltage of each memory unit is larger than the high-level sensing voltage, if so, judging that the memory unit is logic 0, and if not, judging that the memory unit is logic 1; applying the high sensing voltage to each of the memory cells; comparing whether the threshold voltage of each memory unit is larger than the low-level sensing voltage, if so, judging that the memory unit is logic 0, and if not, judging that the memory unit is logic 1; defining the memory cell with the critical voltage larger than the high sensing voltage to belong to the strong correct region; defining the memory cell with the threshold voltage larger than the middle sensing voltage and smaller than the high sensing voltage to belong to the weak correct region; defining the memory cell with the threshold voltage larger than the low bit sensing voltage and smaller than the middle bit sensing voltage to belong to the weak error region; and defining the memory cell with the critical voltage smaller than the low sensing voltage to belong to the strong error region.
Preferably, the method for detecting the storage state of the solid-state storage device further comprises the following steps: adjusting voltage values of the lower sensing voltage and the upper sensing voltage applied to the plurality of memory cells to adjust the log probability ratio.
Preferably, the method for detecting the storage state of the solid-state storage device further comprises the following steps: the sensing voltages applied to the memory cells are determined based on the desired amount of area of the memory states.
Preferably, the method for detecting the storage state of the solid-state storage device further comprises the following steps: obtaining the bit quantity which can be stored by each memory unit; and determining the sensing voltages applied to the memory cells based on the amount of bits that the memory cells can store.
Preferably, the method for detecting the storage state of the solid-state storage device further comprises the steps of inputting or more bit values stored in each memory cell into a decoder, decoding or more bit values of each memory cell by using the decoder, and judging whether the or more bit values of each memory cell can be successfully decoded by the decoder, if so, judging that the or more bit values stored in the memory cells are correct, and if not, judging that the or more bit values stored in the memory cells are wrong.
Preferably, the method of detecting the storage state of the solid-state storage device further comprises the steps of inputting the log probability ratio to the decoder, and decoding or more bit values with the decoder by a decoding program comprising the corresponding log probability ratio.
As described above, the present invention provides a method for detecting the storage state of a solid-state memory device, which defines the storage state of the memory cells of a non-volatile memory by applying N sensing voltages and dividing a strong correct region, a weak correct region, a strong error region, a weak error region, etc., and calculates the number of memory cells per regions under different threshold voltages, and accordingly calculates a logarithmic probability ratio as an input of a decoder, so that the decoder can decode data bit values with different logarithmic probability ratios for different storage states, thereby improving the probability of obtaining correct data bit values.
Drawings
FIG. 1 is a flowchart illustrating steps of a method for detecting storage status of a solid-state storage device according to an embodiment of the present invention.
FIG. 2a is a flowchart illustrating a step of applying a sensing voltage to determine a bit value of a memory cell in a method for detecting a storage state of a solid-state memory device according to a second embodiment of the present invention.
FIG. 2b is a flowchart of the steps of calculating the contrast probability ratio of the method for detecting the storage status of the solid-state storage device according to the second embodiment of the present invention.
FIG. 3a is a flowchart illustrating a step of applying a sensing voltage to determine a bit value of a memory cell in a method for detecting a storage state of a solid-state memory device according to a third embodiment of the present invention.
FIG. 3b is a flowchart of the steps of calculating the contrast probability ratio of the method for detecting the storage status of the solid-state storage device according to the third embodiment of the present invention.
FIG. 4 is a flowchart illustrating a method for detecting a storage status of a solid-state memory device according to a fourth embodiment of the present invention, wherein the method comprises decoding a bit stored in a memory cell by a decoder.
FIG. 5 is a flowchart illustrating a method for detecting a storage state of a solid-state memory device according to a fifth embodiment of the present invention, in which a decoder decodes a memory cell with a probability decoding algorithm corresponding to a log probability ratio.
FIG. 6 is a graph of the number of SLC memory cells versus the threshold voltage for a solid state storage device of the present invention with applied sensing voltage.
FIG. 7 is a graph of the number of TLC memory cells of a solid-state storage device of the present invention applying a sensing voltage versus a threshold voltage.
FIG. 8 is a three-dimensional schematic diagram of the achievable log probability ratio of a specific scale interval of the present invention analyzed by clustering.
Detailed Description
Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown , however, the inventive concept may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein.
Referring to fig. 1, which is a flowchart illustrating steps of a method for detecting a storage state of a solid-state storage device according to an embodiment of the present invention, the method for detecting a storage state of a solid-state storage device according to the embodiment of the present invention may include the following steps S101 to S111, which are applicable to a solid-state storage device, wherein the solid-state storage device may include a memory, such as a NAND Flash nonvolatile memory, and the nonvolatile memory may have a memory array formed by arranging a plurality of memory cells or memory cells (cells), each memory Cell may be configured to store N bits, where N is an integer value greater than or equal to 1.
Step S101: a plurality of sensing voltages, which may have different voltage values, are applied to the respective memory cells. The multiple sensing voltages may be applied sequentially or simultaneously. The application sequence of the plurality of sensing voltages can be applied sequentially according to the magnitude of the voltage values, for example; or first applying the middle sensing voltage, and then sequentially applying the middle sensing voltage and the middle sensing voltage according to the difference value between the other sensing voltages and the middle sensing voltage from small to large or from large to small.
For example, three sensing voltages can be applied, including, but not limited to, a low sensing voltage, a middle sensing voltage, and a high sensing voltage.A method of detecting a memory state of a solid state memory device according to embodiments of the present invention can further include obtaining the middle sensing voltage, and setting the low sensing voltage and the high sensing voltage based on, for example, the middle sensing voltage value.As turning to the graph of FIG. 6, the middle sensing voltage Vt1, the low sensing voltage Vt2, and the high sensing voltage Vt 3. it should be understood that the low sensing voltage value in this embodiment means less than the middle sensing voltage, the high sensing voltage means greater than the middle sensing voltage, and the terms "low" and "high" of the two sensing voltages are used only to indicate a relationship with the "middle" sensing voltage, and are not limited to sensing voltages less than, greater than, or equal to specific voltage values, nor specific voltage range values.
When the power supply or other voltage supply device supplies the sensing voltage to the memory array, the time point of receiving the sensing voltage may be earlier for the memory cell disposed closer to the power supply than for the memory cell disposed farther from the power supply, for example, after the sensing voltage having the same voltage value is supplied to all the memory cells, another sensing voltage having a different voltage value is supplied to all the memory cells, and the different sensing voltage values are sequentially applied to all the memory cells.
Step S103: comparing the Threshold voltage (Threshold voltage) of each memory cell with a plurality of sensing voltages, and defining a plurality of storage states according to the sensing voltages falling at different levels, wherein the plurality of storage states at least include a Strong Correct (SC), a Weak Correct (WC), a Strong Error (SE), and a Weak Error (WE), or more states. In detail, each memory cell may be a memory cell having a floating gate transistor (floating gate transistor) or a charge trap (charge trap), such as: the floating gate transistor can be used for storing hot carriers, and the magnitude of the threshold voltage value of the floating gate transistor can be determined according to the quantity of the stored hot carriers. Therefore, it should be understood that the threshold voltage of the memory cell is a variable value, and the sensing voltage value to be applied to each memory cell can be determined according to different threshold voltage values.
The method for detecting the storage state of the solid-state memory device according to the embodiment of the invention may further include obtaining the amount of bits that each memory cell can store, determining the number and value of the sensing voltages applied to the memory cells based on the amount of bits that the memory cells can store, and/or determining the number and value of the sensing voltages applied to the memory cells based on the amount of regions of the storage states to be defined.
Step S105, calculating the number of memory cells in each memory state includes calculating the area of each region of the strong correct region, the weak correct region, the strong error region, and the weak error region, the area of each region will vary with the threshold voltage of the memory cell and the sensing voltage applied to the memory cell.
Step S107, calculating Strong Correct Ratio (SCR) of the number of multiple memory units in the Strong correct area and the number of multiple memory units in the weak correct area, and the following formula is expressed as:
the SCR represents a strong and correct ratio, which may be between 0.0% and 100%, for example, the SCR is 90%, which is only illustrated and not limited herein. SC represents the number of memory cells in the strong correct region, and WC represents the number of memory cells in the weak correct region.
Step S109: calculating the number of multiple memory units of the Strong Error region, and the Strong Error Ratio (SER) of the number of multiple memory units occupying the sum of the Strong Error region and the weak Error region. Expressed by the following calculation:
wherein SER represents a strong error ratio, which may be between 0.0% and 100%, for example SER ═ 10%, which is merely illustrated and not limited herein. SE indicates the number of memory cells in the strong error region, and WE indicates the number of memory cells in the weak error region.
Step S111: log-likeliodoratio (LLR) is generated based on the strong correct proportion and the strong error proportion.
Referring to fig. 2a and 2b, fig. 2a is a flowchart illustrating a step of determining a bit value of a memory cell by applying a sensing voltage according to a method for detecting a storage state of a solid-state memory device according to a second embodiment of the present invention; FIG. 2b is a flowchart of the steps of calculating the log probability ratio of the method for detecting the storage status of the solid-state storage device according to the second embodiment of the present invention. The method for detecting the storage status of the solid-state storage device of the present embodiment may include steps S201 to S223 shown in fig. 2a and steps S225 to S239 shown in fig. 2b, which are applied to the memory cell having the bit value of logic 1.
First, as shown in fig. 2a, steps S201 to S223 are as follows.
Step S201: a middle sense voltage, such as the middle sense voltage Vt1 shown in FIG. 6, is obtained, and then the middle sense voltage is applied to the memory cell. In this embodiment, it is assumed that the median sensing voltage is a factory value. However, in practice, as the nonvolatile memory is used for a longer time, the distance between the two curves representing logic 1 and logic 0 shown in FIG. 6 may be changed, and a more appropriate middle sensing voltage may be obtained/set again.
Step S203: comparing whether the threshold voltage of the memory cell is less than the middle sensing voltage.
If so, i.e. if the threshold voltage of the memory cell is less than the middle sensing voltage, go to step S205: the judgment bit value is logic 1.
If not, i.e. if the threshold voltage of the memory cell is greater than the middle sensing voltage, go to step S207: the bit value is determined to be logic 0.
Step S209: the lower sensing voltage, Vt2 in FIG. 6, may be set based on the middle sensing voltage, and then applied to the memory cell.
Step S211: comparing whether the threshold voltage of the memory cell is less than the low-level sensing voltage.
If so, i.e., if the threshold voltage of the memory cell is less than the lower sensing voltage, go to step S213: the judgment bit value is logic 1.
If not, i.e. if the threshold voltage of the memory cell is greater than the low sensing voltage, go to step S215: the bit value is determined to be logic 0.
Step S217: the high sensing voltage may be set based on the middle sensing voltage and the low sensing voltage, such as the high sensing voltage Vt3 shown in FIG. 6, and then applied to the memory cell. For example, the difference between the lower sensing voltage and the middle sensing voltage may be the same as the difference between the upper sensing voltage and the middle sensing voltage, but not limited thereto.
Step S219: comparing whether the threshold voltage of the memory cell is smaller than the high-level sensing voltage.
If so, i.e., if the threshold voltage of the memory cell is less than the high sensing voltage, go to step S221: the judgment bit value is logic 1.
If not, i.e. if the threshold voltage of the memory cell is greater than the high sensing voltage, go to step S223: the bit value is determined to be logic 0.
After steps S201 to S223, the sensing voltages are applied in sequence and compared with the threshold voltage of the memory cell, and steps S225 to S239 shown in FIG. 2b define the memory state of the memory cell, as described below.
Step S225: memory cells with threshold voltages less than the lower sensing voltage are defined as strong correct regions. Specifically, as shown in the graph of FIG. 6 representing a bit value of logic 1, the threshold voltage of the memory cell is lower than the low sensing voltage Vt2, and the bit value is determined to be logic 1, which is defined as the strong error region SC 1.
Step S227: defining the memory cell with the critical voltage larger than the low bit sensing voltage and smaller than the middle bit sensing voltage as the weak correct region. Specifically, as shown in FIG. 6, for a curve representing a bit value of logic 1, the threshold voltage of the memory cell is greater than the low level Vt2 and less than the middle level Vt1, i.e., the threshold voltage falls between the low level Vt2 and the middle level Vt1, and the bit value is determined to be logic 1, which is defined as the weak-correct region WC 1.
Step S229: defining the memory cell with the critical voltage larger than the middle sensing voltage and smaller than the high sensing voltage as the weak error region. As shown in FIG. 6, representing a curve with a bit value of logic 1, the threshold voltage of the memory cell is greater than the middle sensing voltage Vt1 and less than the high sensing voltage Vt3, i.e., the threshold voltage falls between the middle sensing voltage Vt1 and the high sensing voltage Vt3, and the bit value is determined to be logic 0, which is defined as the weak error field WE 1.
Step S231: the memory cell with the critical voltage larger than the high sensing voltage is defined as a strong error region. As shown in FIG. 6, representing the curve with the bit value of logic 1, the threshold voltage of the memory cell is higher than the high sensing voltage Vt3, and the bit value is determined to be logic 0, which is defined as the strong error region SE 1.
In step S233, the number of memory cells per memory states is counted, and the area of each region such as the strong error region SC1, the weak error region WC1, the weak error region WE1 and the strong error region SE1 of FIG. 6 is counted.
Step S235: the number of multiple memory units in the strong correct region is calculated, and the strong correct proportion of the number of multiple memory units in the sum of the strong correct region and the weak correct region is calculated. Specifically, the area of the strong correct region SC1 and the area of the weak correct region WC1 corresponding to the data bit value of logic 1 shown in fig. 6 are calculated respectively, and the ratio of the area of the strong correct region SC1 to the total area of the strong correct region SC1 and the weak correct region WC1 is calculated accordingly.
Step S237: calculating the number of the memory cells in the strong error region, and the strong error ratio of the number of the memory cells occupying the sum of the strong error region and the weak error region. Specifically, the area of the strong error region SE1 corresponding to the data bit value of logic 1 shown in fig. 6 is calculated as a ratio of the total area of the strong error region SE1 and the weak correct region WE 1.
Step 239: a log probability ratio is generated based on the strong correct ratio and the strong error ratio.
Referring to fig. 3a and 3b, fig. 3a is a flowchart illustrating a step of determining a bit value of a memory cell by applying a sensing voltage according to a method for detecting a storage state of a solid-state memory device according to a third embodiment of the present invention; FIG. 3b is a flowchart of the steps of calculating the log probability ratio of the method for detecting the storage status of the solid-state storage device according to the third embodiment of the present invention. As shown in FIG. 3a, the method for detecting the storage status of the solid-state storage device of the present embodiment may include steps S301 to S323 shown in FIG. 3a and steps S325 to S339 shown in FIG. 3b, which are applicable to the memory cell originally having a bit value of logic 0. It is assumed hereinafter that a sensing voltage applied to a memory cell of a solid-state storage device is not equal to a threshold voltage of the memory cell.
First, as shown in fig. 3a, steps S301 to S323 are as follows.
Step S301: a middle sense voltage, such as the middle sense voltage Vt1 shown in FIG. 6, is obtained, and then the middle sense voltage is applied to the memory cell.
Step S303: comparing whether the threshold voltage of the memory cell is greater than the middle sensing voltage.
If so, i.e. if the threshold voltage of the memory cell is greater than the middle sensing voltage, go to step S305: the bit value is determined to be logic 0.
If not, i.e. if the threshold voltage of the memory cell is less than the middle sensing voltage, go to step S307: the judgment bit value is logic 1.
Step S309: the high bit sensing voltage, Vt3 as shown in FIG. 6, is set and then applied to the memory cell.
Step S311: comparing whether the threshold voltage of the memory cell is larger than the high-level sensing voltage.
If so, i.e. if the threshold voltage of the memory cell is greater than the high sensing voltage, go to step S313: the bit value is determined to be logic 0.
If not, i.e. if the threshold voltage of the memory cell is less than the high sensing voltage, go to step S315: the judgment bit value is logic 1.
Step S317: the lower sensing voltage, Vt3 as shown in FIG. 6, is set and then applied to the memory cell.
Step S319: comparing whether the threshold voltage of the memory cell is larger than the low-level sensing voltage.
If so, i.e., if the threshold voltage of the memory cell is greater than the lower sensing voltage, go to step S321: the bit value is determined to be logic 0.
If not, i.e. if the threshold voltage of the memory cell is less than the low sensing voltage, go to step S323: the judgment bit value is logic 1.
After steps S301-S323, the sensing voltages are applied in sequence and compared with the threshold voltage of the memory cell, and then the memory state of the memory cell is defined, as shown in steps S325-S339 shown in FIG. 3b, which is described below.
Step S325: memory cells with threshold voltages greater than the high sensing voltage are defined as strong correct regions. As shown in FIG. 6, representing the curve with the bit value being logic 0, the threshold voltage of the memory cell is higher than the high sensing voltage Vt3, and the bit value is determined to be logic 0, which is defined as the strong error region SC 0.
Step S327: defining the memory cell with the critical voltage larger than the middle sensing voltage and smaller than the high sensing voltage as the weak correct region. As shown in FIG. 6, representing a curve with a bit value of logic 0, the threshold voltage of the memory cell is greater than the middle sensing voltage Vt1 and less than the high sensing voltage Vt3, i.e., the threshold voltage falls between the middle sensing voltage Vt1 and the high sensing voltage Vt3, and the bit value is determined to be logic 0, which is defined as a weak positive region WC 0.
Step S329: defining the memory cell with the critical voltage larger than the low level sensing voltage and smaller than the middle level sensing voltage as the weak error region. As shown in FIG. 6, representing a curve with a bit value of logic 0, the threshold voltage of the memory cell is greater than the lower sensing voltage Vt2 and less than the middle sensing voltage Vt1, i.e., the threshold voltage falls between the lower sensing voltage Vt2 and the middle sensing voltage Vt1, and the bit value is determined to be logic 1, which is defined as the weak error field WE 0.
Step S331: the memory cells with threshold voltage smaller than the low sensing voltage are defined as strong error regions. As shown in FIG. 6, representing the curve with the bit value being logic 0, the threshold voltage of the memory cell is lower than the low sensing voltage Vt2, and the bit value is determined to be logic 1, which is defined as the strong error region SE 0.
In step S333, the number of memory cells per memory state is counted, and the area of each region such as the strong error region SC0, the weak error region WC0, the weak error region WE0 and the strong error region SE0 of FIG. 6 is counted.
Step S335: the number of multiple memory units in the strong correct region is calculated, and the strong correct proportion of the number of multiple memory units in the sum of the strong correct region and the weak correct region is calculated. Specifically, the area of the strong correct region SC0 and the area of the weak correct region WC0 corresponding to the data bit value of logic 0 shown in fig. 6 are calculated, respectively, and the ratio of the area of the strong correct region SC0 to the total area of the strong correct region SC0 and the weak correct region WC0 is calculated.
Step S337: calculating the number of the memory cells in the strong error region, and the strong error ratio of the number of the memory cells occupying the sum of the strong error region and the weak error region. The data bit value shown in fig. 6 is calculated as the ratio of the area of the strong error region SE0 corresponding to logic 0 to the total area of the strong error region SE0 and the weak error region WE 0.
Step S339: a log probability ratio is generated based on the strong correct ratio and the strong error ratio.
Please refer to fig. 4, which is a flowchart illustrating a procedure of decoding bits stored in memory cells by a decoder according to a fourth embodiment of the present invention. As shown in fig. 4, the method for detecting the storage status of the solid-state storage device in the present embodiment includes the following steps S401 to S409.
Step S401: the bit value stored in the memory cell is input to the decoder.
Step S403: the decoder is used to decode the bit value of the memory cell.
Step S405: whether the decoder can successfully decode the bit value of the memory unit is judged, and whether the memory unit wrongly judges the bit value as logic 1 as 0 or judges the logic 0 as 1 during access is judged according to the judgment.
If the decoder successfully decodes the bit value of the memory cell, step S407: the bit value of the data stored in the memory cell is determined to be correct.
If the decoder fails to decode the bit value of the memory cell, step S409: the bit value error of the data stored in the memory cell is determined.
The method of this embodiment may further comprise steps of after testing the memory cells of the volatile memory of the solid state memory device repeatedly through S401-S409, evaluating whether the probability of the memory cells storing data is correct is higher than the correct probability threshold range, if so, classifying the memory cells into a strong correct region, counting the number of memory cells belonging to the strong correct region, if not, classifying the memory cells into a weak correct region, counting the number of memory cells belonging to the weak correct region, evaluating whether the probability of data errors is higher than the error probability threshold range, if so, classifying the memory cells into a strong error region, counting the number of memory cells belonging to the strong error region, if not, classifying the memory cells into a weak error region, counting the number of memory cells belonging to the weak error region, further steps of comparing the strong correct region, the weak correct region, the strong error region, and the weak error region divided by the second and third embodiments, if the test result of applying the sensing voltage matches the actual sensing voltage, and if the classification is correct, further classifying the sensing voltage as the correct sensing voltage.
Please refer to fig. 5, which is a flowchart illustrating a method for detecting a storage status of a solid-state memory device according to a fifth embodiment of the present invention, wherein a decoder decodes a memory cell by a probability decoding algorithm corresponding to log probability ratio. As shown in fig. 5, the method for detecting the storage status of the solid-state storage device according to the present invention includes the following steps S501 to S509.
Step S501: and obtaining a logarithmic probability ratio. For example, the control circuit for a solid-state memory device may generate a log probability ratio using the above steps, and then input the resulting log probability ratio to the decoder.
Step S503: the data bit value stored in the memory cell is input to the decoder.
Step S505: the decoding procedure including the corresponding logarithmic probability ratio is used to soft-decode the data bit value of the memory unit. The log probability ratios are associated with the strong correct region SC, the weak correct region WC, the strong error region SE, and the weak error region WE shown in fig. 6, and different decoding procedures can be selected for different regions. The decoding procedure may employ a probability decoding algorithm, such as algebraic decoding, such as BCH Code, or a probability decoding algorithm, such as Low Density Parity check Code (LDPC), which is only illustrated and not limited thereto.
, decoding the data according to the log-likelihood ratio, and especially decoding the strong error region, the weak error region and the weak error region, wherein the decoder is classified as the strong error region that the data read by the memory unit for many times are all correct, i.e. the correct probability is high, and the decoder decodes the data by using a larger log-likelihood ratio, and conversely, the decoder decodes the data stored by the memory unit of the strong error region by using a smaller log-likelihood ratio, so that the decoder has bit values in probability flip code words, and flips the bit value misjudged as logic 0 to be actual logic 1, or flips the bit value misjudged as logic 1 to be actual logic 0, thereby improving the error correction capability of the decoder, and performing subsequent correction processing on the misjudgment of the memory unit when accessing the bit value.
Step S507, calculating the success rate of decoding the bit value of each memory cell in each areas in the strong correct area, the weak correct area, the strong error area and the weak error area by using the decoder, the method of this embodiment may further include comparing the success rate of decoding the decoding program corresponding to the log probability ratio with the success rate of decoding the decoding program corresponding to the fourth embodiment at a preset fixed code rate, determining whether the success rate of decoding the decoding program corresponding to the log probability ratio is increased, and comparing the increased rate.
Step S509: the sensing voltage is adjusted based on the success rate of the decoder decoding. If the decoded power of the decoder does not meet the requirement, the sensing voltage applied to the memory cell can be adjusted, and the log-probability ratio can be adjusted.
Step S511: and judging and recording the correlation between the sensing voltage and the logarithmic probability ratio.
Referring to fig. 6, a graph of the number of SLC cells of a solid state memory device to which a sensing voltage is applied versus a threshold voltage according to the present invention is illustrated, in which a nonvolatile memory of the solid state memory device includes a plurality of memory cells or memory cells, different kinds of memory cells are distinguished according to the amount of data stored in each memory Cell, and if each memory Cell can store 1 Bit, i.e., Bit (Bit) values having logic 0 and 1, it is referred to as a Single-Level Cell (SLC), that is, the memory Cell mentioned in the embodiment can store N bits of data, and for the memory cells of a three-Level memory Cell, N1, 2N 21 is 2, as shown in the graph of fig. 6, the vertical axis represents the number of Single-Level memory cells, the horizontal axis represents the threshold voltage value of the Single-Level memory Cell, and two curves having a logic 1 Bit value and a logic 0 Bit value are formed according to a variation relationship between the number of the memory cells and the threshold voltage value.
The plurality of sensing voltages, such as the middle sensing voltage Vt1, the low sensing voltage Vt2, and the high sensing voltage Vt3, divide the curve representing logic 1 into a plurality of memory states, including the strong correct region SC1, the weak correct region WC1, the strong error region SE1, and the weak error region WE1, and divide the curve representing logic 0 into the strong correct region SC0, the weak correct region WC0, the strong error region SE0, and the weak error region WE 0.
Ideally, the median sense voltage Vt1 crosses the intersection of the two curves for logic 1 and logic 0. However, the non-ideal state shown in fig. 6 of this embodiment means that the steps described above can also be implemented in the non-ideal state.
If the difference between the low Vt2 and the medium Vt1 is the same as the difference between the medium Vt1 and the high Vt3, the two curves may be divided into two regions of the strong correct region SC1 and the strong correct region SC0, two regions of the weak correct region WC1 and the weak correct region WC0, and the other regions may be the same, which is only illustrated and not limited herein.
strong correct regions SC1 and SC0 represent high data correct rate of the memory cells being evaluated, weak correct regions WC1 and WC0 represent low data correct rate of the memory cells being evaluated, whereas strong error regions SE1 and SE0 represent high data error rate of the memory cells being evaluated, while weak error regions WE1 and WE0 represent low data error rate of the memory cells being evaluated.
Unlike the single-Level Cell of fig. 6, the present embodiment of fig. 7 shows a Triple-Level Cell (TLC) that can store three bits of data, that is, the reference in the embodiment refers to "the Cell can store N bits of data", where N is 3 and 2N is 23 is 8 for the three-Level Cell, as shown in fig. 7, there are four sets of two curves, i.e., logic 1 and logic 0, as shown in fig. 6.
In addition, the Multi-Level Cell (MLC) can store two bits of data, N is 2, 2N is 22 is 4, there are two sets of two curves like logic 1 and logic 0 shown in fig. 6, the Quad-Level Cell (QLC), N is 4, 2N is 24 is 16, there are eight sets of two curves like logic 1 and logic 0 shown in fig. 6.
Please refer to fig. 8, which is a three-dimensional schematic diagram of the achievable log probability ratio analyzed by clustering in a specific scale interval according to the present invention. Referring to the method steps of the above embodiment, after different sensing voltages are supplied, a strong correct region, a weak correct region, a strong error region and a weak error region are divided, and a plurality of strong correct ratios and a plurality of strong error ratios are calculated according to the divided regions, and log probability ratios of various ratios are calculated. As shown in fig. 8, each axis represents N pairs of log probability ratios LLR1 to LLRN acquired by N sensing, and circles represent the acquired LLR groups, each group having a plurality of LLR values.
Without being limited to the number of LLR groups shown in fig. 8, the sensing voltage values can be sequentially increased or decreased, and the area size of the defined memory state can be adjusted to obtain different SCR and SER ratios. For example, the implementability LLR values can be analyzed from the LLR groups by using a clustering method for the specific ratio intervals of the SCR and the SER in the NAND Flash nonvolatile memory or the specific ratio intervals of the SCR and the SER desired by the user, as the input of the decoder in step S503 above.
It should be understood that the steps mentioned in the embodiments of the present invention may be executed in any order, or some of the steps may be executed simultaneously, according to the operation requirements.
The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.
Claims (9)
1, A method for detecting a storage status of a solid-state storage device, the solid-state storage device comprising a plurality of memory cells, the method for detecting the storage status of the solid-state storage device comprising the steps of:
setting a plurality of sensing voltages with different voltage values, wherein the plurality of sensing voltages comprise a low sensing voltage, a middle sensing voltage and a high sensing voltage, the low sensing voltage is smaller than the middle sensing voltage, and the high sensing voltage is larger than the middle sensing voltage;
applying the middle sensing voltage to each of the memory cells, and then applying the other sensing voltages to each of the memory cells;
comparing the threshold voltage of each memory cell with the sensing voltages to define a plurality of storage states, wherein the storage states include a strong correct region, a weak correct region, a strong error region and a weak error region;
calculating the number of the plurality of memory cells per regions in the strong correct region, the weak correct region, the strong error region, and the weak error region;
calculating the number of the plurality of memory units of the strong correct area, wherein the number of the plurality of memory units accounts for the strong correct proportion of the number of the plurality of memory units of the sum of the strong correct area and the weak correct area;
calculating the number of the plurality of memory cells of the strong error area, and the strong error ratio of the number of the plurality of memory cells occupying the sum of the strong error area and the weak error area; and
generating a log probability ratio based on the strong correct proportion and the strong error proportion.
2. The method of claim 1, wherein a difference between the lower sensing voltage and the middle sensing voltage and a difference between the upper sensing voltage and the middle sensing voltage are the same.
3. The method of claim 1, further comprising the steps of, for the memory cell having bit value of logic 1:
applying the middle sensing voltage to each memory cell;
comparing whether the threshold voltage of each memory unit is smaller than the median sensing voltage, if so, judging that the memory unit is logic 1, and if not, judging that the memory unit is logic 0;
applying the low sensing voltage to each of the memory cells;
comparing whether the threshold voltage of each memory unit is smaller than the low-level sensing voltage, if so, judging that the memory unit is logic 1, and if not, judging that the memory unit is logic 0;
applying the high sensing voltage to each of the memory cells;
comparing whether the threshold voltage of each memory unit is smaller than the high-level sensing voltage, if so, judging that the memory unit is logic 1, and if not, judging that the memory unit is logic 0;
defining the memory cell with the threshold voltage smaller than the low sensing voltage to belong to the strong correct region;
defining the memory cell with the threshold voltage larger than the low bit sensing voltage and smaller than the middle bit sensing voltage to belong to the weak correct region;
defining the memory cell with the threshold voltage larger than the middle sensing voltage and smaller than the high sensing voltage to belong to the weak error region; and
defining the memory cell with the threshold voltage larger than the high sensing voltage as belonging to the strong error region.
4. The method of claim 1, further comprising the steps of, for the memory cell having bit value of logic 0:
applying the middle sensing voltage to each memory cell;
comparing whether the threshold voltage of each memory unit is greater than the median sensing voltage, if so, judging that the memory unit is logic 0, and if not, judging that the memory unit is logic 1;
applying the high sensing voltage to each of the memory cells;
comparing whether the threshold voltage of each memory unit is larger than the high-level sensing voltage, if so, judging that the memory unit is logic 0, and if not, judging that the memory unit is logic 1;
applying the high sensing voltage to each of the memory cells;
comparing whether the threshold voltage of each memory unit is larger than the low-level sensing voltage, if so, judging that the memory unit is logic 0, and if not, judging that the memory unit is logic 1;
defining the memory cell with the threshold voltage larger than the high sensing voltage to belong to the strong correct region;
defining the memory cell with the threshold voltage larger than the middle sensing voltage and smaller than the high sensing voltage to belong to the weak correct region;
defining the memory cell with the threshold voltage larger than the low bit sensing voltage and smaller than the middle bit sensing voltage to belong to the weak error region; and
defining the memory cell with the threshold voltage smaller than the low sensing voltage as belonging to the strong error region.
5. The method for detecting the storage state of the solid-state storage device according to claim 1, further comprising the steps of:
adjusting voltage values of the lower sensing voltage and the upper sensing voltage applied to the plurality of memory cells to adjust the log probability ratio.
6. The method for detecting the storage state of the solid-state storage device according to claim 1, further comprising the steps of:
the sensing voltages applied to the memory cells are determined based on the desired amount of area of the memory states.
7. The method for detecting the storage state of the solid-state storage device according to claim 1, further comprising the steps of:
obtaining the bit quantity which can be stored by each memory unit; and
the sensing voltages applied to the memory cells are determined based on the amount of bits that the memory cells can store.
8. The method for detecting the storage state of the solid-state storage device according to claim 1, further comprising the steps of:
inputting or more bit values stored in each memory cell to a decoder;
decoding the or more bit values of each of the memory cells using the decoder, and
judging whether the or more bit values of each memory cell can be successfully decoded by the decoder, if so, judging that the or more bit values stored by the memory cells are correct, and if not, judging that the or more bit values stored by the memory cells are wrong.
9. The method for detecting the storage status of a solid-state storage device according to claim 8, further comprising the steps of:
inputting said log probability ratio to said decoder; and
decoding or more bit values with the decoder in a decoding process including the corresponding log probability ratios.
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| TW202008376A (en) | 2020-02-16 |
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