CN110730956B - 用于降低存储器系统中的页面迁移开销的机制 - Google Patents

用于降低存储器系统中的页面迁移开销的机制 Download PDF

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Publication number
CN110730956B
CN110730956B CN201880038630.4A CN201880038630A CN110730956B CN 110730956 B CN110730956 B CN 110730956B CN 201880038630 A CN201880038630 A CN 201880038630A CN 110730956 B CN110730956 B CN 110730956B
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pages
memory
page
buffer
memory access
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CN110730956A (zh
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靖子·埃克特
蒂鲁文加丹·维贾亚拉加万
加布里埃尔·H·洛
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
CN201880038630.4A 2017-06-19 2018-06-14 用于降低存储器系统中的页面迁移开销的机制 Active CN110730956B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/626,623 2017-06-19
US15/626,623 US10339067B2 (en) 2017-06-19 2017-06-19 Mechanism for reducing page migration overhead in memory systems
PCT/US2018/037460 WO2018236657A1 (en) 2017-06-19 2018-06-14 Mechanism for reducing page migration overhead in memory systems

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Publication Number Publication Date
CN110730956A CN110730956A (zh) 2020-01-24
CN110730956B true CN110730956B (zh) 2024-01-09

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US (1) US10339067B2 (enExample)
EP (1) EP3642722B1 (enExample)
JP (1) JP6928123B2 (enExample)
KR (1) KR102350539B1 (enExample)
CN (1) CN110730956B (enExample)
WO (1) WO2018236657A1 (enExample)

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US11620233B1 (en) * 2019-09-30 2023-04-04 Amazon Technologies, Inc. Memory data migration hardware
US20210157647A1 (en) * 2019-11-25 2021-05-27 Alibaba Group Holding Limited Numa system and method of migrating pages in the system
US12253961B2 (en) * 2019-12-27 2025-03-18 Advanced Micro Devices, Inc. Staging memory access requests
US11698859B2 (en) * 2019-12-27 2023-07-11 Sk Hynix Nand Product Solutions Corp. Direct map memory extension for storage class memory
CN114064519B (zh) * 2020-08-03 2024-10-18 美光科技公司 高速缓存的元数据管理
US12130754B2 (en) * 2020-08-17 2024-10-29 Intel Corporation Adaptive routing for pooled and tiered data architectures
KR20220051546A (ko) 2020-10-19 2022-04-26 삼성전자주식회사 전자장치 및 그 제어방법
US12314178B2 (en) * 2020-12-26 2025-05-27 Intel Corporation Management of distributed shared memory
US11789649B2 (en) 2021-04-22 2023-10-17 Nvidia Corporation Combined on-package and off-package memory system
CN118715510A (zh) * 2022-02-23 2024-09-27 华为技术有限公司 使用驱动的内存映射
US12131033B2 (en) * 2023-02-01 2024-10-29 Dell Products L.P. Extending flash media endurance
WO2024190078A1 (ja) * 2023-03-15 2024-09-19 ソニーグループ株式会社 メモリコントローラ、記憶装置およびコンピュータシステム
US12259858B1 (en) * 2023-12-28 2025-03-25 Jpmorgan Chase Bank, N.A. Method and system for migrating database content onto new database infrastructure

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Publication number Publication date
KR102350539B1 (ko) 2022-01-14
EP3642722B1 (en) 2023-08-16
WO2018236657A1 (en) 2018-12-27
KR20200010504A (ko) 2020-01-30
EP3642722A1 (en) 2020-04-29
CN110730956A (zh) 2020-01-24
US10339067B2 (en) 2019-07-02
EP3642722A4 (en) 2021-03-24
JP2020524339A (ja) 2020-08-13
US20180365167A1 (en) 2018-12-20
JP6928123B2 (ja) 2021-09-01

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